KR100454652B1 - Main storage of highly pipelined bus system on multiprocessor system using shared memory - Google Patents

Abstract

PURPOSE: A main storage of a highly pipelined bus system on a multiprocessor system using a shared memory is provided to perform data exchange by occupying faster system bus, and get to be compatible with cache read/write operation through the system bus of a processor having a reinforced cache function. CONSTITUTION: A memory bank(10) comprises the first and the second data bank(B1,B2) accessed by a 16-byte unit. A buffer(20) temporarily stores data. An input queue(21) temporarily stores an address, a transfer type, and the data. An output queue(22) temporarily stores the data read from the memory bank. A memory controller(30) controls data input/output of the memory bank. A data redundancy controller(31) transfers the data of the output queue to a board requesting the data. A response controller(32) responds to a request from a system bus. An error detecting/correcting part(40) checks/corrects a data error when the memory bank is read. An interface(50) connects the main storage to the highly pipelined bus system.

Description

Main memory of hi-fi bus system

The present invention relates to a main memory device connected to a hi-fi bus system, which is one of shared buses used as an information path between a processor and a memory in a system having a multiprocessor structure using a shared memory, and more particularly, a cache function is provided. A hi-fi bus system that performs data exchange with a hi-fi bus, which further comprises two arbitration signals that control bus occupancy in synchronization with clock frequencies above 30 MHz and in response to shorter external access cycles through the bus of the more advanced processors. It is about main memory of.

In a system having a multiprocessor structure using a shared memory, a high-performance bus is a high-performance pipelined bus, which is designed as a shared bus to be used as an information path between a processor and a memory.

In a multiprocessor architecture using shared memory, a system bus is a bus that supports multiple processors in each part of the bus, such as data transfer protocols, transfer rates, arbitration methods, and interrupts. In addition, in order for the performance of the multiprocessor to be high performance, the system bus also provides the performance and functions that are compatible with it. For this, data transfer capability, reliability of data transfer, system configuration capability, and function for system maintenance should be considered.

Data transmission characteristics according to the main specifications of the hi-fi bus are shown in the following table.

Hi-Fi Bus Specification

As shown in the table, the conventional hi-fi bus operates in synchronization with 16.5 MHz, and the conventional processor mounted on the processor board connected to the hi-fi bus was an intel pentium processor. Since the Pentium processor has a structure of processing lines of 64 bytes, a cache write / read operation is performed by four bus cycles (4 x 16 bytes = 64 bytes) on the system bus.

However, according to the high performance and speed of the processor, a Pentium pro processor is introduced, and as the internal Pentium Pro processor is expanded, the externally accessed data is reduced to a structure that processes 32 bytes of lines. Thus, there is a need for a cache write / read operation through the system bus to be performed by two bus cycles (2 × 16 bytes = 32 bytes). In addition, the conventional hi-fi bus system operates in synchronization with the bus clock of 16.5 MHz, but also needs to increase the frequency of the operation clock in order to design a faster system bus in response to an improved processor such as the Pentium Pro processor. It came up.

In addition, there is a need to develop a main memory device having a memory method different from the conventional method, which is compatible with cache write / read operation through the system bus of the Pentium Pro processor and can be connected to a bus system having a higher clock frequency.

Accordingly, an object of the present invention is to provide a main memory device of a hi-fi bus system that occupies a faster system bus and performs data exchange.

Another object of the present invention is to provide a main memory device of a hi-fi bus system that is compatible with cache read / write operations through a system bus of a cache-enhanced processor.

1 is a schematic diagram showing a preferred embodiment of a main memory device of a hi-fi bus system according to the present invention;

2 is an address flowchart of a main memory device of a hi-fi bus system according to the present invention;

3 is a data flow diagram of a main memory device of a hi-fi bus system according to the present invention;

4 is a timing diagram of main signals according to address and data transfer of a main memory device of a hi-fi bus system according to the present invention, (a) in a write mode, and (b) a timing diagram for each part in a read mode.

※ Explanation of code for main part of drawing

B ₁ : first data bank B ₂ : second data bank

10: memory bank (DRAM) 20,20 ₁ , 20 ₂ : data buffer

21: input queue 22,22 ₁ , 22 ₂ : output queue

30: memory controller (MEMC) 31: data feedback controller (DRC)

32: Response Controller (RPC) 40,40 ₁ , 40 ₂ : Error Detection Corrector (EDC)

41: memory register 42: parity check

43,43 ₁ , 43 ₂ : parity generator 50: interface

The main memory device of the hi-fi bus system according to the present invention for achieving the above object, input and output means for performing data exchange with the hi-fi bus system in synchronization with a clock frequency of 30 MHz or more; Storage means for storing data; And control means for controlling data movement between the input / output means and the storage means, wherein the input / output means is connected to a hi-fi bus system further comprising a data synchronizing signal and an address synchronizing signal for mediating bus occupancy. Characterized by performing data exchange with the bus,

The main memory device of the hi-fi bus system according to the present invention is characterized in that the control means controls the data movement between the input / output means and the storage means by two local data bus cycles.

In the main memory of the hi-fi bus system according to the present invention configured as described above, the hi-fi speed is increased to a frequency of 30 MHz or more in accordance with the improvement of the performance of an external processor in which the input / output means writes / reads data on the memory of the main memory. It is connected to the bus system and requests the occupancy of the hi-fi bus according to the state of the data synchronizing signal and the address synchronizing signal which mediates bus occupancy.

When an external processor occupies a hi-fi bus and performs a cache read operation, a designated address is first input through the input / output means through the bus. The control means reads the designated address, reads data in the storage means corresponding to the address, and instructs the input / output means to occupy the bus. The input / output means grasps the state of the data synchronization signal, and then occupies the bus and notifies the control means, and the control means transmits the previously read data on the bus through the input / output means by two consecutive local data cycles. Will be loaded.

In the cache write operation of an external processor, the control means receives data to be loaded on the bus at the same time as the address through the input / output means and stores the data by two consecutive local data cycles at the designated storage means. This will be controlled.

Hereinafter, the configuration and operation of a preferred embodiment of the main memory device of the hi-fi bus system according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic configuration diagram of a preferred embodiment of a main memory device of a hi-fi bus system according to the present invention, and includes a first data bank B ₁ and a second data bank B ₂ to which data is accessed in units of 16 bytes. A memory bank 10; A buffer 20 for temporarily storing data; An input queue 21 for temporarily storing an address, a transmission type, data, and the like; An output queue 22 for temporarily storing data read from the memory bank 10; A memory controller (MEMC) 30 for controlling data input and output of the memory bank 10; A data feedback controller (DRC) 31 for transmitting the data of the output queue 22 to the requesting board; A response controller (RPC) 32 that responds to requests from the system bus; An error detection corrector (EDC) 40 that checks for and corrects errors in data when reading the memory bank 10; And an interface unit 50 for connecting the main memory device to the hi-fi bus system.

In the main memory device of the hi-fi bus system according to the present invention configured as described above, in a data write mode from an external processor (not shown) to the memory bank 10 on the main memory device, the data to be written is written together with the address to be written. It is temporarily stored in the input queue 21 via a system bus and the interface unit 50, and the response controller 32 determines whether the temporarily stored data is valid data and whether it is data to be processed by itself. If it is determined that it is valid data, it responds to the processor requesting a write through the interface unit 50 and the hi-fi system bus and informs the memory controller 30 of the write request. When the write operation is a cache cycle, the memory controller 30 transfers the data of the input queue 21 through the buffer 20 into the input queue 21 at a designated address by two local data bus cycles. Write transfers are made to the corresponding first data bank B ₁ and the second data bank B ₂ , respectively.

In the read mode of the external processor, the processor sends an address and read information to the main memory. If the information is temporarily stored in the input queue 21 and is valid information as in the write mode, the response controller 32 responds to the processor and informs the memory controller 30 of this. The memory controller 30 reads data in the memory bank 10 corresponding to an address stored in the input queue 21 by two local data bus cycles and temporarily stores the data in the output queue 22. . At this time, the error correction means 40 searches for and corrects an error of the read data, and when the normal operation is completed, the data feedback controller 31 notifies the external processor that the read data is ready and transmits the data to the processor. Done.

The data transfer between the main memory and the external processor board of the hi-fi bus system operating as described above will be described in more detail with reference to FIGS. 2 and 3.

Fig. 2 is a block diagram embodying Fig. 1 regarding the address flow in the data write / read operation according to the present invention, comprising: a memory address section 41 for confirming a memory address; And a data parity check unit 42 for determining whether the error is detected or not. FIG. 3 is a block diagram embodying the configuration of FIG. 1 in relation to the data flow during the data write / read operation. And a data parity generator 43 for generating parity for determining whether the error is detected.

The address input from the hi-fi system bus via the interface unit 50 is modified into a local address in the response controller 32 as necessary, and then input into the input queue 21, and the memory controller 30 The address from the input queue 21 is used to generate an address to drive the actual memory bank 10. The address is supplied to the first data bank B ₁ and the second data bank B ₂ via two address buffers 20 ', respectively. When the error detection corrector 40 detects a plurality of data errors, the memory address unit 41 stores the corresponding address so that the memory controller 30 may retry a read or write operation with respect to the address. The parity check unit 42 checks the parity of the address supplied to the memory bank 10 to search for an error in the address.

Data input from the hi-fi bus system via the interface unit 50 is sequentially input to the input queue 21, and data passed through the input queue 21 is stored in the data buffers 20 ₁ and 20 ₂ . The data buffers 20 ₁ and 20 ₂ are divided into respective banks B ₁ and B ₂ , so that at the time of write transfer, each data is stored in the corresponding banks B ₁ and B ₂ by two local data bus cycles. Data buffers 20 ₁ and 20 ₂ are stored separately. In the block write transfer, 32 bytes of data, 16 bytes each are simultaneously stored in the memory bank 10 through the data buffers 20 ₁ and 20 ₂ .

On the other hand, during read transfer, as described above, data read from the memory bank 10 by the previously input address is temporarily input to the output queues 22 ₁ and 22 ₂ by local bus cycles. In this case, the parity generating unit 43 generates a parity corresponding to the data and the first error detection corrector 40 to determine the error of the data by using this, the error-free confirmed when the output queue (22 _1, 22 ₂ Data is output to the hi-fi bus. Even during read transfer, the processing queue is shortened by setting the output queues 22 ₁ and 22 ₂ separately for each bank and performing 32-byte block reads at once.

FIG. 4 is a timing diagram of parts of an address, data, and control signal on a hi-fi bus when a read / write operation of the memory device is performed. FIG. 4 is a timing diagram of parts of a data single / block write transfer. (B) is a timing diagram for each part of data single / block read transfer. 'ABSYNC-' in the drawing is an address synchronization signal according to the present invention, 'ABRQ-' is an address bus request signal, 'Addr' is an address, 'DBINH-' is a data prohibition signal, and 'DBSYNC-' is Data synchronization signal according to the invention, 'DBRQ-' is the data request signal, 'Data' corresponds to the data.

Referring to the data write transfer process with reference to the waveform diagram of each part of Fig. 4, first, an external processor transfers an address specifying a data and a location to store the data to a storage device via a hi-fi bus. After checking the state of the address synchronization signal ABSYNC- for occupancy, if it is inactive, the address synchronization request signal ABRQ- is simultaneously sent to the active state to request the use of the address bus. At the same time, since the data to be stored on the clock is transmitted immediately after the address is transmitted, the data prohibition signal DBINH- is activated to prevent the data bus from being occupied by other boards. Lasts for-). At the same time as the address bus request signal ABRQ- is inactively switched, an address Addr to which data is to be written is transmitted, followed by data.

In the data write operation as described above, since the address and data are simultaneously transmitted in one cycle, the processor board does not need to separately occupy the data synchronization signal DBSYNC- and the data request signal DBRQ-. The upper part of (A) is a single write mode of data, and the lower part is a block write mode of data, and there are two data transfer processes in the block write mode corresponding to the cache cycle of the processor.

Referring to the data read transfer process, as shown in (b) of FIG. 4, the data in the designated address of the memory bank 10 of the storage device is brought to the processor. First, the memory in which the data to be read by the processor is stored is stored. The address on the bank 10 is transferred to the storage device via the hi-fi bus by the same process as the address occupancy described above. The address is read by the main memory in accordance with the above-described process, and the data in the designated address is transmitted to the processor board. First, after checking the state of the data synchronization signal DBSYNC-, if it is inactive, the address is switched to the active state and The data request signal (DBRQ-) is sent while data is prevented from being occupied by the board. In the read mode, as in the write mode, a block read has two data transfer processes.

Conventionally, the occupancy arbitration of the address and data bus has been achieved by the address request signal ABRQ- and the data request signal DBRQ-, but as the operation clock of the hi-fi bus system is increased from 16.5 MHz to 33 MHz, Since the bus arbitration is not possible with one clock of the address request signal ABRQ- and the data request signal DBRQ-, the address and data buses are controlled by one clock of the address synchronization signal ABSYNC- and the data synchronization signal DBSYNC-. Is occupied, and a response to the request (ACK) is made during the address request signal (ABRQ-) and the data request signal (DBRQ-) of the clock to be a bus arbitration.

The main memory device of the hi-fi bus system according to the present invention configured and acts as described above improves the speed by increasing the synchronization frequency of the hi-fi bus connected thereto according to the speed of the processor, and thus the main memory device at the time of data write / read transfer. By configuring the internal write / read operation of the processor to be suitable for the processor, it is a more practical and efficient invention that improves the overall operation speed when transferring data between the processor and the main memory.

Claims (4)

Input / output means connected to a hi-fi bus and inputting or intermitting the hi-fi bus with an address signal and a data signal synchronized with a clock frequency of 30 MHz or more, or outputting the data separately for each bank; Storage means for separately storing the input data for each bank; And And a control means for controlling data movement between the input / output means and the storage means. The method of claim 1, And said control means controls said data movement by two local data bus cycles. The method of claim 1, The main memory device of the hi-fi bus system, characterized in that for storing the data received from the high-fiber bus for each bank at the same time by temporarily storing the corresponding buffer for each bank. The method of claim 1, The input / output means includes an out queue for each bank, and outputs the data separately stored in the storage means to the hi-fi bus for each bank simultaneously.

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