JPH11115258A - Apparatus and method for controlling output - Google Patents

Abstract

PROBLEM TO BE SOLVED: To minimize a shift of a generation estimation time of output data and an actual generation time of the output data, by providing a read means for reading stored data with a pre-read function of reading input data in advance, and providing a storing means with a delay write function of writing conversion data with delay. SOLUTION: When print data are sent from a host computer 200, the CPU 101 being in a standby state for the print data stores the data temporarily, for instance, in a receiving buffer area 104a of a DRAM 104 via a DMAC 106, a DRAM interface 105 under a direct memory access control. When a display list of one page is formed, bit map data stored in a bit map memory area 104c are caught via a pre-read circuit 108, etc., and modified by a plot processor 107. Modified data are returned to be written in the bit map memory area 104c via a delay write circuit 109, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output control method and apparatus connected to an output device for converting input data into output data in accordance with the output format of the output device and outputting the converted output data.

[0002]

2. Description of the Related Art When generating a print image of a page printer, a read-modify-write sequence is repeated for data in a bitmap memory in accordance with a display list, and a desired image is drawn on the bitmap memory. Drawing processors have come to be used. For example, there is an example in which a printer controller for controlling a page printer or the like that performs banding processing also includes this kind of drawing processor. If it is determined that the print process cannot be completed in time, print process control has been performed using a workaround such as shifting to full paint processing.

[0003]

However, in the above-described conventional example, if the prediction of whether or not the banding process can be performed in time for the engine speed is incorrect, an overrun has occurred. A major cause of this phenomenon is that when the drawing processor accesses the memory, it has to wait for the memory access of other devices, and the drawing sequence is delayed by the amount of time waited. This is because even if there is a margin in the bandwidth of the memory bus, the drawing time is greatly increased, and the drawing time prediction and the actual drawing time are greatly different.

[0004]

SUMMARY OF THE INVENTION The present invention has been made for the purpose of solving the above-mentioned problems, and has, for example, the following arrangement as means for solving the above-mentioned problems.

That is, an output control device connected to an output device for converting input data into output data in accordance with an output format of the output device and outputting the output data, wherein a storage means for storing input data; Converting means for converting the input data stored in the output device into output data in accordance with an output format to the output device; reading means for reading the input data stored in the storage means and sequentially outputting the input data to the converting means; Storage means for storing conversion data in the conversion means in the storage means, wherein the reading means has a pre-reading function of pre-reading input data in advance, and the storage means has a delay write function of writing the conversion data with a delay. It is characterized by having.

For example, the conversion means reads the input data through the reading means, modifies the read data in accordance with a conversion list to generate conversion data, and stores the generated conversion data through the storage means. A series of controls stored in the means are repeatedly and sequentially executed.

Also, for example, the input data is bitmap data, the read means and the storage means read and store data with the storage means by direct memory access control, and the read means at least next performs the conversion. A predetermined amount of bitmap data requested to be read by the means is pre-read from the storage means in advance by a predetermined amount, and is ready to be supplied by a request from the conversion means, and the storage means stores the converted data in the conversion means. It is characterized in that the latch data is written once the data is latched and the storage means can be written.

Further, for example, the reading means has a pre-reading function of pre-reading input data in units of one line.
The conversion means generates conversion data on a line-by-line basis. Alternatively, the input data is bitmap data from a data output device that supplies print information, and the output device is a page printer.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of a printer controller according to an embodiment of the present invention.

In FIG. 1, when power is turned on, a CPU 101 controls a ROM interface 102 to
ROM 1 in which a control program for PU 101 is stored
03, a necessary program is read, the system is initialized, and a transition is made to a state of waiting for print data from the host computer 200, which is a print data supply source.

The print data from the host computer 200 is sent to a printer interface 110 capable of parallel data transfer. The print data sent to the printer interface 110 is stored in the ROM 103 and the DRAM by the direct memory access control.
DM that controls writing and reading of data with the 104
The data is temporarily stored in, for example, the reception buffer area 104a of the DRAM 104 via the AC 106 and the DRAM interface 105 for controlling the DRAM 104.

The print data stored in the DRAM 104 is converted by the CPU 101 into a display list that can be processed by the drawing processor 107.
4, for example, in the display list area 104b. Note that the drawing processor 10 according to the embodiment of the present invention.
Reference numeral 7 denotes a printer which draws and generates a print image to be printed out by the printer engine 300 capable of printing out one page at a time, and generates a DRAM 104 according to the display list stored in the display list area 104b.
The read-modify-write sequence is repeated for the data in the bitmap memory area 104c, and a desired image is drawn in the bitmap memory area 104c.

For this reason, when a display list for one page is created, the CPU 101
7 is started to start the banding process. The drawing processor 107 converts the bitmap data stored in the bitmap memory area 104c secured on the DRAM 104 according to the display list for one page stored in the display list area 104b of the DRAM 104 into the DRAM interface 105, D
The image is acquired through the MAC 106 and the prefetch circuit 108, temporarily stored in the buffer area 104d and then modified (drawn), and the modified image data is stored in a corresponding area of the bitmap memory area 104c under the following control. Start processing.

Here, the prefetch circuit 108 prefetches the next bitmap data following the first bitmap data and prepares for the next data request from the drawing processor 107. The drawing processor 107 modifies the acquired bitmap data according to the display list. The modified data is sent to the delay write circuit 10.
9, DMAC 106, DRAM interface 105
Through the bitmap memory area 10 of the DRAM 104
4c.

A specific description will be given. Delay write circuit 109
When bitmap data to be rewritten is sent from the drawing processor 107, the bitmap data is first latched. Then, an ACK signal is returned to the drawing processor 107 before the end of the write cycle of the DRAM 104 to instruct the drawing processor 107 to execute the next processing.
The bitmap data to be rewritten from the drawing processor 107, which has been latched at the timing when the M bus is available and writing is enabled, is written to the bitmap memory area 104c of the DRAM 104.

In this way, the drawing processor 107
After drawing the band, the drawing processor 107 generates an interrupt signal to notify the CPU 101 that drawing of one band is completed. CPU that knows the end of band drawing
The engine interface 101 instructs the drawing processor 107 to draw the next band, and transfers the band after drawing to the print engine.
Start 1

The engine interface 111 activated by the CPU 101 transfers, via the DMAC 106 and the DRAM interface 105, one band for which rendering of bitmap data stored in the bitmap memory area 104c of the DRAM 104 has been completed to the printer engine 300. I do.

Hereinafter, the above control is repeated, and if necessary, drawing of the print data is performed. When the drawing is sequentially completed, the print data is sent from the printer engine 300 and printed out.

FIG. 2 shows D in the embodiment of the present invention.
FIG. 2 is a schematic diagram showing a configuration of a bitmap memory area 104c in a RAM 104. The drawing processor 107 has a
0, a1, a2, a3, b0, b1, b2, c0, c
The bitmap data is modified in the order of words 1, c2, c3, c4,... According to the display list.

The words a0, a1, a shown in FIG.
2, a3, b0, b1, b2, c0, c1, c2, c
Are output data for one line from the printer engine 300, for example. However, the pre-read data (processing unit in the drawing processor 107) is not limited to the data amount for one line described above.
It may be a line or a half line, and is not limited at all.

FIG. 3 shows a DR when the drawing processor 107 performs drawing on the bitmap data shown in FIG.
5 is a timing chart showing peripheral signals related to AM104.

As shown in the upper and middle sections of FIG. 3, in the prior art, read-modify-write-read-modify-write was sequentially and sequentially repeated. In the case where the drawing time is delayed due to access by a device or the like, the drawing time is delayed by the time that has been delayed and waited.

However, in the embodiment of the present invention shown in the lower part, after reading the data of a0 to a3, before writing back the data of a0 to a3, the subsequent data of b0 to b3 is read by the prefetch circuit 108. Therefore, even if the write-back of a0 to a3 is delayed by the DRAM access of another device, the writeback of the next b0 to b2 does not have to be delayed as compared with the related art. As a result, the problem unlike the related art does not occur, the difference between the predicted drawing time and the actual drawing time can be minimized, and the occurrence of print overrun can be prevented.

FIG. 4 is a flowchart showing a memory operation sequence in the prefetch circuit 109. Less than,
The details of the read control of the prefetch circuit 109 in the embodiment of the present invention will be described with reference to FIG.

First, in step S401, it is determined whether or not drawing has been started, and the process waits until drawing is started. When the drawing is started, the process proceeds from step S401 to step S402.
The DRAM interface 105 is activated to start a memory cycle sequence, the first bitmap data is obtained from the DRAM 104, and the buffer area 10
4d.

Next, in step S403, it is determined whether the drawing is completed. If the drawing has been completed in step S403, the process returns to step S401, and returns to the next drawing start waiting state.

On the other hand, if drawing is not completed in step S403, the flow advances to step S404 to determine whether a line break has occurred. If a line feed (line feed) has not occurred in step S403, the flow advances to step S405 to determine whether or not there is a free area in the buffer area for storing the next data on the same line. If there is no free space, the process proceeds to step S406, and it is determined whether a buffer for storing the leading data of the next line is free. Step S406
If there is no free space for storing the head data of the next line, the process returns to step S403 and waits for the end of the next drawing.

On the other hand, if there is a free space in the buffer for storing the head data of the next line in step S406, the flow advances to step S407 to calculate the head address of the next line.
Then, in the subsequent step S408, the memory cycle sequence is activated, the DRAM interface 105 is activated, the first bitmap data of the next line is acquired from the DRAM 104, and stored in the buffer area 104d. Then, the process returns to step S403, and waits for the end of the next drawing.

On the other hand, if there is a free space in the buffer for storing the next data on the same line in step S405, the process proceeds to step S409, and the address is incremented. Subsequently, at step 410, the memory cycle sequence is started, and the DRAM interface 105 is activated.
To acquire the next data from the DRAM 104 and store it in the buffer area 104d. And step S40
Return to step 3 and wait for the end of the next drawing.

On the other hand, if a line break has occurred in step S404, the flow advances to step S411 to read the leading data of the next line in the bitmap memory area 104c and store the next data on the next line. It is stored in the area 104d. Then, in a succeeding step S412, the corresponding area in the buffer area 104 for storing the head data of the next line is cleared. Then, the process returns to step S403.

By controlling as described above, after reading the data of the area to be drawn in the bitmap memory area 104c, before the drawing to this area is completed (before write back), the data in the bitmap memory area 104c is read. Subsequent drawing data can be pre-read by the pre-reading circuit 108, and the difference between the predicted drawing time and the actual drawing time can be minimized.

Next, the interface control of the look-ahead circuit 108 with the drawing processor 107 in the embodiment of the present invention will be described with reference to FIG. FIG. 5 is a flowchart showing a drawing processor interface sequence of the look-ahead circuit in the embodiment of the present invention.

First, in step S501, it is determined whether or not drawing has started, and the process waits until drawing starts. When the drawing is started, steps S501 to S502 are performed.
Then, it is determined whether a data request from the drawing processor 107 has been received. If the data request has not come, the process waits for a data request to come in step S502.

If a data request is generated in step S502, the flow advances to step S503 to determine whether data is stored in the buffer area 104d (data buffer) of the DRAM 104. If data is stored in step S503, the process proceeds to step S505.

On the other hand, if no data is stored in step S503, the process proceeds to step S504, where the DRAM 10
4 waits for the transfer of the drawing data from the bitmap memory area 104c. When the data is transferred, the process proceeds to step S505.

In step S505, the data prefetched by the prefetch circuit 108 is sent to the drawing processor 107. Then, in a succeeding step S506, it is determined whether or not the drawing is completed. If the drawing is not completed, step S50
The process returns to the process of waiting for the next data request after the second. On the other hand, if the drawing is completed, the process returns to the process of waiting for drawing to start in step S501.

The drawing processor 107 modifies the bitmap data obtained by the above control according to the display list, and writes the modified data back to the bitmap memory area 104c of the DRAM 104 via the delay write circuit 109, the DMAC 106, and the DRAM interface 105.

The operation of the delay write circuit 109 will now be described with reference to FIG.
This will be described with reference to FIG. FIG. 6 is a flowchart showing the operation control of the delay write circuit 109.

First, in step S601, it is determined whether or not the drawing processor 107 has finished modifying the bitmap data and has output a write-back write DMA request for requesting writing back to the bitmap memory area 104c. Wait for the back DMA request to be output.

If a DMA request has occurred, step S6
From step 01, the flow advances to step S602 to output a write DMA request to the DMAC 106. Subsequently, step S603
Latches the bitmap data to be written back from the drawing processor 107 to the drawing processor 107.
Returns K. Next, in step S604, it is checked whether an ACK has been received from the DMAC 106 in response to the write DMA request output in step S602, and the system waits for an ACK to be sent.

If ACK is returned in step S604, the flow advances to step S605 to write bitmap data to be written back from the drawing processor 107 to the DRAM 104 under the control of the DMAC 106. Then, returning to step S601, the next drawing processor 10
7 and waits for a write-back DMA request, and repeats the above processing.

As described above, according to the embodiment of the present invention, when the drawing processor 107 reads out the drawing data from the bitmap memory area 104c of the DRAM 104 and adds necessary modifications to write back, Even if the memory access time fluctuates due to contention for memory access with the device, the difference between the predicted drawing time and the actual drawing time due to the extension of the drawing sequence at this time can be minimized, and print overrun can be achieved. Can be prevented from occurring.

That is, in order for the drawing processor 107 to minimize the waiting time due to contention for memory access, the prefetch circuit 108 for bitmap data and the delay write circuit 10 as a delay writeback circuit for bitmap data.
9 is provided between the drawing processor 107 and the DMAC 106 serving as a memory interface circuit, thereby reducing the state in which the drawing processor 107 waits in competition with the memory access of another device, and reduces the difference between the predicted drawing time and the actual drawing time. By almost eliminating it, occurrence of overrun can be suppressed.

[0044]

[Other Embodiments] Even if the present invention is applied to a system including a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), an apparatus (for example, a copying machine) Machine, facsimile machine, etc.).

Another object of the present invention is to provide a storage medium storing a program code of software for realizing the functions of the above-described embodiments to a system or apparatus, and to provide a computer (or CPU) of the system or apparatus.
And MPU) read out and execute the program code stored in the storage medium.

In this case, the program code itself read from the storage medium realizes the function of the above-described embodiment, and the storage medium storing the program code constitutes the present invention.

Examples of the storage medium for supplying the program code include a floppy disk, hard disk, optical disk, magneto-optical disk, CD-ROM, and CD-ROM.
R, a magnetic tape, a nonvolatile memory card, a ROM, and the like can be used.

When the computer executes the readout program code, not only the functions of the above-described embodiment are realized, but also the OS (Operating System) running on the computer based on the instructions of the program code. ) May perform some or all of the actual processing, and the processing may realize the functions of the above-described embodiments.

Further, after the program code read from the storage medium is written into a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, based on the instructions of the program code, It goes without saying that the CPU included in the function expansion board or the function expansion unit performs part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

[0050]

As described above, according to the present invention, when generating output data such as print data, the time for reading the original data for generating the print data from the memory and the time for writing the generated data are reduced. Even if there is a fluctuation, the difference between the predicted time for generating the output data and the actual time for generating the output data can be minimized, and the output data can be supplied stably in accordance with the output control timing.

Therefore, even when the output data is output to a page printer, the output data can be supplied to the page printer at a predetermined timing, and it is possible to effectively prevent a problem such as a print overrun from occurring. Become.

[Brief description of the drawings]

FIG. 1 is a block diagram of a printer controller according to an embodiment of the present invention.

FIG. 2 is a schematic diagram showing a bit map memory area in the DRAM shown in FIG.

FIG. 3 is a timing chart showing an example of control timing when a drawing processor performs drawing in a bitmap memory.

FIG. 4 is a flowchart showing a memory operation sequence of the look-ahead circuit shown in FIG. 1;

FIG. 5 is a flowchart showing a drawing processor interface sequence of the look-ahead circuit shown in FIG. 1;

FIG. 6 is a flowchart showing an operation sequence of the delay write circuit shown in FIG. 1;

[Explanation of symbols]

 101 CPU 102 ROM Interface 103 ROM 104 DRAM 105 DRAM Interface 106 DMA Controller 107 Drawing Processor 108 Look-Ahead Circuit 109 Delay Write Circuit 110 Printer Interface 111 Engine Interface

Claims (9)

[Claims] 1. An output control device connected to an output device for converting input data into output data in accordance with an output format of the output device and outputting the output data, wherein a storage means for storing the input data; A conversion unit that converts the input data stored in the storage device into output data according to an output format to the output device; a reading unit that reads the input data stored in the storage unit and sequentially outputs the input data to the conversion unit; Storage means for storing the conversion data in the conversion means in the storage means, wherein the reading means has a pre-reading function of pre-reading the input data, and the storage means has a delayed write function for writing the conversion data with a delay. An output control device comprising: 2. The conversion means reads input data through the reading means, modifies the read data according to a conversion list to generate conversion data, and generates the conversion data through the storage means to the storage means. 2. The output control device according to claim 1, wherein a series of control operations stored in the output control device are repeatedly and sequentially executed. 3. The input data is bitmap data, wherein the read means and the storage means perform reading and storing of data with the storage means by direct memory access control, and the read means is at least next the conversion means. A predetermined amount of bitmap data requested to be read is pre-read from the storage unit in advance by a predetermined amount, and is ready to be supplied in response to a request from the conversion unit. The storage unit temporarily stores the conversion data in the conversion unit. 3. The output control device according to claim 1, wherein the latch data is written when the data is latched and becomes writable in the storage unit. 4. The apparatus according to claim 1, wherein said reading means has a pre-reading function of pre-reading input data in units of one line, and said converting means generates conversion data in units of one line. The output control device according to any one of the above. 5. The output control device according to claim 5, wherein the input data is bitmap data from a data output device that supplies print information, and the output device is a page printer. 6. An output control method in an output control device connected to an output device for converting input data into output data in accordance with an output format of the output device and outputting the converted data, wherein the storage means for storing the input data When the input data stored in the storage means is converted into output data in accordance with an output format by the output device, the input data stored in the storage means is read in advance in advance and the output An output control method, wherein when storing data in the storage means, the output data is delayed and held until the storage means can store the data. 7. The conversion into the output data, wherein the input data is pre-read from the storage means, the pre-read input data is modified according to a conversion list to generate output data, and the generated output data is stored in the storage means. 7. The output control method according to claim 6, wherein a series of control operations for delay writing the data is repeatedly and sequentially executed. 8. The output according to claim 6, wherein the input data is bitmap data, and reading and writing control with respect to the storage unit is performed by direct memory access control. Control method. 9. A storage medium storing a control procedure for realizing the function according to claim 1. Description: