JPH04333938A - Image storage device - Google Patents

Abstract

PURPOSE:To simultaneously write and read image data without requiring plural processings. CONSTITUTION:The image data to be written or read through plural data input/ output ports 2 to memory cells 1 are arbitrarily designated and based on a cycle select signal outputted from a timing controller 7, the cycle of write or read is controlled by switching the addresses of the image data to the memory cells 1. The switching of the addresses is handled by an address controller 9 based on the combination of a designated image number and the picture element address of the image data corresponding to this image number. In the case of reading, the phases of the respective image data to be read are arranged by executing the shift of shift registers 4 at the data input/output ports 2.

Description

[Detailed description of the invention]

[Purpose of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image storage device that allows image data to be simultaneously written and read from a storage element.

0002

2. Description of the Related Art For example, an image memory having one data input/output port is used as an image memory for storing image data such as medical images. However, the conventional image memory used in this case cannot write image data.
Since it has only one data input/output port for inputting and outputting data for reading and reading, at the same time when writing two images, for example, the first image (referred to as #1), the second image It is impossible to read out the image (referred to as #2). Therefore, by using two image memories, one of which is dedicated for writing and the other for reading, this drawback can be overcome, but this inevitably increases the hardware scale.

Therefore, by combining two image memories, one
By making it into one unit, it is possible to avoid an increase in the hardware scale. However, since such large capacity memories are now easily realized, it is easy to write two images to a memory device at the same time. Therefore, by simply combining a plurality of image memories into a unit, it is still impossible to perform simultaneous writing and reading operations as described above. Especially recently #
Operation to read images 1 and #2 at the same time and add them together (
This addition image (third image,
There is a need for an access technique that writes #3) on the fly, but this cannot be achieved using the conventional addressing method that sequentially accesses images.

Therefore, in order to avoid the above-mentioned drawbacks, for example, one pixel of image #1 is read out using the control operation of a CPU (central processing unit), and then one pixel of image #2 is read out. Timesure provides a method of performing simultaneous write and read operations using one data input/output port, such as reading out one pixel of the calculated image #3 and then writing one pixel of the calculated image #3. But like this 1
In the timesure method using two data input/output ports, three cycles are required in the above example (reading image #1) + (reading image #2) + (writing to image #3). , which increases the number of calculation cycles and complicates the processing.

[0005]

As described above, all conventional image memories have a problem in that it is impossible to simultaneously write and read image data without requiring complicated processing.

The present invention has been made in response to the above-mentioned problems, and it is an object of the present invention to provide an image storage device capable of simultaneously writing and reading image data without requiring complicated processing. This is the purpose. [Structure of the invention]

[0007]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides an image storage device that allows image data to be simultaneously written and read from a storage element, in which image data is input and output to and from a storage element. A plurality of data input/output ports, a plurality of shift registers provided at each data input/output port and each having a controllable number of shift stages so as to align the phases of each data, and controlling the write or read cycle of the storage element. a read/write controller that sends a signal to the storage element to switch the write or read timing, and a timing controller that generates a cycle selection signal to change the write or read timing; The device is characterized in that it includes an address controller that sends a switching signal to the storage element based on.

[0008]

[Operation] Image data to be written to or read from the storage element is arbitrarily designated via multiple data input/output ports, and then written to or read from the storage element based on the cycle selection signal output from the timing controller. The cycle is controlled by switching the address of the image data to be processed. In this case, the address is switched and sent to the storage element based on the combination of the designated image number and the pixel address of the image data corresponding thereto. Furthermore, when reading image data to the storage element, each shift register is shifted so that the phases of the data are aligned, so that the phases of each image data to be read are aligned.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the image storage device of the present invention, in which 1 is a memory element, which is provided with a plurality of data input/output ports 2 (21 to 2M) for inputting and outputting image data. It is being

Each data input/output port 21 to 2M has a data register 3 (31
3M to 3M), shift registers 4 (41 to 4M) whose number of shift stages can be controlled by a timing controller described later so as to align the phases of each data, and a data transceiver 5 which inputs and outputs each data to the memory element 1.
(51 to 5M) are provided.

Image data to be input and output is arbitrarily designated to each data input/output port 21 to 2M. Here, in each input/output port 21 to 2M, [1] to [M] indicate a port number, respectively. For example, data input/output port 21 indicates the port number [1],
It is assumed that the data input/output port 22 indicates the port number [2], and the data input/output port 2M indicates the port number [M]. Also, #1 is the first image number (
image data), #2 is the second image number, #M is the Mth image number
shall indicate the image number of Here, the first image number #1 is specified for the port number [1], and the port number [2] is specified as the first image number #1.
] is designated with the second image number #2, and the port number [M] is designated with the M-th image number #M. However, any combination of port number and image number can be specified. The memory element 1 inputs and outputs image data to and from an arithmetic circuit through each data input/output port 21 to 2M, thereby making it possible to write and read arbitrary image data.

A timing controller 7 generates a cycle selection signal for controlling write or read cycles of the memory element 1 and sends it to a read/write controller and an address controller, which will be described later. The timing controller 7 also generates a clock to control the operation of the data input/output ports 21 to 2M, and generates clocks for controlling the operations of the data registers 31 to 3M and shift registers 41 to 4M.
and sent to each data transceiver 51 to 5M. 8
is a read/write controller which sends a signal to switch the write or read timing to the memory element 1 based on the cycle selection signal.

Reference numeral 9 denotes an address controller which sends a signal to the memory element 1 to switch the addresses of a plurality of image data input and output to each of the data input/output ports 21 to 2M based on the cycle selection signal. This address controller 9 has a plurality of address input registers 10 (
101 to 10M) and each address input register 1
The address multiplexer 11 switches and outputs 01 to 10M outputs based on the cycle selection signal.

That is, in this embodiment, the memory element 1
The address of the image data written to or read from the image data is treated as if the image number and the pixel address of this image data were packed together as one address. As an example, if the image number address is set to 2 bits and the pixel address is set to 10 bits, it will be recognized as a 12-bit address, and nothing else is necessary. Next, the operation of this embodiment will be explained.

In order to make the explanation easier to understand, an example in which M=3 is set in the configuration of FIG. 1 will be explained below. Therefore, three data input/output ports [1], [2], and [3] are provided. Furthermore, an example will be described in which image data is read from first and second image numbers #1 and #2, and the calculation results of these two images are written to third image number #3. Furthermore, it is assumed that the image numbers [1] and [2] are designated as #1 and #2, respectively, and the image number [3] is designated as #3. The correspondence between these port numbers and image numbers is merely an example, and any combination is possible. For example, if you specify #3 in [1] for writing, [2],
It is also possible to specify #1 and #2 in [3] for reading.

As shown in FIG. 2, the image memory 6 of this embodiment
An arithmetic circuit 13 for calculating image data is connected to each input/output port 21, 22, and 23, and a host circuit 14 is also connected thereto. The host circuit 14 sends a read control signal to [1] and [2] and a shift (write) control signal to [3] based on the setting example described above. At the same time, based on the above setting example, [1], [2
] The image numbers of [3] are designated as #1 and #2, and the image number of [3] is designated as #3.

Furthermore, each pixel address is generated as shown in FIG.
is input. The address [3] is set later than the addresses [1] and [2], but this is because the calculation delay in the calculation circuit 13 is reflected.

The timing controller 7, as shown in FIG.
generates a cycle selection signal. For example, if the access time of the memory element 1 is 100 ns, t0 is set to 100 ns or more. This cycle selection signal is sent to the address multiplexer 11 of the address controller 9.
A signal is sent to the memory element 1 so that the address of each image data is sequentially switched. At the same time, the read/write controller 8 sends the memory element 1 [1]
During the cycle [2], a read control signal is sent, and [3]
The cycle sends the light control signal. FIG. 5 is a time chart showing how the read and write operations of the memory element 1 are performed based on the cycle selection signal as described above.

In FIG. 5, when a cycle selection signal is generated, the address controller 9 is controlled based on the cycle selection signal to switch the address. Memory element 1 is first [1]
, [2] read out the image data, and then [3]
] In the cycle, image data is written. In other words, by sequentially switching and supplying each pixel address (shown in FIG. 3) and image number of [1] to [3] selected by the cycle selection signal to the memory element 1, the memory element 1 is kept constant. After the access time has elapsed, the image data is read or written.

When the memory element 1 performs a read operation, the read image data is transferred to the data transceiver 5 with the configuration shown in FIG.
and is sent to shift register 4. At this time, transceivers other than the port selected by the cycle selection signal are
It is controlled so that no collision occurs between the memory element 1 and the image data, and the image data is taken in by a clock generated based on the cycle selection signal. Further, the shift register 4 is controlled to perform shift operations for the number of shift stages at the same time as image data is taken in by a clock.

For example, in FIG. 5, when reading image data to ports [1] and [2], the shift register 5
Immediately before (data output of transceiver 51 in [1] and data output in transceiver 52 in [2]), t0
The phase of the image data is shifted between [1] and [2] by this amount. This occurs because the read operation of memory element 1 is time-shifted by t0 between [1] and [2].
In order to correct this deviation of t0, the shift register 41 corresponding to [1] is set with the number of shift stages of "1" and [2].
] is controlled so that the shift register 42 corresponding to the shift register 42 is given a shift stage number of "0" stage. This allows the phases of the image data output from ports [1] and [2] to be aligned, as shown at the bottom of FIG.

Next, in the write operation, image data is sent from the external arithmetic circuit 13 using the acquisition clock of the transceiver 5, and image data input via the data register 3 and shift register 4 is input into the memory element 1. However, in this case, the data register 3 and shift register 4 are [1], [
2], but the shift register 4 does not perform another shift operation as in the case of reading.

Memory element 1 taken in by transceiver 5
As shown in FIG. 5, the image data to be written to the memory element 1 is first taken into the register in the transceiver 5, but then the image data is written to the memory element 1 only when [3] is selected based on the cycle selection signal. Data transmission is controlled so that image data collisions with other transceivers do not occur.

As described above, according to the present embodiment, image data is read and written by sequentially supplying address, read and write control signals to the memory elements to the data input/output ports selected based on the cycle selection signal. The first image is read from the first port because the number of shift stages of each shift register is controlled so that the phase of image data between each input and output port is aligned, especially when reading. At the same time, the second image can be read from the second port, and at the same time, the calculated image data can be written to the third port, and this can be achieved without requiring complicated processing. can do.

In this embodiment, an example in which three data input/output ports are set has been described, but these are only examples, and four or more ports may be set arbitrarily. Further, although an example has been shown in which inputting the image number, pixel address, readout command, write command, etc. is performed from outside, the present invention is not limited to these in any way.

Furthermore, it is possible to perform multiple interleave operation on the memory element, and with the same configuration as in this embodiment, it is also possible to input and output image data to the outside at the same time as or earlier than the cycle selection signal. Further, according to the present invention, it is possible to miniaturize the hardware and improve the ease of controlling the image number of the memory device.

[0028]

As described above, according to the present invention, a plurality of data input/output ports are provided, and image data input/output to each port is controlled in accordance with a cycle selection signal to perform writing and reading operations to a memory element. This makes it possible to simultaneously write and read image data without requiring complicated processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an image storage device of the present invention.

FIG. 2 is a block diagram showing an example of a configuration for performing image data writing and reading operations using the apparatus of this embodiment.

FIG. 3 is a timing chart showing an example of image address generation in the device of this embodiment.

FIG. 4 is an explanatory diagram of an example of generation of a cycle selection signal in the device of this embodiment.

FIG. 5 is a timing chart illustrating the operation of the device of this embodiment.

[Explanation of symbols]

1 Memory element 2 (21 to 2M) Data input/output port 4 (4
1 to 4M) Shift register 7 Timing controller 8 Read/write controller 9 Address controller 11 Address multiplexer 13 Arithmetic circuit 14 Host circuit

Claims (2)

[Claims] Claim 1: An image storage device capable of simultaneously writing and reading image data to and from a storage element, comprising: a plurality of data input/output ports for inputting and outputting image data to and from the storage element; a plurality of shift registers each having a controllable number of shift stages so as to align the phase of each data; a timing controller that generates a cycle selection signal for controlling the write or read cycle of the storage element; A read/write controller that sends a signal for switching the timing to the storage element, and an address controller that sends a signal to the storage element for switching the addresses of the plurality of image data input and output to the plurality of data input/output ports based on the cycle selection signal. An image storage device characterized by: 2. The address controller arbitrarily specifies an image number for each data input/output port, and combines the specified image number and the pixel address of the image data corresponding to this image number as an address. The image storage device according to claim 1, wherein each of these addresses is switched.