JPH04195440A - Semiconductor memory suitable for frame buffer and graphic processor using the same - Google Patents

Abstract

PURPOSE:To transfer area data at a high speed by providing a shift means, which can shift data read out from a memory element by arbitrary bits, and a mask means which can write only prescribed bits on the memory element. CONSTITUTION:A shift means 105 which can shift data by arbitrary bits and mask means 101 and 108 which can write only prescribed bits on the memory element are incorporated in a semiconductor memory. Data read out from a memory cell 100 in parallel is shifted in the shift means by arbitrary bits and is written only in prescribed write bit positions of the transfer destination. Thus, the area data transfer processing in a frame buffer is executed at a high speed.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a semiconductor memory that can transfer image data in a predetermined area to another area at high speed and is suitable for a frame buffer, and a graphic processing device using the same. [Prior Art] The function of transferring data in a predetermined area to another area within a frame buffer that stores information corresponding to each pixel on a display screen is called BITBLT (Bit Block Tran).
ster) function, and high speed is required as a basic function of graphic processing. To achieve this function,
For example, it is disclosed in Japanese Patent Application Laid-Open No. 172085/1985. Although this known technique provides a method for high-speed processing using a dedicated processor, processing is performed pixel by pixel, and the speed is not necessarily sufficient. On the other hand, looking at trends in semiconductor memory, memory with logic functions, such as dual-port memory for images (memory with a built-in shift function for video output), is attracting attention. "Dual Boat Memory" Nikkei Electronics Nn431.
The disclosure is in pp. 115-1-30. According to the same cited example, flash write and block write are disclosed as functions for clearing data in rows or blocks, but there is no disclosure regarding a method that enables high-speed transfer of area data. do not have. [Problems to be Solved by the Invention] The prior art described in item 1 has a problem in that it is not possible to transfer area data within the frame buffer at a sufficiently high speed. An object of the present invention is to provide a semiconductor memory that can perform area data transfer processing at high speed. Another object of the present invention is to provide a graphic processing device that can transfer area data at high speed using the semiconductor memory described above. Furthermore, another object of the present invention is to provide a small-sized shift means suitable for being built into the semiconductor memory. [Means for Solving the Problems] In order to achieve the above object, a semiconductor memory is provided with a shift means capable of shifting arbitrary bits and a mask means capable of writing only predetermined bits into a memory element. In addition, in order to achieve the above-mentioned other object, a graphic processing device is constructed using a frame buffer memory to which the semiconductor memory described in 1. is applied, and processor means that controls the frame buffer memory and transfers area data. I made it. Furthermore, in order to achieve the above-mentioned other object, a plurality of shift means are combined in series to obtain a shift means capable of shifting arbitrary bits. [Operation] In the semiconductor memory described above, after the data read out in parallel from the memory element is shifted by arbitrary bits by the shift means, the data is controlled to be written only to a predetermined write bit position of the transfer destination. Further, in the graphic processing apparatus having the above configuration, data in a predetermined area is transferred by controlling the frame buffer memory to repeatedly transfer data row by row. Further, arbitrary bits can be shifted by combining a plurality of shifting means. [Example] Hereinafter, an example of the present invention will be described in detail using the drawings. FIG. 1 shows an embodiment of the present invention, in which a semiconductor memory 10 includes a memory cell 1oO, a mask register 101. Data register 1o2. Barrel shifter 103. Arithmetic unit 10
4. Shift register 1o5°RA (row address) decoder 106. CA (column address) register 1o7. Mask control circuit 108° arithmetic unit 109. Selector 110.
Operation mode register 111. Timing control circuit 112
, is built-in. The memory cell 100 stores information for a total of 4M bits (2048 bits×2048 bits). This memory element can be used in various configurations, such as one 2048 x 2048 screen, two 204.8 x 1024 screens, or four 1024 x 1024 screens, but in the following explanation, it is used for 2048 x 2048 screens.
The explanation will be based on the assumption that it will be used as one page of . Mask register 101 stores information that controls which bit position within one row (2048 bits) is written. The data register 102 stores data for one line 20
A 48-bit register that temporarily stores data read from memory or data to be written next. Barrel shifter 103 has the ability to receive one row of data in the data register and shift (rotate) the data by an arbitrary number of bits in the range of 0 to 2047 bits. The arithmetic unit 104 performs an operation between the contents of the data register 102 and the contents of the barrel shifter 103.
It has functions such as logical operations for each bit and arithmetic operations for each group of multiple bits. Shift register 1.
05 stores one line of data to be output for display, and sequentially outputs it serially in response to an SC (Shift C1ock) clock. In terms of logical configuration, it is realized by a 2048-bit shift register or a combination of a 2048-bit data register and a selector. The RA decoder 106 inputs 11 bits A, , 10-A O (Add
A row address is taken out from a time-division signal of row and column addresses sent through the (res) terminal and decoded to select one row of the memory element. The CA register 107 temporarily stores the column address on the AIO to AO terminals in a certain access cycle until the next access cycle. The mask control circuit 108 generates write mask information using the column address supplied from the Al0-AO terminal and the previous column address information stored in the CA register 107, and writes the mask register 1.
Send to 01. The arithmetic unit 109 has a CA register 107
The shift amount to be supplied to the barrel shifter is calculated by calculating the previous column address information stored in the column address information and the column address information supplied from the AIO to AO terminals. selector 110
is the data register 102 and external data terminals D3 to Do.
This is used to select data between (Data). When reading data, 4 bits are selected from 2048 bits of the data register. The selection information is transmitted to the mask control circuit 10.
8, by decoding the upper 9 bits of the column address excluding the lower 2 bits. When writing from outside, this 9-bit decoding information is stored in mask register 1.
01, and selective writing is performed on predetermined 4 bits. The calculation mode register 111 stores the calculation mode written through the D3 to Do terminals. Timing control circuit 112 receives external control signals and generates timing signals necessary for internal operations. As a timing signal given from the outside, RAS (
Row Address 5trobe), CS
(chip(Data Transteroutp
ut Enable), S F,, S F. (Special Function). Here, SFl. SFo controls special access, and in particular provides information for selecting four types of write operations: word-by-word (4-bit) writing, bit-by-bit writing (2048 bits), and operation mode writing. Supplied as. FIG. 2 shows an outline of the configuration of a graphic processing device as an embodiment of the present invention, in which a system processor 1. System memory 2. Rendering processor 3. Frame buffer 4. Z buffer 5. Video control circuit 68 display device 7)
Consists of. The system processor 1 is responsible for controlling the entire graphic processing device, and uses programs and data stored in the system memory 2 to proceed with processing. This processor also executes coordinate transformation processing and clipping processing related to graphics processing. The rendering processor 3 receives control instructions from the system processor 1 and executes processing for generating various figures such as straight lines and filled figures in the frame buffer. Further, when executing the hidden surface erasing process of the three-dimensional figure, the process is performed with reference to the two-buffer 5. The frame buffer 4 stores information corresponding to pixels on the display screen,
It is constructed using a semiconductor memory with a built-in BITBLT function according to the present invention. The Z buffer 5 stores two coordinate values of the figure at the forefront of each pixel data in a three-dimensional figure, and is used for hidden surface erasing processing. The video control circuit 6 obtains processing such as color conversion from the information read out from the frame buffer 4 and generates a video signal to be supplied to the display device 7. In this embodiment, the display device 7 performs display on a display screen, but the same configuration is used when outputting to a printing device. FIG. 3 explains the operation of the semiconductor memory in the embodiment of FIG. 1, and shows a case where a predetermined portion within one row of memory elements is transferred. That is, the transfer source data area is specified by the row address RA s and the start position of the area is specified by the column address CA s, and the transfer destination area is specified by the row address RA s.
o and column addresses CAD1 and CAo2. FIG. 4 shows its operation time chart. To complete the operation shown in FIG. 3, the memory requires three access cycles: read the transfer predetermined, read the transfer predetermined, and write the transfer predetermined. First, a read cycle is an operation common to reading to a general external data terminal, and at the same time one row of data specified by a row address is read to the data register 102, the barrel shifter 102 reads the contents of the previous data register 102. Shift processing is performed. Furthermore, the arithmetic unit 104 performs an operation between the output of the immediately preceding data register 102 and the immediately preceding output of the barrel shifter 103. In the first read cycle, data for one row is read from row address RAs, and in the second read cycle, data is read from row address RAo. At this time, the column address CA s specified in the first read cycle is temporarily stored in the CA register 107, and the subtracter 109 calculates the column address CA, o , specified in the second read cycle.
and the column address CAs stored in the CA register 107 are subtracted, and the barrel shifter 103 shifts data by the number of bits corresponding to the result of this subtraction. Next, when the third cycle begins, the arithmetic unit 104 executes the arithmetic operation specified by the arithmetic mode register 111 between the contents of the immediately preceding data register 102 and the contents of the barrel shifter 103. This third cycle is designated as a row write cycle, and the mask register 101 in one row
Writing is performed to the bit position specified by . The mask register 101 contains the C data specified in the second cycle.
Using the CAos stored in the A register 107 and the column address CA D 2 specified in the third cycle, the C
111 II is generated only in the portion from Ao+ to CAo2, and 'O'' is generated in the other portions. Through the above three-cycle operation, the transfer operation shown in FIG. 3 is executed. That is, the configuration shown in FIG. In the graphics processing device that becomes An example is shown: 1024-bit shifter 201-.512-bit shifter 202..., 4-pitch 1-shifter 203.
Stage shifters are connected in series. Each shifter is controlled by a signal from the shift amount register 200, and controls whether to perform a shift or pass through as is. The information of each bit of the shift amount stored in the shift amount register 200 serves as a signal for controlling each shift. In this way, the input data is sequentially output through a shift operation according to the weight of each bit of the shift amount, resulting in a shift of a predetermined number of bits. Generally, 02 switching elements are required to construct an n-bit barrel shifter, but in the system of this embodiment, it can be constructed with at most nXlog, n switching elements, resulting in a small size. i.e. 20
In the case of a 48-bit Dorell shifter, the conventional method uses approximately 4
This method requires approximately 22 million elements, whereas this method requires approximately 22 million elements.
000 'chords are enough. Although it is slower than conventional methods because it combines elements in series, it is sufficiently fast because it is constructed inside a semiconductor element. In addition, as an intermediate method to fill the difference in speed and number of elements with the conventional method, this example uses an 11-stage series configuration, but it is also possible to combine the functions of multiple shifters and create a parallel logic configuration. can. That is, for example, as an alternative to the combination of 2-bit and 1-bit shifters, one having a 0-, 1-, and 2.3-bit shift function may be used. FIG. 6 shows another embodiment of the invention. It provides a compact logical configuration. The figure mainly shows parts that are different from FIG. 1. A selector 300 is provided between the barrel shifter 103 and the data register 102, and the barrel shifter 103 and arithmetic unit 104 are reduced to 128 bits. The selector 300 operates using some bits of the column address supplied from the mask control circuit 108. This embodiment can only process up to 128 bits of data at a time, so it is slower than the embodiment shown in FIG. 1, but the logical scale is sufficient.
h and is easy to realize. 12 inside the semiconductor memory
Since it performs 8-bit parallel processing, it is sufficiently faster than the conventional method in which processing is performed using an external processor. FIG. 7 shows yet another embodiment. The semiconductor memory 4o has a left position register and a right position register that define the left and right ends of mask bit positions generated in the mask register, and a shift amount register that stores the shift amount of the barrel shifter. These registers include operation mode register 11.
Similarly to 1, data is set via external data terminals ~D. The mask generation circuit 403 is
Mask information is generated from information stored in the left position register and the right position register. Furthermore, in this embodiment, position information in bit units (left position, right position, shift amount) is provided via the data terminal, so addresses in word (4 bits) units are supplied from address terminals A, ~A. ing. CA decoder 400 decodes the column address and controls selector 110 and other control registers. In this embodiment, each control register is mapped to the same address space as memory, and the RS (Register
5elect) signal is used to switch either the memory or the control register. FIG. 8 shows the address mapping. Address space is 1M words (1 word is 4 bits)
It consists of a memory space of 1M words and a control register space of 1M words. The control register space includes a left position register 401. Right position register 402° shift amount register 200. The calculation mode registers 111 are mapped, respectively.
It is accessed using the RS signal and address information. In this way, the embodiment shown in FIG. 7 has the advantage that it is easily compatible with conventional memories because addresses are supplied in word units, and that register access by software is facilitated because the control registers are mapped to the address space. be. FIG. 9 shows yet another embodiment. The semiconductor memory 50 of this embodiment is characterized in that it includes a transfer control section 500. The transfer control unit 500 uses the transfer source address (SA) 501
．． Transfer destination address (DA) 502, transfer size (SX,
5Y)503. It incorporates a transfer command register 504 and an operation mode register 505 to control the transfer of data in a predetermined area. FIG. 10 shows its function, where the transfer source area is defined by SA, SX, and SY, and the transfer destination is specified by DA. Here, SA and DA are addresses that are a combination of row and column addresses. The above registers are mapped to the address space and can be accessed from outside. When a transfer command is written to the transfer command register 504, the data in the row designated by SA is transferred to the row designated by DA, and then the process moves to the next row, repeatedly completing the transfer of data in a predetermined area. It can be continued until That is, this transfer is possible as a result of the transfer control unit 500 operating the timing control circuit 112 to sequentially perform predetermined memory access. Further, during operation, a signal indicating that the device is in operation is outputted from the B S Y (Busy) terminal to the outside. There are various transfer control commands, including those that update addresses in ascending order and those that update addresses in descending order. As described above, according to this embodiment,
Rectangular area data transfer is easily possible by issuing one command. In addition, in a graphic processing device to which this embodiment is applied, the processor only issues the above area,
High-speed transfer processing is performed inside memory. Next, as another embodiment, a semiconductor memory incorporating a Z comparison function suitable for the Z buffer 5 of FIG. 2 will be described. FIG. 11 shows the outline of the configuration of the semiconductor memory 60. The semiconductor memory 60 includes a memory section 600. Address control circuit 6011 buffer 602
．． Comparator 603. It consists of a timing control circuit 604. The memory section 600 includes a memory cell array that stores 512×512×16 bits of information, peripheral buffers, registers, and the like. Address control circuit 601 separates and decodes row and column addresses. The buffer 602 is a bidirectional data buffer, and controls and connects the data terminals on the external and memory sides. Controls cutting. Comparator 603 compares externally supplied write data and read data from memory. The timing control circuit 604 generates timing signals for each part, and in particular has the following functions according to the present invention:
It receives the output of the comparator 603, controls writing to the memory, and outputs a write control signal (WEOUT) to the outside. When attempting to write a Z comparison to a certain pixel position, first two values are read from the address, and a comparison with the write data is performed in the comparator 603. Writing is controlled depending on whether the FIG. 12 shows the configuration of a frame buffer and two buffers, one plane 701. G plane 702.
Bpl/-:/703. It consists of a Z plane 704. Here, the semiconductor memory shown in FIG. 11 is applied to the 2-plane 704. When writing to a certain pixel as part of the process of three-dimensional figure generation, writing is attempted to be done to each plane at the same time, but a Z value comparison is performed inside the semiconductor memory of the two planes 704, and based on the result, 1
IEO1, 1T times signal is generated. This signal is R, G,
It functions as a signal to control writing of each plane of B. As described above, according to this embodiment, as a result of incorporating the three-dimensional Z-value comparison function into the memory, high-speed processing becomes possible, and an external circuit is not required, making it possible to downsize the graphic processing device. [Effects of the Invention] As explained in detail above, according to the present invention, BITB
The built-in memory with LT function enables high-speed area data transfer. Further, in a graphic processing device to which the semiconductor memory described above is applied, processing by the processor becomes easier. moreover,
The new shift method enables the realization of a compact barrel shifter that can shift arbitrary bits. 4)

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment, FIG. 2 is a block diagram of a graphic processing device, FIGS. 3 and 4 are explanatory diagrams of the embodiment, and FIG. 5 is a configuration diagram of a barrel shifter as another embodiment. FIG. 6 is a block diagram of yet another embodiment, FIGS. 7 and 8 are yet another embodiment and its explanatory diagram, and FIGS. 9 and 10 are still another embodiment and its explanatory diagram. 1-1 and FIG. 12 are block diagrams of still other embodiments. 1.01...Mask register, 103...Barrel shifter, 104... Arithmetic unit.

Claims (1)

[Claims] 1) In a semiconductor memory in which a memory element arranged in m rows and n columns can be accessed via a d-bit external data terminal, the data read from the memory element is divided into s (s>d) bits. A semiconductor memory comprising: a shift means capable of shifting any bit within the range; and a mask means capable of writing only a predetermined bit (single or plural) of the output data of the shift means into the memory element. . 2) The semiconductor memory according to claim 1, wherein s=n. 3) The device according to claim 1 or 2, further comprising an arithmetic means for calculating between the output data of the shifting means and the read data from the memory element, and writing the arithmetic result to the memory element. 1. A semiconductor memory characterized by being made to have a large memory capacity. 4) Claim 1 or 2 or 3
2. A semiconductor memory according to item 1, comprising: an address terminal that receives a row address and a column address in a time-sharing manner; and temporary storage means for a column address of a previous access cycle. 5) The semiconductor memory according to claim 4, wherein the masking means is controlled using a column address of a certain access cycle and a previous column address stored in the temporary storage means. 6) The method according to claim 4, further comprising a subtracter for subtracting a column address of a certain access cycle from a previous column address stored in the temporary storage means, and the output of the subtracter is used as the A semiconductor memory characterized in that the amount is supplied as a shift amount to a shift means. 7) Claim 1 or 2 or 3
In the above description, the mask register has a mask position storage means for storing a left position and a right position as information for controlling the mask register, and data is stored in the mask position storage means via the data terminal. semiconductor memory. 8) Claim 1 or 2 or 3
The semiconductor memory according to item 1, further comprising shift amount storage means for temporarily storing the shift amount of the shift means, and data is stored in the shift amount storage means via the data terminal. 9) In claim 3, the method further comprises a calculation mode storage means for storing information for controlling the calculation means, and data is stored in the calculation mode storage means via the data terminal. Features of semiconductor memory. 10) The method according to claim 1, 2, or 3, further comprising means for respectively storing the position of the transfer source area, the position of the transfer destination area, and the size of the transfer area, and storing the transfer area in the memory element. 1. A semiconductor memory comprising transfer control means for controlling the area data to be transferred by repeatedly accessing the area data. 11) The semiconductor memory according to claim 10, wherein data is stored in the storage means in the transfer control means via the data terminal. 12) In any one of claims 7 to 11, the device has a signal terminal for switching address information to a memory or a control register, and one of the control registers spanning multiple words is selected using the address information. A semiconductor memory characterized in that it can be accessed. 13) The semiconductor memory according to any one of claims 1 to 12, wherein the shift means is configured by connecting a plurality of shift means in series. 14) A frame buffer memory configured using a semiconductor memory including means for shifting data in one row of memory elements and transferring it to another row; and processor means for accessing the frame buffer memory and generating graphic information. , output means for sequentially reading and outputting the contents of the frame buffer memory, the processor means managing area data transfer information and causing the frame buffer memory to repeatedly transfer line by line. A graphic processing device characterized in that data in a predetermined area is transferred by transferring data in a predetermined area. 15) Shifting means that divides the number 2^1 (i=0, 1, 2, ..., m-1) into multiple parts and can selectively shift the number of bits included in each part. A data shift means capable of shifting arbitrary bits within 2n-1 bits, which is formed by connecting these in series. 16) 2^0, 2^1, 2^2, ...2^m^-^1
16. The data shifting means according to claim 15, comprising bit shifting means connected in series. 17) A semiconductor memory comprising a comparison means for comparing data written from the outside with data read from a memory element, and controlling writing of data from the outside based on the comparison result.