JPH03277084A - Field memory - Google Patents

Abstract

PURPOSE:To select and set plural delay values by splitting a line memory into plural split lines each having a prescribed pixel number, providing a write and readout data register corresponding to the above memory and controlling them by a delay selection control circuit. CONSTITUTION:When a delay is maximized, a delay selection control circuit 4 selects blocks A, B, C. When write/read addresses are set in common, the delay of (O+P+Q)Xline number (n) in total in pixel number is obtained. When the delay selection control circuit 4 selects the blocks A, B, the block C is not used at all. Then the operation of data registers 1B, 3B is started continuously after the end of the operation of the write data register 1A and the read data register 3A for both the write and readout. The operation of the registers 1A, 3A is again started after the end of the operation of the registers 1B, 3B. Thus, the delay is (O+P)Xn.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a field memory, and more particularly to a sophisticated field memory for temporarily storing and outputting data such as television image signals.

[Conventional technology]

Conventionally, as shown in FIG. 2 as a first example, this type of field memory includes one field (N lines) of line memories 22 for storing data for one line of image signals, and includes an address signal AD. and a FIFO type memory cell array 2 that sequentially writes write data Dw according to a read/write signal R/W and reads data from one field before.
x, and a write circuit 5 which inputs serial input data DIN every N lines and supplies it to the memory cell array 2X according to the read write signal R/W, and the N data read from the memory cell array 2x according to the read write signal R/W.
Line data (DR) is serial output data D.

The configuration includes a readout circuit 6 that outputs as LIT.

In this first example, since reading and writing are controlled by one read/write signal R/W and one address signal AD, the amount of data delay can only be obtained by one field.

To obtain a delay shorter than one field using the circuit in the first example (second example), write data up to the desired delay as shown in Figure 3. Time (
At the address "'m"), it is necessary to reset the address of the address signal AD to "°0°" using the reset signal R3T, and perform external control to read and write again from the address "°0". (In Figure 3, “°
0′.

"'1" to "m" are addresses of memory cell array 2X, (f) and (m) are data of m address of f field, (f-1) and (m) are m address of one field before f field data, the shaded part is invalid data D
Indicates N. ) Also, if you try to obtain a (shorter) delay amount other than one field by asynchronously writing and reading, the third example)
In addition to requiring external control, it also requires two address counters, one for writing and one for reading.

[Problem to be solved by the invention]

In the first example, the conventional field memory described above has a configuration including a FIFO type memory cell array 2x controlled by one read/write signal R, /W and one address signal AD. There is a drawback that the amount is fixed, and in the second example, the address signal AD is controlled externally, so there is a drawback that the control circuit for the address signal AD becomes complicated. In the example, in addition to address control, address counters for writing and reading are required, so
In addition to the complexity of the control circuit for address control, the address counter may make a counting error due to noise coming in from outside the field memory via the power supply line, ground line, etc. This has the disadvantage that the amount of delay will be different from the amount of delay that was calculated. (In the case of synchronous type, there is only one address counter, so the delay amount does not change even if a counting error occurs.) The purpose of the present invention is to select multiple delay amounts without providing a complicated external control circuit. The object of the present invention is to provide a field memory that can be set and obtain a stable amount of delay.

[Means to solve the problem]

The field memory of the present invention is a FIF having multiple lines of divided line memories each having a predetermined number of pixels.
A plurality of O-type memory cell arrays are provided corresponding to each of these memory cell arrays, and after temporarily holding input data of the same number as the number of pixels of the dividing line memory of each of these memory cell arrays according to a control signal, the input data is transferred to the corresponding memory cell array. A plurality of write data registers are provided corresponding to each of the memory cell arrays to transfer data in batches as write data, and are provided to temporarily hold read data for one divided line memory that is transferred in batches from each of the memory cell arrays in accordance with the control signal. It has a plurality of read data registers that output, and a delay amount selection control circuit that outputs the control signal and selectively activates each write data register and each successive data register, and controls data holding/transfer and output. ing.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In this example, each predetermined number (o, p.

Q) divided line memory (21A21B) with pixels
, 21c) in a plurality of lines<n), and each of these memory cell arrays 2A, 2B.

2C, and each of these memory cell arrays (2A, 2B
, 2C) divided line memories (21A, 21B, 21
After inputting the same number of serial input data DIN as the number of pixels (0゜P, Q>) from the data bus D
, 2B, 2c) are provided corresponding to a plurality of write data registers 1^, IB, IC, and each memory cell array 2^, 2B, 2c to transfer the write data at once as write data to the memory cell arrays 2^, 2B, 2c. Output data D is serially outputted by temporarily holding the read data for one divided line memory which is collectively transferred from each of these memory cell arrays (2A, 2B, 2C). a plurality of read data registers 3A outputting as u□ to data bus OB o;
3B, 3C, and control signal SS are output and clock signal CK is output.
and each write data register lA, lB, 1. c and a delay amount selection control circuit 4 that selectively activates each read data register 3A, 3B, and 3C and controls data retention, transfer, and output.

Next, the operation of this embodiment will be explained. For convenience of explanation, groups whose part codes have the suffix °“A” are called block A, and groups whose part codes have the suffix “°B” are called block B.
, C' is called block C.

First, when the delay amount is maximized, the delay selection control circuit 4
Block A, block B, and block C are all selected.

The write operation at this time is to serially write the input data DIN to the write data register IA in synchronization with the clock signal CK.
Enter. Write data register 1^ is input data D
When it is full with IN, continue writing data register I.
Serial write to B. At this time, the data in the write data register IA that is full is stored in the memory cell array 2.
It is transferred to A all at once.

As serial writing continues further, the write data register IB becomes full. When it is full, serial write is transferred to the write data register 1°, and all data in the write data register IB is transferred to the memory cell array 2b at once.

Further, as serial writing continues, the write data register lc becomes full. When it is full, the serial write is transferred to the write data register IA, and all the data in the write data register 1c, which is now full, is collectively transferred to the memory cell array 2°. The same operation is repeated below.

For read operation, read data register 3A
In advance, the divided line memory 21A of the memory cell array 2A is
One line worth of data is transferred at once. Next, the data in the read data register 3A is sent to the data bus DB in 1 bit synchronization with the clock signal CK. Output to. This operation is called serial read.

While serially reading the read data register 3A, the memory cell array 2B is stored in the read data register 3B.
One line worth of data in the divided line memory 21B is transferred at once.

When the serial read of the read data register 3A is completed, the process continues to the serial read of the read data register 3B.

While serially reading the read data register 38, the memory cell array 2c is stored in the read data register 3c.
One line worth of data in the divided line memory 21c is transferred at once.

When the serial read of the read data register 3B is completed, the process continues to the serial read of the read data register 3c.

When the serial read of the read data register 3° is completed, the process continues to the serial read of the read data register 3A, and the same operation is repeated thereafter.

As mentioned above, when all blocks (A, B, C) are used, the amount of delay is maximum, and when the write and read addresses are set in common, the total number of pixels (0+
P+Q) A delay amount of the number of lines (n) is obtained.

Next, when block A and block B are selected by the delay amount selection control circuit 4, block C is not used at all,
For both write and read operations, after the write data register LA and read data register 3A have finished operating, the write data register 1B and read data register 3B start operating, and the write data register IB and read data register 3B end their operations. After that, write data register L again.
A. Start the operation of the read data register 3A.

By doing this, the amount of delay becomes (0+P)Xn.

In this way, depending on which block is selected by the delay amount selection control circuit 4, the delay amount can be changed without complicated control from the outside. In this embodiment, 3 C3 + 3 C2 + c, c = 7, so seven types of delay amounts can be selected.

In this embodiment, an example is shown in which the block is divided into three blocks, block A, block B, and block C, but if the number of blocks is increased, even more delay amounts can be selected. For example, if the number of blocks is 4, 4C4+4C3+
4C2+4C115, and 15 different delay amounts can be selected.

[Effects of the Invention] As explained above, the present invention divides a line memory of a memory cell array into a plurality of divided line memories each having a predetermined number of pixels, and writes a write data register and a read data register corresponding to these divided line memories. By providing a delay amount selection control circuit that selectively controls the operations of the memory cell array, write data register, and read data register, there is no need for complicated external control. A plurality of delay amounts can be selectively set without providing a control circuit, and reading and writing can be performed at the same address, so that a stable delay amount can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a first example of a conventional field memory,
FIG. 3 is a signal waveform diagram for explaining a second example of a conventional field memory. IA~1c...Write data register, 2A~2c
, 2x...Memory cell array, 3A-3c read data register, 4... Delay amount selection control circuit, 5... Write circuit, 6... Read circuit, 21A...-21c...
・Divided line memory, 22... line memory.

Claims (1)

[Claims] 1. A plurality of FIFO-type memory cell arrays each having a plurality of lines of divided line memories each having a predetermined number of pixels, each of which is provided corresponding to each of these memory cell arrays, and which is configured to control each memory according to a control signal. a plurality of write data registers that temporarily hold input data of the same number as the number of pixels of the divided line memory of the cell array and then collectively transfer it to the corresponding memory cell array as write data; 1 transferred in batch from each memory cell array according to the control signal.
A plurality of read data registers that temporarily hold and output read data for divided line memories, and output the control signal to selectively activate each write data register and each read data register, and control data retention, transfer, and output. A field memory characterized by having a delay amount selection control circuit that performs the following. 2. Each write data register is a data register that holds the serial input data for the corresponding number of pixels and then transfers it all at once to the corresponding memory cell array, and each read data register is a data register that holds the serial input data for the corresponding number of pixels and then transfers it all at once to the corresponding memory cell array. 2. The field memory according to claim 1, wherein the field memory is a data register that holds read data for the divided line memory and outputs it as serial data.