JPH01126687A - Display memory control circuit - Google Patents

Abstract

PURPOSE: To reduce the frequency in access to one to quickly write picture data in a display memory by writing only first picture data in the display memory in the case of a large number N of continuous picture elements of the same picture data. CONSTITUTION: A clear circuit 4 which writes clear data in a display memory 2 in accordance with a clear signal sent from an MPU 1 and a display data holding circuit 7 which discriminates whether read data read out by a display data control circuit 6 is significant or not to successively hold only significant data are provided. When N picture elements of the same picture data are continuous, such display memory write address is generated by an address generation circuit 3 that only the first address out of addresses where data of N picture elements should be stored in the display memory 2 is generated but addresses for N-1 other continuous picture elements are not generated. Consequently, data of plural picture elements is written in the display memory only once however long these picture elements are continuous. Thus, the same picture data is quickly written.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an image display device that displays image information, and particularly relates to an image display device that displays image information, and particularly to a method for writing the same pixel data into a display memory at high speed for a plurality of consecutive pixels. The present invention relates to a display memory control circuit suitable for performing the following operations.

[Conventional technology]

In captains, facsimile machines, etc., a continuous sequence of the same image data is compressed by run-length encoding and transmitted, and the receiving terminal decodes it into the original image data and displays the image. Conventionally, as a circuit for decoding such run-length encoded image information,
As described in Publication No. 0-76789, the start address,
By setting the image data and the number of consecutive pixels, the pixel data is automatically stored one pixel at a time in the display memory.'c1
A one-input display memory control circuit is known.

[Problem that the invention seeks to solve]

Another problem with the above-mentioned conventional technology is that since one pixel of image data is written into the t-display memory in one frame cycle, as the number of consecutive pixels increases, the time required for writing also increases in proportion to the number of pixels to be written. was there.

SUMMARY OF THE INVENTION An object of the present invention is to provide a display memory control circuit that solves the problems of the prior art described above and can speed up the writing of the same image data to a plurality of consecutive pixels.

[Means for solving problems]

In order to achieve the above object, the present invention uses an addition conversion address obtained by adding an initial address indicating the starting position of writing the first image data to the display memory, the number N of consecutive pixels to be looked at, and the current address. a selection means for selecting a display memory write address, and a next display memory write address 1- selected by the selection means;
and counter means for incrementing by 1 every memory cycle.

an addition means for generating the addition conversion address by adding the display memory write address and the number of continuous pixels to be written; A clearing means for clearing data, a determining means for determining whether data read from the display memory is valid or invalid, and a data holding means for holding the valid data each time the valid data is input. This is intended to write the same image data to a plurality of consecutive pixels at a higher speed than in the conventional example.

[Effect]

The above-mentioned clearing means looks into the clear data t-display memory. Next, image data is written to the display menu from the initial address selected by the selection means.

At this time, the axis of image data enrichment for each pixel is determined by counting up the display memory write address one by one by the counter means and storing the image data in the display memory according to the counted up address. However, in the case of a plurality of continuous writing pixels, the number of consecutive writing pixels is added to the display memory write address by the adding means, and the display memory write address is increased at once, and the display increased by this N. The memory write address is selected as the addition conversion address by the selection means, and image data is stored in accordance with this addition conversion address. Therefore, the clear data remains in the display memory between the first and eleventh pixel which was skipped without writing anything. By performing such a writing operation to the display memory, only the first image data of consecutive identical image data is stored, and the remaining image data for N-1 pixels remain in the display memory.

Next, when image data is read from the display memory, the discrimination means discriminates whether it is image data or clear data, and only the image data is sent to the data hold means and held. As a result, only the first image data is stored in the series of nine-double image data, but when this first image data is output, the data is held by the data holding means until the next riiJS data arrives. , when viewed from the output side, it appears as if a plurality of consecutive pixels are stored in the total temperature display memory. Furthermore, when writing the primary image data to the display memory, the display memory is cleared with clear data before writing. As a result, no matter how long the continuous multi-pixel data is, it only needs to be written to the display memory once, making it possible to realize a display memory control circuit that can read the same image data at high speed. do.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the display memory control circuit according to the present invention, in which G1 indicates a microprocessor (hereinafter referred to as MPU) for writing image data, and 2 indicates a microprocessor (hereinafter referred to as MPU) for writing image data. 5 is a display memory that stores image data; 5 is an address generation circuit that generates an address that determines where in the display memory 2 the image data should be stored; 4 is M;
A clear circuit writes clear data to the display memory 2 according to a clear signal sent from the PUI, 5 is a display device that displays the display data, and 6 is a clear circuit that writes the image data stored in the display memory 2 to the last scan of the display device i5. Display data control circuit 7 also performs reading control, display data control circuit 6
This is a display data hold circuit that judges the significance of the next read data that is read due to busyness and sequentially holds only the significant data.

FIG. 2 is a diagram showing the correspondence between the display memory 2 and pixel display positions in FIG. 1.

The display memory 2 has a one-to-one correspondence with display pixels. Friend, the addresses of image data increase in the order of display scanning of the display device 5. That is, the X coordinate of the display pixel is assigned to the lower bit of the address, and the X coordinate is assigned to the upper bit of the address.

Next, a method for decoding the run-length encoded compressed data and writing it into the display memory 2 for display will be described.

Figure 3 shows 1 as run-length encoded compressed data.
It shows the process from input to output when writing for 8 pixels from 5th row, 3rd column to 3rd row, 10th column of display pixels.

In the figure, when run-length encoded compressed data is written to the display memory 2, the continuous image source data D1 is written only to the 5th row and 3rd column, which is the first address, and nothing is done for the remaining 7 pixels. Not possible. That is,
Only the image data indicating the start position of the run-length encoded compressed data is stored in the t-display memory 2, and the remaining 1
For the ifI element, 1ITIWi is cleared, and the clear data at 9 is set to 600, and this clear data is not used for image data and is assumed not to exist. Next, the data written to the display memory in this way is output as is, and since there is a one-to-one correspondence between display pixels and display memory 2, the run-length encoded compressed data part consists of 5 lines. Only the beginning of the third column is correct, and the remaining 7 pixels are only displayed with °0" data.Here, if the data is °0° in the output stage of the display method, ignore it, and if it is not, ignore it. By adding an output data hold circuit that holds the output data, the 1101+ data is no longer output to the display pixels, and with this configuration, it is encoded into p-run length and becomes the next compressed data. will be expanded and output for display.

FIG. 4 is a detailed block diagram of the address generation circuit, clear circuit, and display system.

10 is a two-channel multiplexer that selects a start address and an addition conversion address according to an initial value setting signal;
1 is a D flip-flop that launches only the length data on the data bus according to the length signal, 12 is an address counter that counts up the loaded write address one by one according to the clock, and 13 is the current optical memory write address and length data. The adding circuit 14 is a two-man powered NOR gate.

FIG. 5 is a structural diagram showing the data structure of a run-length code.

In the same figure, (a) is a case where image data is sent one pixel at a time, and the most significant bit is "always 0°. (b)
) is a case where length data indicating the number of pieces of the same image data and image data are sent when multiple pieces of the same image data continue, and the most significant bit is always °1°, and the data that follows is judged to be length data. Ru. Further, it is assumed that the MPU 1 discriminates between one image data and length data, and outputs a length signal when the data is length data. The writing operation to the display memory when such a run-length code is used will be explained with reference to FIG.

In the figure, first, a clear signal is sent to the clear circuit 4 from MP
Clear data 00# is supplied from U1 and clear circuit 4
is written to the display memory 2 at high speed and clears the display memory 2. Here, as a method to quickly clear display memory 2, for example, if a dual port memory with a serial input function is used as display memory 2, first input °O'' continuously from the serial input terminal. , clear the data register of the serial port. Next, repeat the internal data transfer from the serial port to the random port to clear the random port. The time required for the above clearing operation is 60110 seconds. It is.

Next IK, when the start address is supplied from MPU1 and the initial value setting signal is given, 2 channel multiplexer 1
0 is switched to the H side.A start address is supplied to the data input of the seat address counter 12, and an initial value setting signal is supplied to the load input through the two-manufactured NOR gate 14t-, and the memory cycle clock rises. The initial value of the data write start address to the display memory is set in the address counter 12 together with the upper value 9.

Next, regarding writing one image data, there is a case where only image data is sent and only that image data is written once, and a case where only one image data is written.
There are two ways of writing to the display memory 2 when image data and length data are sent and the run-length expansion writing of the image data is performed.

1. When reading only image data, the image data and write signal are supplied from the MPUI to the display memory 2, and the display memory 2 writes one image data according to the value of the display memory write address of the address counter 12 at that time. Then, when the memory cycle clock rises 9, the address counter is incremented by one. If only the image data is sent and the temperature reaches .degree. C., the above operation is repeated to write the image data t-1 pixels at a time to the display memory.

Next, when performing run-length expansion writing of image data, one square image data and write signal are stored in the display memory 2.
The image data is supplied from the MPUI and stored in the display memory 2 according to the value of the display memory write address of the address counter 12 at that time. Next, the number of pixels N is supplied from the data input &CMPut of the D flip-flop 11, and the length signal is given to the clock input of the D flip-flop 11.
It is latched to 1. The latched number of pixels is supplied from the data output of the D flip-flop 11 to the adder circuit 15, and the adder circuit 15 adds the display memory write address supplied at that time and the number of pixels N1, and uses the result of the calculation. A certain addition conversion address is supplied to the t-2 channel multiplexer 10. At this time, the 2-channel multiplexer 10 is not given the initial value setting signal, so the L side is supplied with the addition conversion address to the data input of the address counter 12, and the address counter 12 inputs the MPU
A length signal is applied from 1 to the load input through a two-way NOR gate 14, and at the rising edge 9 of the memory cycle clock, an address for writing display data into the display memory is set in the address counter 12. with image data.

When length data is sent, repeat the above operations to load only the image data indicating the start position of the run-length encoded compressed data into the display memory 2, and store the remaining image data into the display memory 2. One image data is written into the display memory 2 according to the number of pixels by performing address operations so that the data "0" when the screen is cleared by the width of the data remains.

By selectively using the data supplied from the two display memory write operations t-MPUt, it is possible to perform run-length expansion writing of image data at high speed. Furthermore, when writing new image data onto the display memory in an overlapping manner, the old image data written in the display memory is cleared as 0° data before writing the new image data.

The sixth @ is a time chart of various data and control signals output by the MPU 1 during display memory writing.

81.82 is the start address on each screen, IJI, L)
2.

1JS, D4, D5, D6, and Dn are image data, and Ll and L2 are length data.

The data bus outputs the glance start address S of the display memory, image data D, length data L indicating how long the same image data lasts, etc. When the initial value setting signal is at signal level or H, the data bus It shows that the glance start address S is fixed at the top.The length signal shows that the length data is fixed on the data bus when the signal level is H.The write signal shows that the length data is fixed on the data bus when the signal level is L.
Indicates that the image data on the data bus is written to the display memory when . The memory cycle clock indicates the load timing or count-up timing of the address counter 12. The clear signal is output during the vertical retrace period at which the screen changes, indicating that the display memory is to be cleared with clear data.

Next, a method for reading image data stored in the 1-display memory 2 will be described.

FIG. 7 is a detailed block diagram of the display data hold circuit 7, the display device 5, the display control circuit 6, and the display memory 2.

Reference numeral 14 denotes a data discrimination circuit for discriminating whether it is image data or clear data, and 15 indicates D for latching only (iiiiii!) data among the image data and clear data read out from the display menu 2 according to the output of the data discrimination circuit 14. It's a flip flop.

In the same figure, the °C1 display control circuit 6 supplies a horizontal synchronization signal and a vertical synchronization signal to the magnifying display device 5 to perform a rask operation, and in synchronization with the rask operation of the display device 5, the data is transferred from the display memory 2 to the display pixels. Correspondingly, the next address is busy reading out the stored m-image data. Data discrimination circuit 14
Then, the read data read out from the 1 display memory 2 is constantly monitored, and when image data is read out, a latch signal is supplied to the t-D flip-flop 15. When the latch signal is input, the D flip-flop 15 latches the read data at that time, and supplies the latched read data as display data to the display device i5. As a result, the clear data left when writing image data to the display menu 2 is no longer displayed.

As described above, for example, when writing image data compressed by run-length encoding to the display memory 2, f!
By breaking the structure in which run-length expansion is carried out by dividing the length of L, high-speed decoding processing of run-length encoded image data can be realized.

In addition, although the purpose of the explanation so far has been to speed up the decoding process of run-length encoded 1111g1 information, it is clear that it is also effective for high-speed line drawing processing, surface vm crushing processing, etc. It is.

In the above embodiment, @ is stored as clear data in the display memory 2.
If you write "0" and the value does not overlap with the image data, any numerical value can be used for the clear data and temperature is also good.Furthermore, each image data itself has valid/invalid information (for example, if the 8th bit of the data is " When the 8th bit of the data is 0°, it is invalid data, and when the 8th bit of the data is 1", it is valid data.) In this case, to clear the display memory 21, the data 8 All you need to do is clear the first bit.

〔Effect of the invention〕

As explained above, according to the present invention, the same image data can be used for consecutive N pixels? : When writing to the display memory, no matter how long the same image data lasts, only the first image data is written to the display memory, and only one access is required. This makes it possible to write image data into the display memory at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the display memory control circuit according to the present invention, FIG. 2 is an explanatory diagram showing the correspondence between the display memory and pixel display positions in FIG. 1, and FIG. 3 is a run-length code. FIG. 4 is a detailed block diagram of the clear circuit, display memory, and address generation circuit, and FIG. 5 is an explanatory diagram showing the process from input to output when writing compressed data. A structure diagram showing the data structure of a run-length code! ! %
Figure 6: Time chart of each data and control signal output by MPU 1 in writing to light display memory, No. 7
The figure shows a detailed block 1 consisting of a display device @S, a display control circuit 6, a display memory 2, and a display data hold circuit 7. -MPU 2-Display memory 5-Address generation circuit 4-Clear circuit 5-Display device 6-Display control circuit 7-Display data hold circuit 12-Address counter 15-Addition circuit 14-Data judgment circuit 15-D flip-flop agent Katsuo Ogawa, Bentoshi. times →^ Figure 5 (Q) (b)

Claims (1)

[Claims] Equipped with a display memory that stores and retains at least image information,
In a display memory control circuit of an image display device that displays image information stored in the display memory, when the same image data continues for N pixels, the address where the data of the N pixels in the display memory should be stored is determined. an address generation circuit that generates a display memory write address that generates only the first address in the display memory and does not generate a display memory write address for the remaining N-1 consecutive pixels, and image data read from the display memory. A display memory control device comprising: a display data hold circuit that selectively holds only image data other than predetermined clear data by making a determination; and a clear circuit that clears the display memory when updating image data. circuit.