JPH076087A - Method for accessing frame buffer - Google Patents

Abstract

PURPOSE:To increase the speed of plotting up to twice as fast as before and make the method effective when many longitudinal and lateral lines are platted in the field of CAD, etc. CONSTITUTION:A frame buffer is subdivided into two memory banks 0 and 1 and data are written in the memory banks 0 and 1 alternately and read out. For this writing and reading method, a display screen is divided in a longitudinal/lateral lattice state and the different memory bank 0 or 1 is used for each adjacent divided rectangular area. The two memory banks 0 and 1 can efficiently be utilized by turns in either of cases wherein the display screen is drawn laterally and longitudinally.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention divides a frame buffer for storing image data into two memory banks, and selects one of the memory banks based on the address information contained in the access request signal to the frame buffer. The present invention relates to a method of deciding whether to access the memory cell of, and accessing the memory cell of the memory bank based on this decision.

[0002]

2. Description of the Related Art When displaying an image on a CRT or the like, it is necessary to first store the pixel signals forming the image in a bit map memory. Bitmap memory is also called a frame buffer. The image data input to the frame buffer through the input / output bus is written at a predetermined address of the frame buffer, read at a fixed timing, and sent to a display device such as a CRT, where the image is displayed. Reproduced.

The role of the frame buffer is to process a large amount of data as fast as possible and faithfully reproduce the image. By the way, conventionally, when accessing the frame buffer, the frame buffer is
An access method of subdividing into two areas (memory banks) and alternately writing and reading for each memory bank has been adopted.

The correspondence between this memory bank and the display screen on the CRT is as shown in FIG. 4, in which the display screen is vertically divided at regular intervals and each is made to correspond to memory bank 0 or memory bank 1. ing. FIG. 5 is an enlarged view for explaining in more detail. The pixels on the display screen are allocated so as to correspond to the memory bank 0 or the memory bank 1 for each horizontal n pixels (n = 8 in FIG. 5). ing.

FIG. 6 shows the structure of the frame buffer,
3 is a block diagram for explaining a connection state between the frame buffer and the bus controller, and the frame buffer 11 includes eight memory cells FB00 to FB07 corresponding to the memory bank 0 and eight memory cells corresponding to the memory bank 1.
One memory cell FB08-FB0f. The respective data of the horizontal 8 pixels are stored in the eight memory cells of the same memory bank of the frame buffer 11.

The bus controller 12 is a memory cell FB.
00-FB07, a line for sending a signal RAS0 used when designating the row address of all memory cells and a signal CAS0-7 used when designating the column address of each memory cell, and a specific row address and column address Is connected to the memory bank 0 through an address line for designating the. Further, the bus controller 12 uses the signal RAS1 used to specify the row address of all memory cells and the signal CAS8-used to specify the column address of each memory cell for the memory cells FB08-FB0f of the frame buffer 11. It is connected to the memory bank 1 through a line for sending f, an address line for designating a specific row address and a column address, and a data line.

The function of the bus controller 12 is as follows. That is, when image data (consisting of gradation data and an address) for each pixel is serially sent from the system bus, the bus controller 12 decodes the address data, and the pixel has any of the pixels in FIG. Determine if it should belong to a memory bank. If it should belong to memory bank 0, it generates signal RAS0 and signals CAS0-7. If memory bank 1
Signal RAS1 and a signal CAS8-f are generated. The signal RAS0 and the signal RAS1 are generated once and then continued, whereas the signal CAS0-7 continues only while receiving pixel data which should belong to the memory bank 0, and the signal CAS8-f belongs to the memory bank 1. It is designed to continue only while receiving pixel data to be processed.

FIG. 7 is a chart showing the transmission timing of the signal RAS, the signal CAS, the address signal, etc.
A case where a horizontal line is drawn on the display screen of the RT (see FIG. 4), that is, a case where writing is alternately performed in the memory bank 0 and the memory bank 1 is shown. First, the RAS0 signal and the RAS1 signal are low-enabled, and signals CAS0-7 and CA which are in opposite phases to the clock depending on whether to write to the memory bank 0 or the memory bank 1.
S8-f occurs. When the signal CAS0-7 becomes low enable, the designated memory cells FB00-F
Data is written to the designated address of B07, and when the signal CAS8-f becomes low enable, the data is written to the designated address of the designated memory cells FB08-FB0f. Since the signals CAS0-7 and CAS8-f have opposite phases to each other, writing to the memory bank 0 and writing to the memory bank 1 are alternately performed, which is a vertical line in FIG. This is because the horizontal lines were drawn while passing through the regions one after another.

[0009]

However, when a vertical line is drawn on the display screen of the CRT (see FIG. 4), data is written only in any memory bank. That is, even if the bus controller 12 decodes the address data, it only determines that the pixel should belong to the memory bank 0. Therefore, RAS1 signal and CAS8
-F remains disabled.

The time chart at that time is as shown in FIG. Compared to the previous time chart, since the RAS1 signal and the signal CAS8-f are not generated, the writing to the memory bank 1 is not performed at the time when the writing to the memory bank 1 is originally performed. This means that the time originally taken for writing to the memory bank 1 is wasted.

Therefore, an object of the present invention is to solve the above-mentioned technical problems and efficiently use two memory banks alternately when drawing a vertical line or a horizontal line on a display screen. An object of the present invention is to provide a frame buffer access method that enables quick access.

[0012]

According to a method of accessing a frame buffer as set forth in claim 1 for achieving the above object, the frame buffer is subdivided into two memory banks, and each memory bank is alternately arranged. When writing or reading, the correspondence between the memory bank and the display screen is different from the conventional one. That is, the display screen is divided into vertical and horizontal grids,
A different memory bank corresponds to each of the adjacent divided rectangular areas.

[0013]

According to the above method, since the display screen is divided into the vertical and horizontal lattices, for example, when the display screen is drawn horizontally or vertically, two memory banks are used in both cases. You can use them alternately and efficiently.

[0014]

Embodiments will be described in detail below with reference to the accompanying drawings showing embodiments. FIG. 1 shows a memory bank and a CRT according to the present invention.
It is a figure which shows the correspondence with the above-mentioned display screen, Comprising: A display screen is divided vertically and horizontally at fixed intervals, and each corresponds to the memory bank 0 or the memory bank 1. In this embodiment, it is assumed that the number of pixels on the display screen is 2048 in the horizontal direction and 1024 in the vertical direction, and each of the horizontal 8 pixels is divided by the memory bank. Therefore, the number of memory banks included in one row on the display screen is 2048/8 = 256, and the number of memory banks present in one column on the display screen is 1024.

Since the structure of the frame buffer and the connection relationship between the frame buffer and the bus controller are the same as those in FIG. 6, the reference numerals appearing in FIG. 6 will be used as they are. The structure of the bit string that constitutes one image data is as shown in FIG. 2, as in the conventional structure. In the figure, a 32-bit string of A0-A31 is illustrated,
The lower three digits are the designated address of the memory cells FB00-FB07 or memory cells FB08-FB0f. As described above, each data of horizontal 8 pixels on the display screen is stored in the memory cell FB of the frame buffer 11.
00-FB07 or memory cells FB08-FB0f, respectively, so that the lower three digits are also designated bits of horizontal 8 pixels on the display screen.

The fourth digit is a bit indicating whether 8 horizontal pixels on the display screen are in memory bank 0 or memory bank 1, that is, a bit for identifying the memory bank. In FIG. 3, the numerical values of the four digits from the bottom are entered for each pixel on the display screen. It can be seen that whether the memory bank 0 or the memory bank 1 can be identified depending on whether the numerical value in the fourth digit is 0 or 1.

The 12th digit bit is a bit representing a row on the display screen. This is because if 2048 bits on the display screen continue from the upper left to the upper right, the 11th digit is full, and the 12th digit is moved up to the left end one line down. From the above, (1) 4th digit A3 = 0, 12th digit A12 = 0: memory bank 0 (2) 4th digit A3 = 1, 12th digit A12 = 0: memory bank 1 (3) 4th digit Digit A3 = 0, 12th digit A12 = 1: memory bank 0 (4) Fourth digit A3 = 1, 12th digit A12 = 1: memory bank 1 can be determined.

When the image data for each pixel is serially sent from the system bus to the bus controller 12,
The above determination is made based on the fourth digit A3 and the twelfth digit of the address data to determine which memory bank the pixel should belong to. Further, for the next pixel, it is determined which memory bank the pixel should belong to.

Since the memory bank is specified for two consecutive pixels in this manner, the following four cases can be considered. Previous pixel: memory bank 0, current pixel: memory bank 0 Previous pixel: memory bank 0, current pixel: memory bank 1 Previous pixel: memory bank 1, current pixel: memory bank 0 Previous pixel: memory Bank 1, current pixel: memory bank 1 In this embodiment, whether or not to output the CAS signal is determined as follows.

If: CAS0-7 enable, CA
S8-f disable: CAS0-7 enable, CAS8-f enable: CAS0-7 enable, CAS8-f enable: CAS0-7 disable, CAS8-f
Enable By doing so, the following result is obtained.

When a horizontal line is drawn on the display screen of the CRT (see FIG. 1), the case of or
7 is also enabled and CAS8-f is also enabled. Therefore, writing to memory bank 0 and writing to memory bank 1 continue alternately. Also, when a vertical line is drawn on the display screen of the CRT (see FIG. 1), this is also the case, so writing to memory bank 0 and writing to memory bank 1 continue alternately.

Therefore, as explained in the conventional example,
When a vertical line is drawn on the display screen, the data can be processed and drawn at twice the speed as compared with the case where the vertical line is written only in one of the memory banks. In this embodiment, in the case of, only writing to the memory bank 0 continues,
In the case of 1, there is a drawback that only writing to the memory bank 1 continues, but these cases correspond to the case of drawing diagonally in FIG. Since such a case usually appears infrequently, even if the processing is partially delayed for this reason, the processing speed as a whole does not decrease so much, so that it is not a problem.

In the above embodiment, the display screen is a horizontal 204
There are 8 pixels and 1024 pixels in the vertical direction, and it is assumed that the pixels are divided by the memory bank every 8 pixels in the horizontal direction, but the size is not limited to this. It goes without saying that the invention can be carried out even in cases other than this size. However, if the size changes, the position of the memory bank identification bit shown in FIG. 2 also changes.

[0024]

As described above, according to the frame buffer access method of the present invention, when the frame buffer is subdivided into two memory banks and writing and reading are alternately performed for each memory bank, the display screen is displayed vertically and horizontally. Since the memory cells are divided in a grid pattern and different memory banks are used for the respective adjacent rectangular areas, for example, when the display screen is drawn horizontally or vertically, 2 The two memory banks can be efficiently used alternately. Therefore, the drawing speed can be increased up to twice as high as the conventional one, which is effective in the case of drawing a large number of vertical lines and horizontal lines in a field such as CAD.

[Brief description of drawings]

FIG. 1 is a diagram showing a correspondence between a memory bank according to the present invention and a display screen on a CRT.

FIG. 2 is a diagram showing a structure of a bit string forming one piece of image data.

FIG. 3 is a diagram in which four-digit numerical values are entered from the bottom for explanation of each pixel on the display screen.

FIG. 4 is a diagram showing a conventional correspondence between memory banks and display screens on a CRT.

FIG. 5 is an enlarged view for explaining in more detail the correspondence between memory banks and display screens on a CRT in the related art.

FIG. 6 is a block diagram for explaining a structure of a frame buffer and a connection state between the frame buffer and a bus controller.

FIG. 7 is a waveform diagram showing the timing of transmission of a signal RAS, a signal CAS, an address signal and the like.

FIG. 8 is a waveform diagram showing the timing of sending signals RAS, CAS, address signals, etc. when drawing vertical lines on the display screen of the CRT.

[Explanation of symbols]

 11 frame buffer 12 bus controller FB00-FB0f memory cell

Claims (1)

[Claims] 1. A frame buffer for storing image data is divided into two memory banks, and when a bus controller receives an access request signal to the frame buffer, based on address information included in the access request signal. Which memory bank to access, and based on this determination, specify the signal and column address used when specifying the row address of the memory cell for the memory cell of the memory bank. In a method of accessing a frame buffer that outputs a signal used at times and an address signal for designating a row address and a column address of a memory cell, which memory bank of the access request signal is to be accessed is specified. The address information for determining the display screen is divided into vertical and horizontal grids. , Divided frame buffer access method comprising the information for instructing to access different memory banks for each rectangular area each adjacent a.