JPH0514605Y2 - - Google Patents

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a dither conversion circuit, and particularly to a dither conversion circuit that can achieve high speed.

(Prior Art) An outline of a conventional dither conversion circuit will be explained using FIG.

In the figure, 1 is a comparison circuit that compares image information and a dither threshold value for each pixel, and 2 is a dither pattern memory that stores the dither threshold value. 3 takes in the bit clock and sends a control signal synchronized with this to the comparison circuit 1 and the address counter 4.
This is the CPU sent to. An address counter 4 sends an address signal to the dither pattern memory 2.

FIG. 7 shows an example of a 4×4 matrix dither pattern stored in the dither pattern memory 2. In FIG. As is well known, this dither pattern is the (4n+1)th (where n=0, 1,
2,..., the same applies hereafter) The dither threshold value in the first column is applied to the image information of the scanning line, and the dither threshold value in the second column is applied to the image information of the (4n+2)th scanning line.
For the image information of the (4n+3)th scanning line, the third
The dither threshold value of the fourth column is applied to the image information of the (4n+4)th scanning line.

Now, when pixel information consisting of 4 bits is inputted one by one to the comparator circuit 1 in synchronization with the bit clock, the dither pattern memory 2 outputs a column corresponding to the scanning line to which the pixel information belongs. The dither thresholds are read out one by one in synchronization with the bit clock. The comparison circuit 1 compares the pixel information with the dither threshold value, and if the former is larger than the latter, outputs dither image information of "1", for example,
Conversely, if it is smaller, dither image information of "0" is output.

In this way, all the pixel information input to the comparison circuit 1 is converted into binary dither image information.

(Problems to be solved by the invention) The above-mentioned conventional techniques had the following problems.

In the conventional dither conversion circuit, as described above, the dither threshold value set in the comparator circuit 1 is
Since the input pixel information is reset for each pixel, this processing takes time and is not suitable for high-speed dither conversion processing.

An object of the present invention is to speed up dither conversion processing.

(Means and operations for solving the problem) In order to solve the above problem, the present invention provides a dither pattern memory and a dither threshold value for one column read from the dither pattern memory. a plurality of holding means for holding in parallel, a plurality of comparison means for comparing each of the dither threshold values and image information in parallel, and outputs of the comparison means are synchronized one by one with a clock of the image information. By storing one row of dither threshold values in advance, it is no longer necessary to read out and load the dither threshold values one by one in synchronization with the reading of image information. The feature is that it speeds up the conversion process.

(Example) The present invention will be explained below with reference to an example. 1st
The figure shows a block diagram of the first embodiment of the present invention, and FIG. 2 shows a time chart of the main parts of the signal.

In FIG. 1, 11 is a CPU, and 12 is a dither pattern memory. This dither pattern memory 12 stores a dither pattern as shown in FIG. 13 is a port having at least two ports A and B;
Each of ports A and B has a data latching function. A currently commercially available IC (8255A-5) can be used as this port.
Reference numeral 14 designates four comparison circuits, the outputs of which are led to a selector 15 and selected cyclically.

Next, the operation of this embodiment will be explained with reference to FIG.

First, at time t ₁ , when the CUP 11 addresses the first two dither thresholds stored in the first column of the dither pattern memory 12, the dither thresholds "11" and "4" are set for the dither pattern. memory 1
2 to port 13. At this time, the CPU
Since port 11 outputs a select signal and selects port A of port 13, the dither threshold is latched to port A by write signal WR.

Next, at time t ₂ , the remaining two dither threshold values in the first column of the dither pattern memory 12 are "6".
and “9” are read out and transferred to port 13. At this time, since the CPU 11 selects port B of the ports 13 by the select signal, the dither threshold value is latched at port B by the write signal WR.

When the first column of dither thresholds is latched at port 13, each of the dither thresholds is latched to comparator circuit 14.
are supplied to each of them. That is, the first dither threshold value "11" is sent to the first comparison circuit 14a, the second dither threshold value "4" is sent to the second comparison circuit 14b, and the third dither threshold value "6" is sent to the third comparison circuit 14c. To,
The fourth dither threshold value "9" is the fourth comparator circuit 14d.
is supplied to

At time _t3 , image information _P1 , _P2 , _P3 , _P4 ,...
... are inputted sequentially, and a select signal is inputted to the selector 15 in synchronization with this. The selector 15 first selects the first comparison circuit 14a, and then sequentially selects the comparison circuits 14b, 14c, 14d, and 14a by clicking the sign. Therefore, the image information _P1 is simultaneously compared with the first to fourth dither threshold values by the first to fourth comparison circuits 14a to 14d, but only the comparison result of the first comparison circuit 14a is compared. It passes through the selector 15 and is extracted as dithered image information _D1 .

Next, when the image information P ₂ is input, the selector 15 selects the second comparison circuit 14b, so the comparison result between the image information P ₂ and the second dither threshold "4" is the dither Selector 15 as image information
is output through. Similarly, image information P ₃ ,
P ₄ , P ₅ , P ₆ , . . . are sequentially compared with the third, fourth, first, second, . . . dither threshold values, respectively, and the results are output as dither image information.

In this way, the first scanning line (line)
When all of the image information has been converted into dither image information, the CPU 11 accesses the dither pattern memory 12 at time _t4 , and the first dither threshold value "12" and "0" in the second column are Read out. At this time, the CPU 11 selects the port A of the ports 13, so when the write signal WR is input to the port 13, the two dither thresholds are latched to the port A. Further, at time _t5 , when the CPU 11 accesses the remaining two dither threshold values "2" and "14" in the second column of the dither pattern memory 12 and selects port B of the port 13, the write signal WR The two dither thresholds are latched to the port B at the timing of .

Therefore, the first to fourth dither thresholds of the second column latched to port 13 are the first to fourth dither thresholds, respectively.
is supplied to the comparison circuit.

At time t ₆ , the image information of the second scan line
When Q ₁ , Q ₂ , and Q ₃ are input to the comparator circuit 14,
Each image information is compared with the first to fourth dither threshold values. When the image information _Q1 is input to the comparison circuit 14, the selector 15 selects and outputs the output of the first comparison circuit 14. Further, when the image information _Q2 is input to the comparison circuit 14, the output of the second comparison circuit 14b is selected and output. At the same time, the third, fourth, first, second comparison circuits 14c, 14d, 14a, 14b, . . . are connected to the image information Q ₃ , Q ₄ , Q ₅ , Q ₆ , . select. In this way, the image information of the second scan line is converted to image information.

When this conversion is completed, the first two dither thresholds "7" and "8" of the third row surface are latched to port A of port 13 in the same manner as above, and then the remaining dither thresholds "10" and "8" are latched to port A of port 13. 5" is latched to port B. Then, the image information of the third scanning line is converted to dithered image information.

When all image information conversion for the third scan line is completed, the first two dither threshold values "3" and "15" in the fourth column are latched to port A of port 13, and then the remaining Two dither thresholds “13” and “1”
is latched to port B. When this latch is completed, the image information of the fourth scanning line is input to the comparator circuit 14 and converted into dithered image information in the same manner as described above.

When this fourth conversion is completed, the dither threshold value of the first column is latched to the port 13, and the image information of the fifth scan line is converted to dither image information. Thereafter, the above processing is repeated to convert the image information of all scanning lines into dithered image information.

According to this embodiment, the dither threshold value corresponding to one scanning line is read out in advance from the dither pattern memory and latched to the port, which eliminates the conventional method of reading out and loading the dither threshold value for each piece of image information. The processing time was reduced to about 1/3 compared to conventional equipment.

Next, the second embodiment of the present invention is shown in FIGS. 3 and 4.
This will be explained using figures. Figure 3 is a block diagram, Figure 4
The figure shows a time chart of the main parts of the signal.

This embodiment differs from the first embodiment in terms of configuration in that a first register 17a and a second register 17b are provided between the port 13 and the comparison circuit 14. In addition, for the same or equivalent items as in Figure 1,
The same symbols are attached.

Next, the operation of this embodiment will be explained with reference to FIG. The same operations as those in the first embodiment will not be explained.
Differences from the embodiment will be explained.

At time t ₁ , before scanning for reading the document is started, first, the first row of the dither pattern,
A second dither threshold is latched to port A of ports 13, and then at time _t2 the third and fourth dither thresholds of the first column are latched to port B of ports 13. Then, at time _t3 , the set clock is input to the first and second registers 17a and 17b. As a result, the first and second dither threshold values are stored in the first register 17a, and the third and fourth dither threshold values are stored in the second register 17a.
It is stored in b. When this operation is completed, scanning for reading the original is started, and the image information of the first scanning line is converted into dither image information by the same operation as in the first embodiment.

In this embodiment, while the image information of the first scanning line is being converted into dither image information, the first and second dither signals in the second column of the dither pattern are connected to port A of port 13. A threshold is latched to port A of port 13, and third and fourth dither thresholds are latched to port B. When the conversion process of the first scanning line is completed, the set clock is applied to the first and second registers 17a and 17b at time _t4 , and the set clock is applied to the first and second registers 17a and 17b.
The contents of 7b are converted into first and second dither threshold values and third and fourth dither threshold values in the second column of the dither pattern, respectively.

Subsequently, the image information of the second scanning line is transferred to the comparison circuit 14, and a process of converting this image information into dithered image information is executed.

When this conversion process starts, the dither threshold value in the third column of the dither pattern memory 12 is read out,
It is latched to port A and port B of port 13.

Thereafter, similar operations are repeated to continue the process of converting image information into dithered image information.

According to the second embodiment, while the image information of a scanning line is being converted into dither image information, the dither threshold value for converting the image information of the next scanning line into dither image information can be latched in the port 13. Therefore, the load to the registers 17a and 17b can be performed simply by inputting the set clock.
The conversion process can be performed at a higher speed than in the embodiment.

Comparing the conversion processing time of this embodiment with that of the conventional device, it is found that when reading an A4 size document, it took about 24 seconds with the conventional device.
In this example, it only took about 7 seconds, which was a significant reduction.

A circuit diagram embodying the second embodiment is shown in FIG. In the figure, parts corresponding to those in FIG. 3 are given the same reference numerals. As shown,
8255A-5 as port 13, register 17a
and LS273 as 17b, comparison circuit 14a~
As the selector 14d, an LS85 IC is used, and as the selector 15, an LS153 IC is used.

The details of this specific example almost correspond to those in FIG. 3, so the explanation thereof will be omitted, but the comparison circuits 14a to 14d of this specific example generate a logic "1" signal when the dither threshold value is larger than the image information. It is configured such that a logic "0" signal is output when the two are equal or smaller. This condition setting is for comparison circuit 1.
This is done by connecting the second, third and fourth pins 4a to 14d. Further, the lead wires marked with an x in the figure are not necessary for the operation of the present invention.

In the first and second embodiments described above, an example using a 4×4 matrix dither pattern was explained, but the present invention is not limited to this.
16×16 matrix or 2×2 matrix, etc.
Of course, the present invention can also be applied to conversion processing using an n×n (n=2, 3, 4, . . . ) dither pattern.

(Effects of the invention) As is clear from the above explanation, according to the present invention, the following effects are achieved.

In this invention, one of the columns in the dither pattern is latched to a port in advance, and this is compared with the image information read out by scanning the original, so that The conversion process eliminates the need to load/set dither thresholds. Therefore, the conversion process can be made approximately three times faster than conventional methods.

Furthermore, if the dither threshold value for the next scan line is set to the port during the conversion process of the previous scan line, the dither threshold value from the dither pattern memory to the port is set during the conversion process of the previous scan line. It can be done in between. Therefore, the time required for the setting need not be included in the time from the end of the previous scanning line to the transition to the next scanning line, so that the conversion process can be made faster.

[Brief explanation of the drawing]

Figures 1 and 3 are the first and second figures of the present invention, respectively.
A block diagram of the second embodiment, FIGS. 2 and 4 are time charts of the main parts of the signals in FIGS. 1 and 3, respectively, and FIG. 5 is a diagram showing a specific circuit example of the second embodiment. , Figure 6 is a block diagram of the conventional device,
FIG. 7 is a diagram showing an example of a 4×4 matrix dither pattern. 11...CPU, 12...Dither pattern memory, 13...Port, 14...Comparison circuit, 15
...Selector, 17a, 17b...Register.

Claims (1)

[Claims for Utility Model Registration] (1) A dither pattern memory and 1 read from the dither pattern memory.
a plurality of holding means for holding dither threshold values for columns in parallel; a plurality of comparison means for comparing each of the dither threshold values and image information in parallel; and a plurality of comparison means for comparing each of the dither threshold values with image information one by one. selection means for cyclically selecting in synchronization with the clock of the image information, and when the dither processing for one column of the image information is completed, the dither threshold values for the next column are held in the plurality of holding means. A dither conversion circuit characterized in that: (2) The dither conversion circuit according to claim 1, wherein the holding means for holding the dither threshold comprises a port having a latch function and a register connected to the port.