JPS63123171A - Data transfer device - Google Patents

Abstract

PURPOSE:To transfer transparent data and opaque data by one data transfer by calculating two pieces of transfer destination data so as to store the results in a transfer destination memory if a mask register shows an effective bit and if an opaque mode holds no transfer destination data and storing the transfer destination data as it is any cases apart from the above-mentioned case. CONSTITUTION:The logic '1' of the mask register 13 indicates the arithmetic effective bit position of a computing element 10, while logic '0' holds the transfer destination data as it is. If a flip flop 19 is of logic '1', that is called a transparent mode, and a background color that a background color register 22 shows is regarded as 'B'. The contents of a data bit 1 hold bits of the transfer destination data corresponding to the bit position 'B'. The bit position of the contents 'F' of the data register 1 executes operations specified by an arithmetic mode register 16 between two pieces of transfer destination data, and the results are stored in corresponding transfer destination bits. If the flip flop 19 is of logic '0', the contents of the data register 1 and the transfer destination data are calculated, and the results are stored in the transfer destination memory 11.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is a method of combining image data stored in a destination memory and source data in bit units that are less than or equal to the bit length that can be accessed in one memory. The present invention relates to a data transfer device that performs arithmetic operations between and writes the results into memory at high speed.

2. Prior Art As a conventional data transfer device, for example, Japanese Patent Laid-Open No. 81-9
This is shown in Japanese Patent No. 766.

FIG. 4 shows a block diagram of this conventional data transfer device, where 1 is a data register DBR12 storing source data, an address register 12 is an address register holding a word address of a destination, and 4 is a data register 1. 6. the memory to which the contents of are to be transferred; .

7 is a gate opened by the gate signals WT and RD, 8 is an arithmetic unit having a general-purpose register, 9 is a latch circuit for storing data to be sent to the transfer page 3, and 10 is connected between the data register 1 and the latch circuit 9. An arithmetic unit that performs operations on bits specified by a mask register, which will be described later; 11 is a bit pointer BP indicating the bit position of the transfer destination address; 12
are count up signal INC, counter down signal DE
C adds and subtracts the bit address by connecting the address register 2 and bit pointer BP, and 13 is the arithmetic unit 10.
a mask register MASK that specifies the operation valid bit of
14 is a decoder that decodes the contents of the pit pointer 11; 15 is a selection circuit that outputs either the contents of the mask register 13 or the output of the decoder 14 as calculation valid bit designation data to the arithmetic unit 10 according to the mask selection signal MSEL; The operation mode register RORR, 17, which specifies the operation of the operation unit 1Q, is a selection circuit, 18, which outputs either the operation mode register 16 or direct designation from the control unit to the operation unit as an operation mode designation signal, according to the operation designation selection signal R8EL. is a control unit that supplies control signals to each block.

In the conventional data transfer device configured as described above, the transfer source data is aligned with the transfer destination position in the arithmetic unit 8 and stored in the data register 1, and the word address of the transfer destination is stored in the address register 2. The bit position within the word is stored in the bit pointer 11. address register 2
The contents of the memory indicated by are held in the latch circuit 9. With the output of data register 1 and the output of latch circuit 9 as input,
The calculation is performed by the calculation unit 10 in the calculation mode specified by the calculation mode register 16. When the arithmetic unit 10 performs an operation, the valid bits of the operation designated by the contents of the mask register 13 output the above-mentioned operation result, and the output of the latch circuit other than the valid bits is output as is.

Problems to be Solved by the Invention However, with the above configuration, when transferring not only the character pattern but also the background of the character (opaque), for example when transferring character font data, the background It was necessary to perform data transfer twice and character pattern data transfer. Further, there is a problem in that it is not possible to save (transparent) the data of the transfer destination 51, -, except for the character pattern when it is colored.

In view of this, an object of the present invention is to provide a data transfer device that transfers background data and realizes transparency when colorized in one data transfer.

Means for Solving the Problems The present invention provides a register that holds transfer data, a latch circuit that holds transfer destination data, an arithmetic unit that inputs the respective outputs and performs arithmetic operations, and a register that holds transfer data and a latch circuit that holds transfer destination data. A flip-flop that indicates whether or not to save the pixel at the transfer destination, a detection circuit that detects a specific pixel from the data output from the register, a mask register that holds information on the operation valid bit of the arithmetic unit, and data transfer. This is a data transfer device equipped with an address register that stores a destination address.

Operation According to the above-described configuration, the present invention calculates the transfer source data and the transfer destination data and sends the result to the transfer destination when the pixel has a valid bit indicated by the mask register and is in opaque mode or does not hold transfer destination data. Store in memory. In cases other than the above, the transfer destination data is stored as is. As a result of this operation, in opaque mode, the transfer destination data is rewritten with respect to the valid bit indicated by the mask register, and in transparent mode, the transfer destination data indicated by the transfer source data is operated only on pixel positions that do not store the transfer destination data, and the results are transferred to the transfer destination. For other pixels, the original data is saved.

Embodiment FIG. 1 shows a block diagram in a first embodiment of the present invention, which deals with binary images. In Figure 1, 1 to 1B
has the same configuration as the conventional example shown in FIG. 19 is a flip-flop that indicates whether or not to save the destination pixel for a pixel of specific data among the transferred data during data transfer; 22 is a register that indicates the background color; and 21 is the data held by data register 1. ENOR circuit that detects the background color indicated by the background color register 22; 20 is a flip-flop 19;
The output of the ENOR circuit 21 and the output of the ENOR circuit 71, -
This gate outputs the mask register 13 using the NAND output as a gate signal, and indicates the operation valid bit of the arithmetic unit 1o.

The operation of the data transfer device of this embodiment configured as described above will be described below.

The transfer source data is aligned to the transfer destination position by the calculation unit 8 and stored in the data register 1, and the transfer destination address is stored in the address register 2.

The contents of the transfer destination memory indicated by the address register 2 are held in the latch circuit 9. The outputs of the data register 1 and the latch circuit 9 are respectively input to the arithmetic unit 1o. The calculation mode of the calculation unit 1o is designated by the calculation mode register 16.

Next, the second part about transparency, opacity mode, and mask register.
This will be explained using figures.

A logic 1 in the mask register 13 indicates the operation valid bit position of the arithmetic unit 1o, and a logic 0 stores the data at the transfer destination as is. When the flip-flop 19 is logic 1, it is called transparent mode, and the background color indicated by the background color register 22 is set to "B".
shall be. The contents of the data register 1 save the bit of the transfer destination data corresponding to the pit position of "B". For this purpose, the operation valid bit input to the arithmetic unit 1o is used to calculate the pit position and output the output of the latch circuit as it is. At the pit position where the content of the data register 1 is "F", an operation specified by the operation mode register 16 is executed between the transfer source data and the transfer destination data, and the result is stored in the corresponding transfer destination bit. When the flip-flop 19 is at logic 0, it is called an opaque state, and an operation is performed between the contents of the data register 1 and the destination data, and the result is stored in the destination memory. In this case, operations are performed on the transfer destination data regardless of the contents of the data in the data register 1.

While sequentially transferring adjacent addresses to the memory, the address in the address register 2 is updated by adding 1 or subtracting 1 using the 1 adder/subtractor 12 every time one data transfer is completed.

As described above, according to this embodiment, by using the ENOR circuit 21 as the background data detection circuit, it is possible to easily realize the transparent and opaque modes of a binary image.

FIG. 3 is a block diagram of a data transfer device showing a second embodiment of the present invention. In FIG. 3, numerals 1 to 21 have the same structure as in FIG. 1. The difference from the configuration shown in FIG. 1 is that the memory 41 selection circuits 6, 7 .
Data register 1° latch circuit 9. Arithmetic unit 10. game)
2o, ENOR circuit 21. The point is that the background register 22 is provided with a plurality of bits in order to express one pixel with a plurality of bits.

The operation of the data transfer device of the second embodiment configured as described above will be described below.

The transfer source data is matched with the transfer destination position by the calculation unit 8 and stored in the data register 1 for each color plane.

Store the data transfer destination address in address register 2,
The contents of the address indicated by the address register 2 are read and held in the latch circuit 9 for each memory plane. Data for each memory plane of the data register 1 and data for each memory plane of the latch circuit are input to the 10-page arithmetic unit 1o corresponding to each plane. The calculation mode of each calculation unit 1o is designated by the calculation mode register 16.

A logic 1 in the mask register 13 indicates the operation valid bit position of the arithmetic unit 1o, and a logic 0 stores the data at the transfer destination as is. When the flip-flop 19 is at logic 1, the pixel indicated by each memory plane of the data register 1 stores the pixel of the destination data corresponding to the pit position that matches the color indicated by the background color register 22. For this purpose, the output of the latch circuit for the operation at the bit position is output as is to the operation valid bit input to the arithmetic unit 10.

For bit positions other than the above bit positions of the data register, calculations are performed on the transfer source data and transfer destination data for each memory plane,
Store the result in the destination bit of the corresponding memory plane. When the flip-flop 19 is at logic 0, an operation is performed for each memory plane of the data register 1 and latch circuit 9, and the results are stored in each memory plane of the transfer destination memory.

During successive transfers of adjacent addresses to the memory, the address in the address register 2 is updated by adding or subtracting 1 using the 1 adder/subtractor 12 every time one transfer is completed.

As described above, according to this embodiment, by having a plurality of memories, data registers, launch circuits, arithmetic units, and background color data detection circuits, data transfer of transparent and opaque color images can be realized.

Details of the invention As described, according to the present invention, transparent.

Transparent data transfer can be achieved with a single data transfer, and can be similarly extended to color images, which has great practical effects.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data transfer device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of processing in the same embodiment, and FIG. 3 is a block diagram of a data transfer device according to another embodiment of the present invention. FIG. 4 is a block diagram of a conventional data transfer device. 1...Data register, 2...Address register, 4...Memory, 6.7...
・Gate, 8...Arithmetic unit, 9...Latch circuit, 10...Arithmetic unit, 11...Bit pointer, 12...1 Adder/subtractor, 13...
...Mask register, 14...Decoder, 1
6゜17... Selection circuit, 16... Arithmetic mode register, 18... Control block, 19
...Flip-flop, 20...Gate, 21...ENOR circuit, 22...
Background color register. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 (T=O) Figure 3 Nomigo y 22 BR 1st-19/a Tsukasa 219
20. /610 2'/ WT 5 ARBP±1 Control unit 1. , Trivia 9/ Figure 4

Claims (1)

[Claims] A first register that holds transfer data, an address register that holds a transfer destination address that stores the data, a latch circuit that holds the contents of the memory indicated by the address register, and an output of the first register. an arithmetic unit that takes the output of the latch circuit as a first input and performs a desired operation between the input data; a control unit that generates the type of operation of the arithmetic unit; and an operation enabler of the arithmetic unit; A mask register that holds bit information, a flip-flop that indicates whether or not to save the destination pixel for a pixel of specific data among the transferred data, and detects specific data from the data output from the first register. a detection circuit;
N of the output of the flip-flop and the output of the detection circuit
The AND output is ANDed with the output of the mask register, and for bits for which logic 1 is specified, a desired operation result is output between the data of the first register and the latch circuit, and logic 0 is specified. A data transfer device characterized in that the output of an arithmetic unit that directly outputs the output of a latch circuit is transferred to the bit that has been input.