JPS6316381A - Memory device - Google Patents

Abstract

PURPOSE:To execute at a high speed a color code processing such as a painting- out processing in a closed area, by taking the color code processing into the inside of a memory. CONSTITUTION:In case of painting-out in a closed area, a color code of a boundary point, and a color code used for painting-out are set to a register 106 and a register 105, respectively. A read-out data from a memory cell array 101 selected by an ADR signal is inputted to a comparator 107, and compared with a boundary color code. When said data has allowed to coincide with the boundary color code, the comparator 107 outputs an EQ signal to a processor. The processor simultaneously the EQ signals from memory devices of the number of pieces of word width, handles the color code as a binary signal, and decides a part of logic '1' to be a picture element of the boundary color code in a word. The processor starts painting-out by a designated color between the boundaries, outputs a WE signal, and executes an arithmetic operation between the array 101 and the register 105.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a memory device for use as a frame buffer in a bitmap display device.

2. Description of the Related Art A conventional memory device is, for example, the one shown in FIG. In the figure, 1 is a memory cell array which is a collection of memory cells, the memory cells are selected by the address signal DB (1 word n pit), 2 is a write cycle, and 10 is the write data from the port and the data in the memory cell. 3 is a mask register that controls writing on a bit-by-bit basis; 4 is a mask register that stores one row of data in the memory cell, and is read/written independently of the Ilo port using the S I10 port. This is a data register that can perform

In the conventional memory device 10 configured as described above, as shown in FIG. is updated (drawing). Also, a video signal is output from the SI10 port to the RT12 port (display).

Problems to be Solved by the Invention However, in the above configuration, when one pixel is expressed with multiple values (color code or gradation code, hereinafter referred to as color code) as shown in FIG. In Figure 4a, R, G,
B, I shows the case of 4 bits/pixel), processor 1
1, each pixel must be recognized by a color code, and the data bus width is fixed by the processor 11 (
For example, 16 pinots), when each pixel is represented by a color code compared to a binary image, the processor 11 has the problem that the number of pixels that can be processed at once decreases, reducing the processing speed (data bus width If the image size is 16 bits and 4 bits/pixel, the processor 11 can handle only 4 pixels at the same time, which requires 4 times the processing time compared to a binary image).

SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a memory device that can perform color code processing at high speed, particularly fill-in processing in a closed area.

Means for Solving the Problems The present invention is a memory device that includes a first register that holds a write pattern, a second register that holds a comparison pattern, and a comparator that compares read data.

According to the above-described configuration, the present invention stores the contents of the first register in the memory cell in synchronization with the write signal (VX) when writing, and stores the contents of the first register in the memory cell in synchronization with the write signal (VX) when writing, and stores the contents of the first register in synchronization with the data read from the memory cell and the second register when reading. By comparing two turns of comparison and outputting a match/mismatch signal to the outside, the processor does not need to process the color code, and processes pixels as binary values no matter how many pits the color code has. This allows for faster processing.

Embodiment FIG. 1 shows a block diagram of a memory device in an embodiment of the present invention. 101-104 correspond to FIG. 3 1-4, respectively. 105 in FIG. 1 is a write data register (first register) that holds a write pattern;
Reference numeral 106 denotes a comparison data register (
A second register 107 is a comparator that compares the read data from the register 106 and the memory cell array 101 and generates a match signal KQ of "°1" when they match according to the result.

The operation of the memory device 110 of this embodiment configured as described above will be described below.

The write data register 1o5. is written using the 5I10 port in the display blanking interval. A pattern is set in the read data register 106. For example, in the case of filling in a closed area, the color code of the boundary point is set in the register 106, and the color code used for filling is set in the register 105. Read data from the memory cell array 101 selected by the ADH signal is input to the comparator 107 and compared with the boundary color code. Comparator 107 if it matches the border color code
The processor 11 outputs the KEQ signal as shown in FIG. 2(b). Here, the processor 11 reads the EQ multiplied signals from the word-width number of memory devices at once (for example, if the word width is 16 bits, how many bits (n bits) does the color code represent? Regardless of the presence 2
Can be treated as a value signal, with logic 1 in a word
'' is the pixel of the boundary color code.When the processor 11V'i determines the boundary, it fills in with the specified color between the boundaries, and the 6° memory device that generates the WX signal receives the WX signal. Then, the result of a predetermined operation performed between the data already stored in the memory cell array 101 selected by the ADH signal and the register 105 is stored.

As described above, according to this embodiment, by incorporating the registers that hold the write color code and the read color code in the memory device, the processor can read pixels of n-bit color codes as shown in FIG. 2(a). can be treated as a binary image.

Note that in this embodiment, register 105. register 1
06 and the mask register 103 are set using 10 ports, but a dedicated port may be provided.

Further, the EQ multiplied signal and the WE multiplied signal may be multiplexed to one input/output terminal.

As described in detail, according to the present invention, by incorporating color code processing into the memory, color code processing such as filling in a closed area can be performed at high speed, and its practical effects can be achieved. is big.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a memory device according to an embodiment of the present invention, FIG. 2 is a diagram of a graphic system using the memory device of the same embodiment, FIG. 3 is a block diagram of a conventional memory device, and FIG. 4 is a block diagram of a conventional memory device. 1 is a diagram of a graphics system using a conventional memory device; FIG. 101...Memory cell array, 102...
...Arithmetic unit, 1o3...Mask register, 10
4... Data register, 1o5... Write data register, 106... Comparison data register, 107... Comparator. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 (■ <b) Figure 3

Claims (1)

[Claims] a memory cell array that is a collection of memory cells selected by an address signal; a data register that stores data for one row of the memory cell array and sequentially outputs the data;
A first register that holds a first pattern performs a logical operation between the data already stored in the memory cell and the first pattern held in the first register, and outputs the result to the memory cell. an arithmetic unit; a mask register that specifies control on a bit-by-bit basis when storing the output of the arithmetic unit in a memory cell; a second register that holds a second pattern; 1. A memory device comprising a comparator that performs a comparison with a second pattern held by a second register.