JPH0117190B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a mask calculation circuit that can easily change the mask position and size.

Generally, when handling image data in graphic processing, the processing unit is a rectangular area, which is cut out from the image memory, and the cut out rectangular area is further divided into areas of arbitrary size, and calculations are performed on the divided small areas. Operations such as , etc. are often performed. Handling image data in units of rectangular areas is advantageous when performing address operations when reading from memory, and it is of course possible to read out areas of any size from any location in memory space using software. However, since the access time is long and the graphic processing takes a lot of time, various hardware have been devised to cut out a rectangular area at high speed and process the data using a dedicated image memory and a dedicated bus line.

However, when performing calculations on a rectangular area using hardware, it is easy to configure a circuit for a rectangular area with a fixed size, but for a variable rectangular area, buffer memory configuration, address calculation, etc. are complicated and the circuit configuration is difficult. becomes complicated. The present invention aims to provide a circuit that can easily carry out a mask operation on a rectangular area cut out to an arbitrary size from an arbitrary part of an image memory, and further on arbitrarily divided areas. is a circuit that performs a mask operation on image data of a predetermined portion of an arbitrary area within the storage area of an image memory, and divides the readout output for each scanning line of the image memory into a plurality of parts, and outputs one of them as an address signal. a first plurality of read-only memories receiving a plurality of read-only memories as part of the memory;
and a plurality of read-only memories. This will be explained in detail below with reference to the drawings.

FIG. 1 shows an outline of the graphic processing system, in which 10 is an image memory, 12 is an image data bus, 14 is a mask circuit, and 16 is an address control section. The image memory 10 is expressed two-dimensionally as shown in FIG. 2, and is, for example, a matrix plane with N rows and N columns.
Two-dimensional image data can be written to this. An n×n rectangular area following an arbitrary point x, y of this N×N plane image data is extracted, and a mask operation is performed on a part of this rectangular area. The operation of cutting out a rectangular area from the image memory 10 can be performed by the circuit shown in FIG. In this figure, 18 is a counter which receives the timing signal _S2 and counts it to generate an address signal for the read-only memory (ROM) 20. The ROM 20 also has a storage area of N×N like the image memory 10 in FIG.
0 also receives the same timing signal and counts it to create an address signal, so the ROM 20 is synchronized with the image memory 10 and memory cells at the same address are accessed. In the ROM 20, data "1" is written to memory cells in an n x n area starting from the positions x and y, and data "0" is written to memory cells in other areas. While the rectangular area is being accessed, the AND gate G is open and the readout output _S1 of the image memory 10 is passed through, and while other areas are being accessed, the gate G is closed, thus cutting out the n×n rectangular area. Ru.

However, in ROM20, if the starting point address x, y of the rectangular area changes, or if the size n×n changes,
The ROM 20 itself must be replaced, which is troublesome. It is desirable that the region to be computed can be changed in various ways as described above. FIG. 4 shows another example of a rectangular area, where a, b, and c are vertically divided examples, in which the N×N image memory storage area is divided into three equal parts by a vertical line, and the left side is shown with diagonal lines. In this example, the right side and center are rectangular areas, and d, e, and f are divided into three equal parts by a horizontal line, and the upper, lower, and center areas are rectangular areas. The image memory 10 is read by main scanning in the horizontal direction and sub-scanning in the vertical direction. Since the calculation target area changes in various ways in this way, it is desired to have hardware that can easily handle changes in the starting point coordinates x, y, size n×n, etc., using software, for example.

5 and 6 illustrate one embodiment of the invention. FIG. 5 shows a circuit that generates a readout output for one scanning line of the image memory 10, 22a, 22b, 22
c... is a shift register of multiple a bits,
A plurality of b are provided (a×b=N), and each is connected in cascade. These registers sequentially take in the readout output _S1 of the memory 10 using the timing signal _S2 , so that the output DO from each register stage is the same as the readout output of one scanning line of the N-bit memory 10. However, there is a delay of one scanning period when all outputs are available. Such output DO is ROM2 in Figure 6.
6a, 26b... are input. FIG. 6 shows ROM groups 24 and 26 (a, b,
c . . . are subscripts for distinguishing each other), and form an n×N mask. The front stage ROM24 is the rear stage ROM24.
The ROM 26 is used for control, and the latter ROM 26 is used for calculation. For example, an 8-bit control signal _S3 is input to the pre-stage ROM 24 to specify an area. For example, signal S ₃ causes only ROM24a to switch to the subsequent ROM26.
ROM24b, 24c...
. . . When the subsequent ROM is disabled (for example, always outputs "0"), the calculation area shown in FIG. 4a is set. However, here n is ROM
It is equal to the number of bits of the output DO input to 26a.
If n is large, the subsequent ROM26b, 26
All you have to do is enable c... Further, when the region to be calculated is in the center as shown in FIG. 4c, the corresponding ROMs such as 26c and 26d may be enabled, and the ROMs before and after it may be disabled. Furthermore, if the area is taken horizontally as shown in Figure 4 d, e, f, the scanning direction must be reversed, or the ROM
An appropriate method may be used, such as enabling all of 26 and providing a separate gate to prohibit the portion corresponding to the horizontal scanning output outside the target area.

The subsequent ROM 26 receives “1” in the input signal bit.
Outputs calculation results such as counting the number of (black) pieces. This uses the signal from the previous stage ROM 24 and the corresponding ROM input portion of the output DO as an address signal,
This is done by accessing with the signal and reading the stored contents of the address. For example, ROM26a
The signal from the ROM 24a that is input to the ROM 24a is 4 bits of 1111 (“1” indicates “valid”, so in this case, it indicates that all DO components DOa are adopted to the ROM 26a), and the DOa input to the ROM 26a is 0111. Assuming that there are 4 bits, the above calculation result can be output by writing data "3" to address 11110111 of the ROM 26a. other
The same applies to ROM. Note that when transmitting the output of the ROM 26 in series, the strobe signal _S4 is raised to perform reading when the input signals are complete. Also, with this method, the front ROM 24 is the rear ROM
It is possible to determine not only whether it is valid or invalid, but also how many bits of the DO component of the input should be adopted, and therefore to set the calculation area more precisely (setting the calculation target area within the above-mentioned rectangular area). For example, in the example above
If the output of ROM24a is 0111, this indicates constant counting of the following 3 bits except for the first bit of DOa, so ROM26a inputs 01110111.
In response, it outputs "3" (this is stored in advance. Of course, "3" is also written to address 01111111). By the way, ROM24
If the output is 0000, this indicates that the subsequent ROM is not selected. Furthermore, if the output of the ROM 24 includes an instruction bit indicating whether the object to be counted is white bits or black bits, white bit counting can be performed instead of black bit counting.

In FIG. 7, another set of pre-stage ROM for area determination is added, and the ROM 24 is configured to access the post-stage ROM 26 by performing a wired OR. In this way, the calculation target area can be set in the form of an island within the N×N memory area as shown in FIG. For example, ROM24 is from x to x
+n, the corresponding ROM26 is enabled,
If the ROM 28 is enabled only during the period when sub-scanning is performed between y and y+n, and disabled during other periods, n×
n areas are set.

ROM24, 26, 28 in Figures 6 and 7
If it is made into a programmable ROM, it can be freely rewritten, increasing flexibility even further.

As explained above, according to the present invention, a mask circuit is provided which sets an n×n rectangular area at any point x, y in an N×N memory area and performs a required operation on a desired portion in the area. be able to. use
Since the number of ROMs can be increased or decreased as appropriate, it is easy to deal with increases or decreases in the memory area, and using PROM as the ROM provides various advantages such as increased flexibility.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an overview of the image data processing system, FIG. 2 is an explanatory diagram of a rectangular area, FIG. 3 is a block diagram showing an example of a mask circuit, and FIG. 4 is an explanatory diagram of various rectangular areas. 5 to 7 show embodiments of the present invention, FIG. 5 is a block diagram of a circuit that generates a delayed output for each scanning line, and FIGS. 6 and 7 are block diagrams of a mask processing circuit section. be. In the drawing, 10 is an image memory, n×n rectangles are arbitrary areas 26a, 26b, . . . are the first ROM group, 2
4a, 24b, . . . are the second ROM group.

Claims (1)

[Claims] 1. In a circuit that performs a mask operation on image data of a predetermined portion of an arbitrary area within the storage area of an image memory, one of the readout outputs _S1 for each scanning line of the image memory is divided into a plurality of pieces. a first plurality of read-only memories 26a, . . . receiving part of the address signal DOa, . . . and each of the first plurality of read-only memories 26a, . A mask arithmetic circuit comprising a second plurality of read-only memories 24a, .