JP2002216128A - Logical filter and its control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a logical filter and its control method to enable execution of a filter processing by reading data of a plurality of pixels in a space area of a desired position to be required for the filter processing once while enabling the filter processing again by storing an image to which the filter processing is executed. SOLUTION: When the filter processing is executed to a 3×3 pixel area in an inputted image, nine memories 302-1 to 9 are prepared. Then when inputted image data is stored in the respective memories, it is stored by providing offset equivalent to deviation quantity of the respective pixel positions to constitute the pixel area. When pixel data of a position A is read, the data of 3×3 pixels of an area 310 is read at once as a result by constituting the respective memories to have the same address space from a processor. Read pixel data group is transferred to the filter processing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a logic filter device and a control method thereof.

[0002]

2. Description of the Related Art In image processing, for example, in a pixel block unit of a binary image composed of n.times.m pixels, a pixel block is located at a center position according to a logical pattern of "1" and "0". There is a process of outputting a logical operation result (logical filter processing result) for a pixel.

For example, when detecting an isolated pixel, first, input image data is binarized (if the input pixel is 8 bits, it is binarized based on whether or not it is larger than a threshold value, for example, "30").
And store it in the image memory. And 3 × 3 9
A pixel is read out, and its central pixel is “1”,
When all the pixels are “0”, it is determined that the center pixel (pixel of interest) is an isolated point. The determination result is output as binary data. For example, if "1", the target pixel is treated as an isolated pixel, and if "0", it is treated as a non-isolated pixel, and is passed to various subsequent processes.

In order to increase the processing speed during the above processing, a look-up table (LUT) is generally used in many cases. The look-up table (LUT) is realized by a memory element, and in the above case, receives a 9-bit (9-pixel) address signal and outputs 1-bit. In other words, “1” or “0”, which is the result of determination when input as a 9-bit address, is stored in the lookup table in advance. As a result, the process of determining whether each pixel is "1" or "0" is substantially unnecessary, and 1-bit output can be performed from the memory at the timing when the values of 9 pixels are input. Therefore, the speed of the logical filter processing can be increased.

[0005]

However, in order to obtain nine pixels of data (9 bits) to be supplied to the look-up table, nine random read accesses to the image memory are required after all. Is required.

To solve such a problem, a circuit configuration as shown in FIG. 6 may be adopted. Less than,
The illustrated configuration and operation will be described.

The analog image signal input from the input terminal 7 is converted into, for example, 8-bit digital data per pixel by the A / D converter 1 and compared with a threshold value, for example, "30" by the binarization circuit 2. To binarize. The binarized result is stored as binary data 8 in the latch group 5 and supplied to the FIFO memory 3. FIFO memory 3
Has a memory capacity for one line of an image, so that the binary data 9 output from the FIFO memory 3 is
The binary data 8 is delayed by one line from the binary data 8. Similarly, the output of the FIFO memory 3 is supplied to the FIFO memory 4, where the signal 10 which is further delayed by one line is output.
Generate

Accordingly, when the signal from the FIFO 3 is used as a target line, the data after one line is output from the binarization circuit 2 and the data before one line is output from the FIFO memory 4, and data for a total of three lines is output. The data is supplied to the latch group 5.

As shown in the figure, the latch group 105 has three latches for each line, and as a result, stores and holds 3 × 3 two-dimensional binary data. Therefore, by supplying the data from each latch to the LUT 6 as an address, a logical filter process can be performed.

According to the above configuration, the configuration can be realized by hardware, data of 3 × 3 pixels is generated at one time,
It will be supplied to the lookup table. Therefore, the processing speed can be made high.

However, such a configuration has the following problems.

I) To perform the filter processing again,
It is necessary to input the image signal again.

Ii) The order of the filter processing is fixed,
For example, filter processing cannot be performed on 3 × 3 pixels at a desired position (random access is not possible).

The present invention has been made in view of such a problem, and it is necessary to perform the filtering process while storing the image to be filtered while enabling the filtering process again.
An object of the present invention is to provide a logical filter device and a control method thereof, which enable data of a plurality of pixels in a spatial region at a desired position to be read at a time and to perform a filtering process.

[0015]

In order to solve such a problem, for example, a logical filter device of the present invention has the following configuration. That is, a logical filter device that performs arithmetic processing on a pixel region formed by a pixel of interest in the input image data and a pixel data group around the pixel of interest, has the same address space, and constitutes the pixel region When storing the input image data in the memory group and the memory group having the number N of pixels, an offset corresponding to each pixel position of the pixel area is given to each of the first to Nth memories of the memory group. Reading means for supplying and reading a common address signal to the memory group; inputting a pixel data group read from the memory group by the reading means; And filter means for performing logical operation processing.

[0016]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of the image processing apparatus according to the embodiment. In the figure, reference numeral 100 denotes a CPU for controlling the entire apparatus, and reference numeral 200 denotes an input terminal for inputting image data. In the embodiment, a non-interlaced image signal is input. 300 represents the input image signal as A
This is a memory unit for temporarily storing digital binary data after the / D conversion, and includes a memory control unit 301 and a memory 302 as shown. Reference numeral 400 denotes a look-up table (LUT) stored in the memory unit 300 for filtering on a 3 × 3 pixel basis, and 500 denotes an LUT 40
An image processing circuit that performs various processes based on the data filtered by 0 (since it is not directly related to the present invention,
The description is omitted).

In the above configuration, the memory unit 300 and the LU
The logic filter device of the present embodiment is configured by T400.

In the present embodiment, the logical filter device is n
This is effective for the xm pixel block, but for simplicity, here, for the 3x3 pixel block,
An example will be described in which it is determined whether or not the center pixel is an isolated pixel, and the determination result (“1” when the pixel is an isolated pixel, “0” when the pixel is a non-isolated pixel) is output to the image processing circuit 500. . Therefore, the memory section 300 includes nine memory chips. In this connection, the LUT 40
The address signal to 0 is also 9 bits. When 3 × 3 pixels are arranged in a line (bit 0 to bit 8), and the center pixel of the 3 × 3 pixel is located at bit 4, the LUT 400 has the address “00000010000B (B indicates a binary number)”.
"1" is stored and stored, and "0" is stored in other address positions.

The logical filter device of the embodiment for realizing the above object further has the following features.

I). It is possible to repeat the filtering process many times.

Ii). Filtering of input image data can be performed not on a fixed order but on a 3 × 3 pixel block at a desired position (random access).

Iii). An access for reading data of 9 (= 3 × 3) pixels including the target pixel is realized at one time.

The feature of the embodiment lies in the memory section 300 in FIG. 1. In order to explain the detailed operation, the principle will first be described with reference to FIG.

Each of the nine memories provided in the memory section 200 is a memory for storing binary image data (1 pixel = 1 bit), and each is an independent memory chip. Each of the memory chips 302-1 and 302-2,
... 302-9.

Further, from the CPU 100, each memory chip has the same address space (the CPU 10
0 uses a common address when accessing each memory chip).

In the embodiment, each of the memory chips 30
When storing the binary image data of the input image data in 2-1 to 9-1, the binary image data is written at an address position shifted by one pixel as shown in FIG.

That is, assuming that x and y are writing positions when binary data is stored in the address space of the memory 302-5, binary data at the same pixel position in the same image is written to the memory chip 302-1. In some cases, (x-1, y-
Write to the address position of 1). Other memory chip 30
2-2 to 9 are also written in the positions as shown in the figure.

As a result, in the region except for the upper two horizontal lines and the left two vertical lines in FIG. 2, nine memory spaces overlap each other.

As described above, the memory chip 302
-1 to 9 have the same address space as viewed from the CPU 100. Therefore, for example, when the binary data (total 9 bits) stored in each of the memory chips 302-1 to 30-9 is read from the memory chips 302-1 to 30-9 by addressing the position A shown in FIG. 3
Centering on the binary data read from 02-5, 3
Reading of × 3 binary pixel data succeeds. If the read 9 pixels (9 bits) are output to the LUT 400, the LUT 400 outputs the result of determining the isolated pixel.

FIG. 3 shows a specific configuration of the memory section 300 in the embodiment for realizing the above operation, and the operation will be described.

In the figure, reference numeral 31 denotes an A / D converter for converting an image signal (non-interlaced signal) input from an input terminal 200 into digital data, and 32 denotes a digital data which is 2
This is a binarization circuit that converts the data into value data (1 pixel = 1 bit). Reference numeral 33 denotes a synchronization signal generation circuit that generates various synchronization signals based on the horizontal and vertical synchronization signals in the image signal supplied from the input terminal 200. Gates 34-1 to 3-9 supply signals from the binarization circuit 32 to the memory chips 302-1 to 30-9 based on signals G0 and G1 (logically inverted signals of G0) from the CPU 100, or Chip 3
This switches whether data read from 02-1 to 02-9 is output to the LUT 400.

A counter 35 counts the pixel clock from the synchronizing signal generation circuit 33, outputs the value being counted as an address signal, and resets each time one frame of image data is input. The counter is reset by a signal. An offset register 36 stores an initial address (offset address) of the counter 35. 37 indicates one of the address from the CPU 100 and the address from the counter 35 as C
The selector is selected based on an instruction signal from the PU 100. Reference numeral 38 denotes a register for holding a signal for setting whether or not the memory chips 302-1 to 30-9 are in a read state, and 39, a register for holding a signal whether or not to activate the memory chips 302-1 to 30-9. It is.

In the above configuration, the reference numerals 31 to 39 constitute the memory control circuit 301 of FIG.

Next, the operation in this configuration will be described. When inputting image data from the input terminal 200, C
The PU 100 activates the gate signal G0 so as to supply the signal from the binarization circuit 32 to the memory chips 302-1 to 30-9, and makes the registers 38 and 39 writable only to the memory 302-1. Write data for Then, "0" is set as an initial value in the offset register 36, and the selector 37 is set to select an address signal from the counter 35.

As a result, the input image signal is converted into digital data by the A / D converter 31, and the binary signal by the binarization circuit 32 is supplied to each of the memory chips 302-1 to 30-9. However, at this stage, the memory chip 302
Since only -1 is in a writable state, as a result, binary data corresponding to the input image data is written only to the memory chip 302-1. At this time, since the value set in the offset register 36 is "0", the data is written from the address "0" of the memory chip 302-1.

When the writing of one frame of the binary image to the memory chip 302-1 is completed, the CP
U100 sets writing to only the memory chip 302-2, and sets "1" to the offset register 36. By this, 2 of the next frame
The value image is written from the address position shifted by one pixel with respect to the memory chip 302-1.

Hereinafter, when writing to the memory chip 302-3, only the memory chip is made valid, and "2" is set in the offset register 36. Easy to understand.

The initial value held in the offset register 36 when writing to the subsequent memory 302-4 is:
This value depends on the number of pixels in the horizontal direction of the input image. For example, when the input image data is 500 × 500 pixels, “500” may be set in the offset register 36. As a result, writing is performed from the position shifted by one line to the memory chip 302-1. The value set in the offset register 36 when writing to the memory chip 302-5 is "501" (=
500 + 1), and becomes "502" when writing to the memory chip 302-6. A similar reason is that when writing to the memory chip 302-7, "1000" (2
Is set), and the memory chip 302 is set.
In the case of -8, "1001" may be set, and in the case of the memory chip 302-9, "1002" may be set. Of course, when writing binary data to each memory chip, the registers 38, 3
9 will be updated.

When the writing of binary images for nine frames into the memory chips 302-1 to 30-9 is completed as described above, each of the memory chips 302-1 to 302-1 is consequently obtained in a state equivalent to that shown in FIG. 9 stores binary data.

The CPU 100 activates the gate signal G1 and this time, all the memory chips 302-1
The signals supplied to the output enable (OE) terminal and the chip select (C / S) terminal are made active for .about.9. Then, the CPU 100
A setting signal is output so as to select an address from.

Thereafter, the CPU 100 may supply an arbitrary address signal. The binary data held in each of the memory chips 302-1 to 30-9 specified at the address position is read out, output to the LUT 400, and the filtering process is executed. It is to be noted that, as described with reference to FIG.
It is data of 9 pixels of the pixel block, that is, data of 9 bits (signals B0 to B8 in FIG. 3).

Since the address output by the CPU 100 has no offset, the address is output to an address space equivalent to the first memory chip 302-1 when the binary image data is written. Therefore, in order to read 9 pixels at an address corresponding to the center pixel position of the 3 × 3 pixel block, the corresponding offset address may be added by internal processing on the CPU 100 side. However, when writing a binary image to the memory chips 302-1 to 30-9, the value set in the offset register 36 for the memory chip 302-5 is set to "0", and when writing to other memory chips, the shift amount is set. May be set in the offset register 36. For example, “−501” is set for the memory chip 302-1. By doing so, the CPU 100 can specify the address of the central pixel of 3 × 3 pixels.

In any case, if the CPU 100 increments the address by "1", the same filter processing as in FIG. 6 can be realized. In some cases, if the address is increased by "n" every time addressing is performed, filtering at discrete pixel positions becomes possible. Further, the filtering process can be performed only on a certain region of interest, and there is no restriction on the order of the filtering process.

In the configuration shown in FIG. 6, the number of pixels constituting one line of the image is fixed. However, according to the present embodiment, image data of an arbitrary size is handled by the value given to the offset register 36. become able to.

In the above embodiment, the memory chip 3
When writing the binary image data in 02-1 to 02-9, the switching was performed every time one frame was input. That is, the binary data written in each of the memory chips 302-1 to 302-9 is an image that is temporally different. This is particularly effective as long as the object in the image to be processed does not move or the entire image does not change. On the contrary, it can be realized as a filter for detecting the moving amount in the case of a moving image.

Also, all the memory chips 302-1 to 309-1
The same data may be stored in time. When storing the same data in time, FIG.
The configuration shown in FIG.

That is, the circuits 40 and 4 delay the time until the binary data output from the binarization circuit 32 reaches each memory by the amount corresponding to the shift amount shown in FIG.
1 ... are interposed. The circuits 40, 41, etc. may be flip-flops or FIFOs. In this case, the offset register 36 in FIG. 3 becomes unnecessary.

Further, in the embodiment, a filter that allows only an isolated pixel to pass has been described as an example. However, the present invention is not limited to this, and various filters may be employed.

The memory chips 302-1 to 30-9 store 1-bit data (binary data). However, the number of bits per pixel may be 2 bits or more.

Further, the output of the LUT 400 is not limited to one bit, but may be a plurality of bits.

Further, in the embodiment, only one look-up table has been described. However, as shown in FIG. 5, a plurality of LUTs each performing filter processing having different functions are connected in parallel. No problem.

Further, in the embodiment, a 3 × 3 two-dimensional filter is taken as an example, but the size of the filter may be larger. Further, the present invention can be applied to a three-dimensional filter (a filter that takes into account a two-dimensional spread of an image and a time axis) or a multidimensional filter that is larger than that.

Further, in the embodiment, the input image data is described as non-interlaced image data, and various synchronizing signals are superimposed thereon. However, the input image data may be in any form. The present invention is not limited by the present invention.

[0055]

As described above, according to the present invention, the image to be subjected to the logical operation processing is stored so that the logical filter processing can be performed again, and the desired area required for the filter processing in the spatial region can be obtained. Can be read out at once and filter processing can be performed.

[Brief description of the drawings]

FIG. 1 is an overall block configuration diagram of a logical filter device according to an embodiment.

FIG. 2 is a diagram for explaining the principle of storing and reading image data in the embodiment.

FIG. 3 is a circuit configuration diagram of a memory unit in FIG. 1;

FIG. 4 is another circuit configuration diagram of the memory unit in FIG. 1;

FIG. 5 is a diagram showing an application example of the filter device.

FIG. 6 is a block diagram of a conventional filter device.

Continuation of the front page (72) Inventor Akihiko Nishiide 127, 4-7 Asahigaoka, Hino-shi, Tokyo F-term (reference) 5G057 CA06 CA12 CA16 CB06 CB12 CB16 CE06 CH09 CH11

Claims (6)

[Claims] 1. A logical filter device for performing an arithmetic process on a pixel area formed by a pixel of interest and surrounding pixel data groups in input image data, the logical filter apparatus having the same address space, And when the input image data is stored in the memory group, each of the first to Nth memories of the memory group corresponds to each pixel position of the pixel area. Storing means for giving an offset and storing; supplying a common address signal to the memory group;
A logical filter device comprising: reading means for reading; and filter means for inputting a pixel data group read from the memory group by the reading means and performing a logical operation on the pixel data group. 2. The logical filter device according to claim 1, wherein said storage means binarizes the image data and stores the image data. 3. The logical filter device according to claim 1, wherein said read means reads in accordance with an address signal from a microprocessor. 4. A filter means for performing a logical operation on a pixel area composed of a pixel of interest in the image data and its surrounding pixel data group, and a filter means having the same address space and having the number N of pixels constituting the pixel area. A method of controlling a logical filter device including a memory group, wherein when the input image data is stored in the memory group, each pixel of the pixel region is provided to each of the first to Nth memories of the memory group. A storage step of giving an offset corresponding to the position and storing the same, supplying a common address signal to the memory group,
A control method for a logical filter device, comprising: a reading step of reading; and a step of supplying a pixel data group read from the memory group by the reading unit to the filter unit and performing a logical operation process. 5. The control method according to claim 4, wherein in the storing step, the image data is binarized and stored. 6. The control method according to claim 4, wherein the reading is performed in accordance with an address signal from a microprocessor.