JPS6346581A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To perform arithmetic operations among (n) picture elements in one memory cycle by using a means which receives the same address signal and performs simultaneously the reading control and the writing control of n-bit picture element data and an arithmetic circuit which performs arithmetic operations among (n) picture elements. CONSTITUTION:A semiconductor storage device 21 reads out 1-bit picture element data to buffers 28a and 28b from memory cell arrays 25a and 25b by address signals supplied to an address counter 22. These picture element data are calculated by an inter two picture element arithmetic circuit 29 and outputted. One of both arrays 25a and 25b is selected for writing the arithmetic result. Then the arithmetic operations are also possible among image data supplied via an input circuit 30 and the image data stored in both arrays 25a and 25b based on the control signals C0-C3. Thus different image data can be stored in the same address of both arrays 25a and 25b respectively. Then the picture element data on a designated address are sent in parallel to the circuit 29 and arithmetic processing is carried out in one memory cycle.

Description

[Detailed Description of the Invention] [Purpose of the Invention (Industrial Application Field) The present invention relates to a semiconductor memory device used in, for example, an image display device, and particularly relates to a semiconductor memory device having a pixel operation function. .

(Prior Art) For example, a semiconductor memory device equipped with a pixel calculation function is used in computer image terminals, digital television receivers, etc. In addition to its function as an image memory, each pixel It is also possible to perform calculations between the two. This pixel opening σ is necessary when superimposing each image data in a display device, and for example, the logical sum (OR), logical product (AND), and exclusive logical sum (EXOR) between each pixel. etc. is calculated.

However, the conventional pixel calculation function was limited to calculation between 1-bit image information in the stomach made of semiconductor memory equipped with this calculation function and 1-bit image information input from an external storage device. It was something.

A semiconductor memory device storing such a pixel calculation function is applied, for example, to a system as shown in FIG. 4, and the following calculation operation is executed to obtain one pixel calculation function.

First, the storage section 12 is read accessed by a command from the control section 11, and 1-bit pixel data corresponding to a designated address value is read from the storage section 12 to the accumulator lla of the control section 11. Next, the semiconductor memory device (hereinafter referred to as a storage unit with training function) 13 equipped with a pixel calculation function is write-accessed by the control unit 11, and the image data held in the accumulator 11a becomes 2TI.
The data is sent to the storage unit 13 with calculation function. In this memory unit 13 with arithmetic function, a computation is performed between the pixel data sent from the accumulator 11a and the pixel data in the memory unit 13 whose address is designated by the control unit 11, and the result of this computation is The address value in the functional storage device 13 is written again. For this reason, the original pixel data previously stored in the storage unit 13 with arithmetic functions will be destroyed. In addition, after one pixel-to-pixel operation, two
Since only one piece of pixel data can be processed, the above process must be repeated (number of pixel data - 1) times to perform an operation between three or more pieces of pixel data.

Then, the storage section 13 with calculation function is operated by the vin section 11.
When read access is made, the arithmetic result data stored in the arithmetic function storage section 13 is outputted to the outside. Therefore, before obtaining the result of inter-pixel operation,
A total of 3 memory cycles were required.

(Problems to be Solved by the Invention) The present invention was made in view of the above points. For example, when processing image data, it is difficult to solve the problem between a large number of pixel data. 2! The object of the present invention is to provide a semiconductor memory device that can perform data filling at a sufficiently high speed without destroying the original pixel data.

[Structure of the Invention] (Means for Solving the Problems) That is, in the semiconductor memory device according to the present invention, reading and writing of pixel data of n (n≧2) bits can be performed simultaneously upon receiving the same address signal. The device is equipped with a control means and an arithmetic circuit that performs arithmetic operations between n pixels, so that arithmetic operations between n pixels are executed within one memory cycle.

(Function) In other words, in a semiconductor memory device equipped with the above-mentioned means, it is possible to output the calculation result to the outside within the same memory cycle as the calculation processing between pixels, and the calculation speed becomes faster. At the same time, the original double-thread data stored in the memory cells can be prevented from being destroyed.

(Example) The present invention will be described in detail below with reference to the drawings. FIG. 1 shows a semiconductor memory device 21 according to the present invention, and an address counter 22 is composed of a row address counter 221 and a column address counter 222. The row address counter 221 receives the upper half of the address signal A1 supplied from the outside, while the column address counter 222 receives the lower half of the address signal A2. Furthermore, the address counter 22 is supplied with a preset signal and a clock signal, and the address signal A1,
By A2, preset signal, and clock signal,
Address counter 22 is activated.

That is, address values supplied from the outside to the address counter 22 are set in the row address counter 221 and the column address counter 222 by a preset signal, and the address values are incremented by a clock signal.

The semiconductor memory device 21 includes a plurality of memory cell arrays 25a and 25b, for example, two memory cell arrays, sense amplifiers 26a and 26b that amplify the input and output data of each of the memory cell arrays 25a and 25b, and data that transfers the input and output data, respectively. Bus 27a, 27b,
Furthermore, column decoders 24a and 24b are respectively provided to designate the column addresses of the memory cell arrays 25a and 125b, and each pair receives a row decode signal input from the row decoder 23 and a column address counter 222. They are operated in parallel depending on the column address value.

The row address counter 221 outputs each address value to the row decoder 23, and the column address counter 222 outputs each address value to the column decoders 24a and 24b. Row decoder 23 decodes the address value input from row address counter 221 and outputs a decode signal to memory cell array 25a125b.

That is, during reading, 1-bit data selected by row decoder 23 and column decoder 24a among the data stored in memory cell array 25a is sent to buffer 28a via sense amplifier 26a and data bus 27a. , At the same time, memory cell array 2
5b also sends 1-bit data to the buffer 28b via the sense amplifier 2θb and the data bus 27b.

That is, one bit of data is read from each of the memory cell arrays 25a and 25b in response to the same address signal.

The two-pixel calculation circuit 29 receives an input circuit 30 from the outside according to a 4-bit control signal CO to C3 input from the outside.
Two data are selected from among the three data of the input data inputted through the buffer 28a, the data in the buffer 28a, and the data in the buffer 28b, and an operation is performed between the two selected pixels. This two-pixel calculation is performed by the two-pixel calculation circuit 29.
By the 4-bit calculation signals FO to F3 input to the
The content of the calculation is determined. and,
The two-pixel calculation circuit 29 selects one of the three buffers 28a, 28b, and output circuit 31 according to the control signals CO to C3, and writes the calculation result therein. The output circuit 31 outputs the calculation result inputted from the two-pixel calculation circuit 29 to the outside according to the output control signal from the two-pixel calculation circuit 29.

FIG. 2 shows the contents of the control by the control signal @Go-03 described above. For example, when the control command for "b1 selection write J" is input to the two-pixel calculation circuit 29, the input circuit 30 The contents are written to the memory cell 7 array 25a via the buffer 28a. Also, rbl -F (bl,
b2) When a write command is input, the data in the buffer 28a and the buffer 28b are selected, and the operation result is sent to the memory cell array 2 via the buffer 28a.
5a.

When the "b1 selection read" command is input, the buffer? 28
Data a is outputted to the outside via the output circuit 31.

ro=F (bl, b2)! J t'J R
When 1st order ffi is input, buffer? 28a and the data in the buffer 28b are selected, and the calculation results are sent to the output circuit 3.
It is output to the outside via 1. rbl =F ('b?
, i > Write” command is input, the buffer?
28a and the data of the input circuit 30 are selected, and the calculation results are sent to the memory cell array 25a via the buffer 28a.
It is now written to .

FIG. 3 shows an example of the calculation contents determined by the above calculation signals @FO to F3, and the two-pixel calculation circuit 29 executes calculations according to the calculation signals @FO to F3. In this figure, ×1 and ×2 are the selected 2
This shows two data.

In the semiconductor memory device configured as described above, one bit of pixel data is simultaneously read out from each of the memory cell arrays 25a and 25b to the buffers 28a and 28b according to the address signal input to the address counter 22. become. The read 2-bit pixel data is then computed by the 2-pixel arithmetic circuit 29, and the computed result is output to the outside via the external circuit 31. It is also possible to select at least one of the memory cell arrays 25a, 25b and write the above calculation result into the memory cells of that array. Furthermore, the control signal C
According to O to C3, the image data input from the outside via the input circuit 30 and the memory cell 7 rays 25a, 25b
It also becomes possible to perform calculations on image data stored in the .

Therefore, two sets of memory cell arrays 25a.

25b can store different pixel data at the same address, and moreover, two pieces of pixel data at a specified address can be sent in parallel to the two-pixel arithmetic circuit 29. Arithmetic processing between pixels
It can be executed within a memory cycle.

Furthermore, since calculations between two pixels can be executed without inputting pixel data from the outside, even if the external system is configured with one data bus, the results of calculations between two pixels can be stored in the same memory cycle. The signal can be output to the outside via the output circuit 31. Therefore, the calculation results are stored in the memory cell array 25a.

Since there is no need to write data into the pixel data 25b again, it is possible to prevent the original pixel data from being destroyed. Furthermore, since the result of the calculation between two pixels can be retrieved in one memory cycle, by sequentially incrementing the address value using the address counter 22, the result of the calculation between the two pixels can be directly used to refresh the display. .

Note that in the above embodiments, the memory cell array is used.

Although we have explained the case where two sets each of sense amplifiers, data buses, column decoders, and buffers are provided to perform calculations between two pixels, memory cell arrays, sense amplifiers,
By providing nIl data buses, column decoders, and buffers, and using n pixel arithmetic circuits, it is possible to perform n pixel arithmetic operations within one memory cycle.

[Effects of the Invention] As described above, according to the present invention, it becomes possible to perform arithmetic processing between pixels at a higher speed than before, and also to export the arithmetic results to the outside within the same memory cycle as the arithmetic processing. Since it can be output, the original image data written in the memory cell array does not need to be destroyed. Further, it becomes possible to easily apply the present invention to refreshing a display and the like.

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention, FIG. FIG. 4, which is a diagram showing the calculation contents of the calculation signal input to the semiconductor storage device, is a system configuration diagram using a conventional semiconductor storage device. 21... Semiconductor storage device, 22... Address counter, 23-... Row decoder, 24a, 24b-...
Column tecoder, 25a. 25b...Memory cell array, 26a, 26b...
Sense amplifier, 27a, 27b--data bus,
28a, 28b--Buffer, 29--Two-pixel culm circuit, 3o--Input circuit, 31--Output circuit.

Claims (4)

[Claims] (1) n (n≧2) sets of memory cell arrays and read and write control means that receives the same address signal and simultaneously selects each 1-bit memory cell from each of the memory cell arrays to control reading and writing of data. and n read out by this read and write control means.
1. A semiconductor memory device comprising: an arithmetic circuit that performs arithmetic operations between each piece of data from each bit of memory cell; and an output circuit that outputs the arithmetic results obtained by the arithmetic circuit to the outside. (2) The arithmetic circuit supplies the arithmetic result to the read and write control means, and the read and write control means selects at least one of the n sets of memory cell arrays, and the memory of the selected array. 2. A semiconductor memory device according to claim 1, wherein said calculation result is written into a cell. (3) n (n≧2) sets of memory cell arrays, and read and write control means that receives the same address signal and simultaneously selects each 1-bit memory cell from each of the memory cell arrays to control reading and writing of data. and n read out by this read and write control means.
An arithmetic circuit that performs arithmetic operations between data from each bit memory cell and one bit of data input from the outside, totaling n+1 bits, and outputs the arithmetic results obtained by this arithmetic circuit to the outside. A semiconductor memory device characterized by comprising an output circuit. (4) The arithmetic circuit supplies the arithmetic result to the read and write control means, and the read and write control means selects at least one of the n sets of memory cell arrays, and the memory of the selected array. 4. The semiconductor memory device according to claim 3, wherein said operation result is written into a cell.