JPH0727557B2 - Data transfer device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to image data stored in a transfer destination memory and transfer source data in a bit unit of a bit length equal to or shorter than a bit length capable of accessing the memory once. The present invention relates to a data transfer device which performs a calculation at high speed and writes a result in a memory at high speed.

2. Description of the Related Art As a conventional data transfer device, for example, Japanese Patent Laid-Open No. 61-9766
It is shown in the publication.

FIG. 4 is a block diagram of this conventional data transfer apparatus, in which 1 is a data register DBR storing transfer source data, 2 is an address register holding a word address of a transfer destination, and 4 is the above data. A memory to which the contents of the register 1 are to be transferred, 6 and 7 are gates opened by the gate signals WT and RD, 8 is an arithmetic unit having a general-purpose register, 9 is a latch circuit for storing transfer destination data, and 10 is the above data An arithmetic unit for performing an operation on a bit designated by a mask register described later between the register 1 and the latch circuit 9, 11 is a bit pointer BP indicating a bit position of a transfer destination address, 12 is a count-up signal INC, a counter-down signal DEC 1 is an adder / subtractor for the bit address connecting the address register 2 and the bit pointer BP, and 13 is a mask register MASK for designating the operation valid bit of the arithmetic unit 10, 14 Is a decoder for decoding the contents of the bit pointer 11, 15 is a mask selection signal MSEL
Selection circuit that outputs either the contents of the mask register 13 or the output of the decoder 14 to the calculator 10 as calculation valid bit specification data, 16 is a calculation mode register RORR that specifies the calculation of the calculator 10, and 17 is a calculation specification selection A selection circuit that outputs either the operation mode register 16 or direct designation from the control unit to the arithmetic unit as the operation mode designation signal by the signal RSEL, and 18 is a control unit that supplies a control signal to each block.

In the conventional data transfer apparatus configured as described above, the transfer source data is aligned with the transfer destination position in the arithmetic unit 8 and stored in the data register 1, and the word address of the transfer destination is stored in the address register 2. The bit position in the word is stored in the bit pointer 11. The contents of the memory indicated by the address register 2 are held in the latch circuit 9. The output of the data register 1 and the output of the latch circuit 9 are used as inputs, and the arithmetic unit 10 calculates in the arithmetic mode in the arithmetic mode register 16. When operated by the arithmetic unit 10, the effective bit of the operation specified by the contents of the mask register 13 outputs the above operation result, and outputs the output of the latch circuit as it is except the effective bit.

Problems to be Solved by the Invention However, in the above-mentioned configuration, in the case of transferring character font data, for example, when transferring not only the character pattern but also the character background (opaque), It was necessary to perform data transfer and character pattern data transfer twice. Further, there is a problem in that it is impossible to save (transparent) the data of the transfer destination except for the character pattern in the case of colorization.

In view of the above point, the present invention has an object to provide a data transfer device that realizes transfer of background data and transparency in the case of colorization in one data transfer.

Means for Solving the Problems The present invention relates to a register for holding transfer data, a latch circuit for holding transfer destination data, an arithmetic unit for inputting respective outputs to perform an operation, and a specific pixel in the transfer data. A flip-flop that indicates whether or not to save the transfer destination pixel, a detection circuit that detects a specific pixel from the data output from the above register, a mask register that holds the operation effective bit information of the above operation unit, and data transfer The data transfer apparatus includes an address register that stores a destination address.

With the above-described structure, the present invention calculates the transfer source data and the transfer destination data and stores the result in the transfer destination memory when the pixel is the effective bit indicated by the mask register and does not hold the transfer destination data in the opaque mode. In cases other than the above, the transfer destination data is stored as it is. By this operation, in the opaque mode for the valid bit indicated by the mask register,
In the transparent mode, the transfer destination data is rewritten, and in the transparent mode, the transfer destination data indicated by the transfer source data is calculated only at the pixel positions that are not saved and the result is stored in the transfer destination, and the other pixels retain the original data. It

First Embodiment FIG. 1 shows a block diagram in the first embodiment of the present invention, which deals with a binary image. In FIG. 1, 1 to 18 have the same structure as the conventional example of FIG. Reference numeral 19 denotes a flip-flop that indicates whether or not to store a transfer destination pixel for a pixel of specific data in the transfer data during data transfer.
Is a background color register, 21 is the data held by the data register 1, and detects the background color indicated by the background color register 22.
ENOR circuit, 20 is the output of flip-flop 19 and ENOR circuit 21
The gate that outputs the mask register 13 that receives the output of the above as the input and uses the NAND output as the gate signal indicates the operation valid bit of the calculator 10.

The operation of the data transfer device of the present embodiment having the above-described configuration will be described below.

The transfer source data is aligned with the transfer destination position by the arithmetic unit 8 and stored in the data register 1, and the transfer destination address is stored in the address register 2. Address register 2
The contents of the transfer destination memory indicated by are held in the latch circuit 9.
The outputs of the data register 1 and the latch circuit 9 are input to the arithmetic unit 10, respectively. The arithmetic mode of the arithmetic unit 10 is designated by the arithmetic mode register 16. Then transparent, opaque mode,
The mask register will be described with reference to FIG.

The logic 1 of the mask register 13 indicates the operation valid bit position of the arithmetic unit 10, and the logic 0 stores the data of the transfer destination as it is. When the flip-flop 19 is logic 1, it is called a transparent mode, and the background color indicated by the background color register 22 is "B". The bit of the transfer destination data corresponding to the bit position where the content of the data register 1 is "B" is saved. For this reason, the operation valid bit input to the arithmetic unit 10 is used to output the output of the latch circuit as it is at the above bit position. At the bit position where the content of the data register 1 is "F", the operation designated by the operation mode register 16 is executed between the transfer source data and the transfer destination data, and the result is stored in the corresponding transfer destination bit. When the flip-flop 19 has a logic 0, it is called an opaque mode, and an operation is performed between the contents of the data register 1 and the transfer destination data and the result is stored in the transfer destination memory. In this case, the operation is performed with the transfer destination data regardless of the contents of the data in the data register 1.

While the successive adjacent addresses are being transferred to the memory, the address of the address register 2 is updated by adding 1 or subtracting 1 using the adder / subtractor 12 each time data transfer is completed.

As described above, according to this embodiment, by using the ENOR circuit 21 as the background data detection circuit, it is possible to easily realize the transparent and opaque modes of the binary image.

FIG. 3 is a block diagram of a data transfer device showing a second embodiment of the present invention. In Figure 3, from 1 to 21,
The configuration is the same as that of FIG. The difference from the configuration of FIG. 1 is that for colorization, a memory 4, a selection circuit 6, 7, a data register 1, a latch circuit 9, an arithmetic unit 10, a gate 20, an ENOR circuit 21,
This is that the background register 22 is provided for a plurality of bits in order to represent each pixel by a plurality of bits.

The operation of the data transfer apparatus of the second embodiment configured as described above will be described below.

The transfer source data is aligned with the transfer destination position by the arithmetic unit 8 and stored in the data register 1 for each color plane. The data transfer destination address is stored in the address register 2, and the content of the address indicated by the address register 2 is held in the read latch circuit 9 for each memory plane. Data register 1
The data for each memory plane and the data for each memory plane of the latch circuit are input to the arithmetic unit 10 corresponding to each plane. The arithmetic mode of each arithmetic unit 10 is designated by the arithmetic mode register 16. Mask register 13
The logic 1 indicates the operation valid bit position of the arithmetic unit 10, and the logic 0 stores the transfer destination data as it is. When the flip-flop 19 has the logic 1, the pixel of the transfer destination data corresponding to the bit position where the pixel indicated by each memory plane of the data register 1 matches the color indicated by the background color register 22 is stored. For this reason, the calculation of the bit position is output to the operation valid bit input to the arithmetic unit 10 as it is from the output of the latch circuit. Except for the above bit positions of the data register, the calculation of the transfer source data and the transfer destination data is performed for each memory plane, and the result is stored in the transfer destination bit of the corresponding memory plane. When the flip-flop 19 is a logical 0, the arithmetic operation is performed for each memory plane of the data register 1 and the latch circuit 9, and the result is stored in each memory plane of the transfer destination memory.

While the successive adjacent addresses are being transferred to the memory, the address of the address register 2 is updated by adding 1 or subtracting 1 using the adder / subtractor 12 each time data transfer is completed.

As described above, according to the present embodiment, by having a plurality of memories, data registers, latch circuits, arithmetic units, and background color data detection circuits, it is possible to realize transparent and opaque data transfer of color images.

EFFECTS OF THE INVENTION As described above, according to the present invention, transparent and opaque data transfer can be realized by one-time data transfer, and the same can be extended to a color image. large.

[Brief description of drawings]

FIG. 1 is a block diagram of a data transfer device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of processing of the same embodiment, and FIG. 3 is a block diagram of a data transfer device according to another embodiment of the present invention. FIG. 4 is a block diagram of a conventional data transfer device. 1 ... Data register, 2 ... Address register, 4 ...
... Memory, 6,7 ... Gate, 8 ... Calculator, 9 ... Latch circuit, 10 ... Calculator, 11 ... Bit pointer, 12 ...
1 adder / subtractor, 13 ... Mask register, 14 ... Decoder,
15,17 ... Selection circuit, 16 ... Calculation mode register, 18 ...
Control block, 19 Flip-flop, 20 Gate, 21 ENOR circuit, 22 Background color register.

Claims (1)

[Claims] 1. A first register for holding transfer data,
An address register that holds the transfer destination address that stores the data, a latch circuit that holds the contents of the memory indicated by the address register, an output of the first register as a first input, and an output of the latch circuit A second input, an arithmetic unit that performs a desired arithmetic operation between input data, a control unit that generates the type of arithmetic operation of the arithmetic unit, a mask register that holds arithmetic effective bit information of the arithmetic unit, and transfer data A flip-flop that indicates whether or not to save a transfer destination pixel for a pixel of specific data, a detection circuit that detects specific data from the data output from the first register, an output of the flip-flop, and The NAND output of the detection circuit and the output of the mask register are logically ANDed, and for the bit for which the logic 1 is designated, For a bit for which a desired operation result is output between the data of the latch circuit and logic 0 is designated,
A data transfer device characterized by transferring the output of an arithmetic unit which outputs the output of a latch circuit as it is.