JPS60173585A - Display control system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Section] The present invention relates to a display control method in a CRT, LCD, or other data display device that is configured using a bitmap method and has an attribute display function, and particularly relates to a display control method for a data display device such as a CRT or LCD that is configured using a bitmap method and has an attribute display function. The present invention also relates to a display control method that enables attribute-based processing using a small-capacity attribute memory by performing attribute processing on display data.

Traditionally, CR'r display devices configured with a bitmap method and equipped with an attribute display function use a large-capacity attribute memory corresponding to the bits of the bitmap memory, and the information written to this attribute memory is A display control method is used to control the attributes of data when displaying the data using attribute data.

More specifically, when data is sent from the bitmap memory to the data display device, attribute processing is performed based on information in the attribute memory.

Therefore, a large capacity attribute memory corresponding to the bitmap frame memory for display is required, and the display data transmission circuit is required to perform high-speed attribute processing, resulting in many inconveniences such as increased costs. was there.

Therefore, the two-display control method of the present invention solves these inconveniences in conventional monitor display devices such as CART that have an attribute display function, and uses a large-capacity attribute memory corresponding to the bits of the bitmap memory. The purpose of this invention is to eliminate the need for attribute processing and to enable attribute processing to be performed using a small-capacity attribute memory.

Kazu-Issei.

For this purpose, in the display control method of the present invention, a CRT configured using a bitmap method and having an attribute display function is used.
In a data display device such as the above, an attribute memory stores coded attribute information, and an attribute processing means provided in a data input section of the bitmap memory and performs attribute processing of data according to attribute information from the attribute memory. The data output from the attribute processing means is written into the bitmap memory.

Next, an embodiment of the display control method of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a functional block diagram showing an example of a CRT display device used when implementing the display control method of the present invention. In the drawing, 1 is a display data memory that stores display data, 2 is an attribute memory that stores attribute information, and 3 is a display data memory that stores display data.
4 is an attribute conversion circuit, 4 is an address generation circuit, 5 is a display timing control signal generation circuit, 6 is a bitmap memory, and 7 is an attribute conversion circuit.
is P/S (parallel → serial) conversion circuit, 8 is CRT
Shows the display unit.

The display data memory 1 is provided in a data processing section, which is not particularly shown in detail, and temporarily stores display data information. Further, an attribute memory 2 is also provided in the data processing section in the same way, and encoded attribute information is temporarily stored therein.

The attribute conversion circuit 3 is an attribute processing means that processes and converts the display data stored in the display data memory 1 using the attribute information stored in the attribute memory 2 when writing the display data to the bitmap memory 6.

Address generation circuit 4 generates an address signal for bitmap memory 6.

The display timing control signal generation circuit 5 generates control signals for controlling the display timing on the CRT display unit 8 and the reading/writing of the bitmap memory 6 according to the input control signal.

The bitmap memory 6 has a frame memory corresponding to the screen of the CRT display unit 8.

The P/S conversion circuit 7 converts the pattern data read from the bitmap memory 6 from parallel data to serial data and outputs the data to the CRT display unit 88.

The CRT display unit 8 displays pattern data based on display data processed and converted according to the attribute information in a visible pattern.

The following FIG. 2 is a functional block diagram showing a detailed configuration example of the attribute conversion circuit 3 and its surroundings for the CRT display device shown in FIG. 1. Reference numerals in the drawing are the same as those in FIG.
D indicates a thinning logic section, DATA indicates display data before attribute processing, and DATA' indicates display data after attribute processing.

FIG. 2 shows the detailed structure of related parts of the display data memory 1, attribute memory 2, attribute conversion circuit 3, and 4-bit map memory 6 shown in FIG.

Furthermore, in the circuit shown in FIG. 2, the attribute information stored in the attribute memory 2 has a 4-bit configuration, and for example, the first bit is enlarged, the second bit is reduced, the third bit is inverted, and the fourth bit is is the information that instructs each attribute of thinning, making it possible to specify four types of attributes in total.

Of the four bits of this attribute information, each attribute is designated by the position of one or more bits given by "1".

In response to such attribute information, the attribute conversion circuit 3 has the following information:
Attribute conversion logic units 3A to 3D are provided respectively.

That is, when the attribute information instructs enlargement, the enlargement logic section 3A is selected. Similarly, the reduction logic section 3B is selected for reduction, the inversion logic section 3C is selected for inversion, and the thinning logic section 3D is selected for thinning.

Note that the inverted gate circuit used in this attribute conversion circuit 3 can be constructed of, for example, a Nant gate circuit. Similarly, for example, the expansion/reduction logic can be configured by controlling the connection positions of input data lines and output data lines, and the thinning logic can be configured by controlling the number of connections.

Is the display data DATA Do-D? This is a case of an 8-bit configuration, which is input from the display data memory 1 to the attribute conversion circuit 3, and is processed and converted by each logic section 3A to 3D selected according to the attribute information. The changed display data is stored in the bitmap memory 6 as data DATA'.
sent to.

Next, the operation of the display control system of the present invention will be explained using the CRT display device shown in FIGS. 1 and 2.

In the case of FIG. 2, the display data DA
This shows a case where TA is inverted.

First, under control from a data processing unit (not shown),
From the display data memory 1 of the data processing section, for example, ro
Display data DATA such as olllooJ is input to the attribute conversion circuit 3.

On the other hand, in the attribute conversion circuit 3, the inversion logic section 3C is enabled by the attribute information ro O10J indicating the attribute for inverting the display data DATA, and the input display data DATA is inverted by the Nantes gate circuit, and rl 1000011J Convert to data DATA'.

Next, the inverted data D processed by the attribute conversion circuit 3
ATA' is written to a specified address in the bitmap memory 6 by the address generation circuit 4 and the display timing control signal generation circuit 5.

By such an operation, attribute processing is performed to invert the display data, and data subjected to attribute processing according to the attribute information is written into the bitmap memory 6.

When displaying the data in the bitmap memory 6 on a CRT screen, the P/S conversion circuit 7 loads the display data from the bitmap memory 6 using the timing clock from the address generation circuit 4, and outputs the display timing control signal. Generating circuits 5 to 7 shift out bits one by one using the supplied shift clocks and send them to the CRT display unit 8.

The operation when other attribute information is given is also similar to this inverted attribute processing.

As explained in detail above, in the display/control method of the present invention, in a data display device such as a CRT that is configured using a bitmap method and has an attribute display function, an attribute memory that stores coded attribute information and a bit Attribute processing means is provided in the data input section of the map memory and performs attribute processing on data according to attribute information from the attribute memory, and data output from the attribute processing means is written to the bitmap memory. There is.

As described above, according to the display control method of the present invention, attribute processing is performed using coded attribute information when writing to the bitmap memory, so attribute processing is performed using a small-capacity attribute memory. This makes it possible to eliminate the need to use a large capacity attribute memory corresponding to the bits of the bitmap memory.

=8= In addition, there is no need for high-speed attribute processing required in conventional bitmap type CRT display devices, etc., and the circuit configuration used for this is relatively simple, so it is advantageous in terms of cost. Many excellent effects can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a functional block diagram showing an example of a CRT display device used when implementing the display control method of the present invention, and FIG. 2 is a functional block diagram showing an attribute conversion circuit 3 of the CRT display device shown in FIG. FIG. 2 is a functional block diagram showing a detailed example of the peripheral configuration thereof. In the drawing, 1 is a display data memory, 2 is an attribute memory, 3 is an attribute conversion circuit, and 3A is its expansion logic section.
3B is a reduction logic section, 3C is an inversion logic section, 3D is a thinning logic section, 4 is an address generation circuit, 5 is a display timing control signal generation circuit, 6 is a bitmap memory,
7 is a P/S conversion circuit, and 8 is a CRT display unit. Patent applicant: Ricoh Co., Ltd. − Patent attorney: Toshitaka Kankawa

Claims (1)

[Claims] In a CRT or other data display device that is configured using a bitmap method and has an attribute display function, there is an attribute memory that stores coded attribute information, and a data input section of the bitmap memory that stores information from the attribute memory. genus of,
1. A display control system comprising: attribute processing means for performing attribute processing of data according to gender information; and writing data output from the attribute processing means into a pit map memory.