JPS6352195A - Display control system - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to display control technology, and relates to a technology that is effective when applied to, for example, superimposed display of character display and graphic display on an LCD (liquid crystal display).

[Prior Art] There are cases where it is desired to display characters such as letters and codes in a superimposed manner on the screen of an LCD display device.

Conventionally, for example, the liquid crystal controller L manufactured by Suwa Seikosha Co., Ltd.
In order to perform overlapping display in a graphic system using SI 5ED1330, a large-capacity memory is installed outside the display controller to hold composite data obtained by taking the logical OR of character display data and graphic display data. After writing overlapping display data of characters and graphics in a one-to-one correspondence, this was displayed on the display screen.

[Problems to be Solved by the Invention] The overlapping display method described above requires a large capacity memory outside the display controller to store the composite data in order to realize the overlapping display, which increases the cost. There was a problem with putting it away.

An object of the present invention is to enable overlapping display to be realized in a graphic display system without providing a large capacity memory.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, one of the character display data associated with the same pixel on the LCD device screen is stored inside the display control device that reads display data from the display data memory.
The number of OR gates into which one bit of the bit and the graphic display data are respectively input is provided in a number corresponding to the bits constituting the display data. Also, by supplying the raster address to the graphic code RAM,
This allows a linearly increasing address signal to be supplied to the graphic code RAM.

[Operation] According to the above means, the same raster address as the raster address supplied to the character generator ROM is supplied to the graphic code RAM, and the logical sum of the data read from the graphic code RAM and the data read from the character generator ROM is performed. can be used as superimposed display data, so that the above objective of realizing superimposed display without providing a large capacity memory outside the liquid crystal display controller for storing the composite data can be achieved. Can be done.

[Embodiment] FIG. 1 is a block diagram showing an example of the case where the present invention is applied to an LCD display controller.

In FIG. 1, an MPU (Micro
The processing unit (Processing unit) supplies address signals for writing via address bus AB to character code RAM 3 and graphic code RAM 5 via multiplexers 7 and 8, and also supplies write data via data bus DB.

The timing controller is designated by numeral 2.

For example, as shown in FIG. 2, eight OR gates G to G are provided inside, and the graphic code R
8-bit configuration data MD read from AM5, ~
MD, are gates G1 to G, respectively.

8-bit data MD supplied to one input terminal of the character generator ROM 4 and read from the character generator ROM 4;
~MD, , are supplied to the other input terminals of gates 01 to G8, respectively, and the superimposed data is sent to the power supply circuit and drive IC1.
LC as an LCD display device with an integrated liquid crystal panel
Output to D module 6.

The timing controller 2 has a function to set a mode for each display, and can be set in three display modes: graphic display mode, character display mode, and superimposed display mode of graphic display and character display (hereinafter simply referred to as superimposed display mode). The system has been made operational.

Although not particularly limited, for example, the timing controller 2 is provided with a G/C terminal and an AT terminal as mode setting terminals, and when the G/C terminal is set to a high level, a graphic display mode is set, and the G/C terminal is set to a high level. When the /C terminal is set to low level and the AT terminal is set to high level, the character display mode is set, and when both the G/C terminal and the AT terminal are set to low level, the superimposed display mode is set. ing.

In addition, the timing controller 2 sends address signals MA, ~MAY, and raster address signals RA, ~RA4 for reading display data of the character code RAM 3 and graphic code RAM M5 to the character code RAM 3 and graphic code RAM 5 through multiplexers 7.8, respectively. It is supplied to RAM3 and graphic code RAM5.

Display data to be displayed on the display screen on the LCD module 6 is stored in the character code RAM 3. This display data is read using a 16-bit address signal M supplied from the timing controller 2.
It is performed based on A, ~MA□.

The character generator ROM 4 stores pattern information for generating an image signal (for example, a character pattern consisting of 8 dots vertically and 8 dots horizontally) corresponding to the character code read from the character code RAM 3. One raster worth of data designated by raster address signals RA, -RA4 supplied from the timing controller 2 is sequentially read out in parallel.

The graphic code RAM 5 has an LCD module 6.
Graphic display data to be displayed on the upper display screen is stored, and the data is read out based on an address signal supplied from the timing controller 2.

An example of overlapping display of graphics and characters will be described below.

When the G/C terminal and AT terminal of the timing controller 2 are set to low level, the superimposed display mode is set.The display pattern to be displayed on the display screen is read out from the timing controller 2. Address signal MA for reading character code, ~
MA, is supplied to the character code RAM3. As a result, the display data in the character code RAM 3 is read out, and based on this, the character generator R
The character pattern displayed on the display screen is read from the OM4, and the raster address signal R of the character pattern is read out from the OM4.
Raster data MD specified by A, ~RA,
-MD, , are supplied to one input terminal of each of OR gates 01-G shown in FIG. At the same time, the graphic code RAM 5 receives address signals MA, ~M supplied from the timing codon roller 2.
A, and graphic display data MD, ~MD, based on raster address signals RA0~RA, are connected to OR gate G.
1 to G, respectively, are supplied to the other input terminals.

The display screen of this embodiment is, for example, as shown in FIG.
It is possible to display a pattern of 32 horizontal characters x 8 dots and 24 vertical lines x 8 rasks, that is, 768 character patterns. Therefore, in order to prepare an address that can correspond to this display screen in the graphic code RAM 5, the address signal has a 13-bit configuration. However, the addresses required to read the character code RAM are 10 bits (MA, ~MA,), and the first rask of the 32-character pattern is displayed at addresses O to 31 on the display screen, and then the first rask is displayed again. If you want to return to the first (0th) character pattern and display its second rask, the address supplied to the character code RAM is supplied as is to the graphic code RAM 5 and read out, as shown in Figure 3. The graphic display data corresponding to the 32nd address cannot be read out, resulting in an undesirable display problem. Therefore, the graphic code RA
M5 has 9 character pattern reading addresses MA, ~M
The graphic code RA increases linearly using A.
In order to generate an address for M, a 3-bit raster address signal RA, ~RA2 is inserted between the 5th bit MA and the 6th bit MA of addresses MA, ~MA, as shown in FIG. Graphic code RA in the form
It is arranged to be supplied to M5.

Note that the positions at which the raster addresses RA, ~RA, are inserted may be changed depending on the width of the display screen. As a result, the 8-bit superimposed data is output from the gates G to G to the LCD module 6, and the superposed data is displayed on the display screen.

By the way, if you only want to display the character, press G
/C terminal at low level and timing controller 2
Set the G/C data bit of the internal mode register to low level. With the above settings, the character display data MD, -MDls input to the gates G□ to G, are output as they are from the gates G, -G, and are displayed on the display screen on the LCD module 6.

On the other hand, if you only want to display graphics,
The C terminal is set to high level or the G/C data bit of the mode register inside the timing controller 2 is set to high level. As a result, the character display data MD, ~MD, input to the gates Gi~G, are all set to low level, and the graphic display data MD, ~MD are input to the gates Gi~G.
MD is output as it is from the gates G1 to G, and is displayed on the display screen on the LCD module 6.

In the above embodiment, one bit of the character display data and one bit of the graphic display data that are associated with the same pixel on the screen of the LCD device are stored in the display control device that reads display data from the display data memory. The number of OR gates into which are respectively input are provided in a number corresponding to the bits constituting the display data. Also,
By supplying a raster address to the graphic code RAM, a linearly increasing address signal can be supplied to the graphic code RAM, so that the raster address is the same as the raster address supplied to the character generator ROM. When a raster address is supplied, the data read from the graphic code RAM and the data read from the character generator ROM are logically summed, and this can be used as superimposed display data. It is possible to obtain the effect that overlapping display can be performed without providing a large-capacity memory outside the liquid crystal display controller.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Mona%N.

In other words, in the above embodiment, since one rask of one display pattern is composed of 8 bits, the number of gates in the timing controller is 8, but the number of gates may vary depending on the number of bits composing the display pattern. The number of gates can be increased or decreased.

In the above explanation, the invention made by the present inventor was mainly applied to the field of application in which the invention is based, which is the superimposed display of character display and graphic display on LCD, but the present invention is not limited to this. Applicable to image control systems in general.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, characters and graphics can be displayed in an overlapping manner without providing a memory for overlapping display outside the LCD display controller.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of the case where the present invention is applied to an LCD display controller, Fig. 2 is an explanatory diagram of gates provided inside the timing controller, and Fig. 3 is an explanation showing the configuration of the display screen. FIG. 4 is an explanatory diagram showing an example of connection of address signal lines to the graphic code RAM 5. 1...MPU, 2...timing controller, 3...character code RAM, 4...character generator ROM, 5...graphic code RAM, 6...LCD module, 7゜8...
...Multiplexer, G~G, ...OR gate. Figure 3 Figure 4

Claims (1)

[Claims] 1. A display device and a character code memory that stores display data displayed on the display screen in the form of a code;
A character generator memory that generates a display pattern corresponding to the code read from the character code memory, a graphics memory that stores graphic display data, and a display screen of the character display data and the graphic display data. A display control device includes a display data synthesis circuit that performs a logical sum of respective data associated with the same pixel of the above and outputs the result, reads out display data from each of the memories, synthesizes it, and supplies it to a display device. A display control system comprising: 2. When performing a composite display of the character display data and graphic display data, the address signal supplied to the character code memory and the raster address supplied to the character generator memory are appropriately supplied to the graphic memory. 2. The display control system according to claim 1, wherein graphic display data is read out.