JPS61235891A - Display control system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to display control technology, and relates to a technology that is effective when used in a liquid crystal display controller driver that controls and drives, for example, a dot matrix type liquid crystal display device.

[Background Art] As an LSI (Large Scale Integrated Circuit) liquid crystal display controller driver (hereinafter referred to as liquid crystal controller) that controls and drives a dot matrix type liquid crystal display device,
For example, a display data RAM (random access memory) that stores display data as codes internally, and a character generator ROM (read memory) that forms display patterns based on codes read from the display data RAM. -Only memory), and the parallel data read from this character generator ROM is converted into serial data and sent to the liquid crystal drive circuit to be displayed on the display panel of the liquid crystal display device. (Hitachi MO3LSI Data Book LCD Driver LS published by Hitachi, Ltd. in March 1982)
IJ, pages 52-85).

However, conventional LCD controllers display characters with black dots on a white background, and in order to display black and white inverted characters (white dots on a black background), complicated external circuits are required. There was an inconvenience that it was necessary.

[Object of the Invention] The object of the invention is to provide a display that can easily and freely display black and white inverted characters without changing the display data stored in the display data memory by adding simple hardware. Our goal is to provide control technology.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

That is, a RAM in which display data is stored as a code.
For example, for each character code, an additional bit is provided to specify whether it is a normal character or an inverted character, and when driving the display, this additional bit is read out along with the character code, and the character generator ROM is read using that and the above character code. By calculating the exclusive OR with the read signal, black and white inverted characters can be easily and freely added without changing the display data stored in the display data RAM by adding simple hardware. This achieves the above purpose of making it possible to display images.

The present invention will be specifically explained below using the drawings.

[Embodiment] FIG. 1 shows an embodiment in which the present invention is applied to a liquid crystal controller LSI.

Although not particularly limited, each circuit block surrounded by a chain line A in the figure is formed on one semiconductor chip such as a single crystal silicon substrate.

A power supply voltage Vcc and a ground potential GND are applied to the internal circuit from the outside to the semiconductor chip A, and an oscillation signal ○SC1,0 for forming an internal clock signal is applied.
5C2 and liquid crystal display driving power supplies v1 to v5 are supplied.

In FIG. 1, the circuit designated by IR is an instruction register that holds instructions supplied from an external microprocessor to a liquid crystal controller via an input/output buffer IOB. The instruction held in the instruction register IR is decoded by the instruction decoder ID and is
, 11 display shift'', ``display clear'', and other internal control signals corresponding to various commands.

What is indicated by the circuit symbol AC is an address counter to which an address indicating a write position is set when data is written. This address counter AC includes instruction register IR and instruction register IR.
The instruction and the set write address are set via the decoder ID.

The circuit code DR is the human output buffer IO.
This is a data register that holds write data etc. supplied from the microprocessor via B. The data held in this data register DR is transferred to the internal bus BUS.
The data can be supplied to a display data RAM and a character generator RAM, which will be described later.

In this embodiment, although not particularly limited, the instruction code and write data supplied from the microprocessor via the common data input/output terminals DB, ~DB3, and DB4~DB7 are input to the instruction register IR and the data register. Selectively loaded into DR. To switch the data, a switching signal R3 is supplied from the microprocessor to the liquid crystal controller. By this switching signal R3, the data input/output terminal DB
o DB3. Signals input to DB4 to DB are taken into a desired register (IR or DR).

What is indicated by the circuit symbol DD-RAM is a display data RAM that can be read and written at any time and stores display data displayed on a display panel of a liquid crystal display device (not shown). This display data RAM (DD-RAM) is, for example, 8
It has a capacity to store 80 characters represented by bit codes. Moreover, in this embodiment, an additional bit string BIT consisting of 80 bits is stored in the display data RAM in correspondence with the number of characters that can be stored, "80".
(DD-RAM), and when each 8-bit character code is read out, the information of one corresponding bit in this additional bit string BIT is read out at the same time.

However, writing to the additional bit string BIT is as follows:
Writing of the character code is performed via an internal bus BUS using a separate command.

What is indicated by the circuit code ROM is the above display data R.
This is a read-only character generator ROM in which pattern information for generating a signal (character pattern) corresponding to a character code read from AM (DD-RAM) is stored. Although not particularly limited, in this embodiment, in addition to the character generator ROM, a character generator RAM (CG-RAM) is provided in which the user can set and freely register arbitrary patterns.

The above character generator ROM (CG-ROM
) and character generator RAM (CG-RA
M) is the character code and timing generation circuit TG read out from the display data RAM (DD-RAM).
It is accessed by an address decoder AD which generates a selection signal by decoding a column signal synchronized with a common signal (signal applied to the common electrode of the display panel) supplied from the address decoder AD.

In this embodiment, this character generator RAM
Exclusive logic between the output signals of CG-ROM and CG-RAM (hereinafter collectively referred to as character generator memory) and the signal read from the additional bit string BIT of the display data RAM (DD-RAM) Exclusive OR gates Gl and G2 for calculating the sum are provided, and their outputs are supplied to the parallel-to-serial conversion circuit PSC.

In the drawing, one exclusive OR gate G1 and one G2 are shown, but in reality, the number of exclusive OR gates G1 and G2 corresponds to the number of bits of data read out in parallel from each character generator memory CG-ROM and CG-RAM. Only a few can be provided. The character pattern data read out in parallel from the character generator memory CG-ROM or CG-RAM is converted into serial data in the parallel-to-serial converter circuit PSC, and is converted into serial data by the shift register SR.
, is supplied to

When the shift register SR1 accumulates, for example, 40 bits of data supplied from the parallel-to-serial conversion circuit PSC, it sends them all together to a latch circuit LTC having a 40-bit configuration. Based on the data held in the latch circuit LTC, the segment signal driver SSD drives the segment electrodes of the liquid crystal display panel with segment signals SEG, ~5EG4
0 is formed and output to the outside of the chip.

The circuit code TG indicates a timing generation circuit, and this timing generation circuit TG generates column signals supplied to the address decoder AD based on oscillation signals 08C1 and ○SC2 supplied from external terminals. It also forms internal clock signals for the aforementioned instruction register IR and other circuit blocks. Furthermore, the timing generation circuit TG performs synchronization with the liquid crystal driver LSI etc. externally attached to the liquid crystal controller of this embodiment.
Signals CL, CL2. Form M and output.

Furthermore, in this embodiment, the timing generation circuit TG
A 16-bit shift register, SR2, which is shifted by a clock signal output from A common signal driver CSD is provided that outputs common signals C0M1 to COM, .

In addition, in this embodiment, a cursor (underline for - characters) is placed at the data writing position on the liquid crystal panel based on the address set in the address counter AC.
A cursor blink control circuit CBC is also provided for displaying the characters indicated by the address counter AC in a blinking manner.

Note that the circuit code FLG is a busy flag that indicates the internal status of the liquid crystal controller LSI.By checking this busy flag FLG, the microprocessor can control the liquid crystal display, which operates at a slower speed than the microprocessor. The internal state of the controller can be known and successive accesses to the liquid crystal controller can be made to wait.

The contents of the busy flag FLG are the data input/output terminal D.
B o '= One of D B (for example, DB7)
It is possible to output to the outside from. A signal E supplied from the microprocessor to the liquid crystal controller is an operation activation signal for the liquid crystal controller.

In the liquid crystal controller of the above embodiment, if there is a character that you want to display in reverse black and white, it is necessary to write "1" in advance to the additional bit corresponding to the address containing the code of that character to perform the reverse display. “
Write 0".

By doing this, when display driving, display data RA
M (DD-RAM), along with the character code, the black and white inversion information of the corresponding additional bit is simultaneously read out, and the exclusive OR gate G1. Supplied to G2. A part of the character pattern read from the character generator memory CG-ROM or CG-RAM according to the character code (data for -Rask),
The exclusive OR with the black and white inversion information is calculated and sent to the parallel-to-serial conversion circuit PSC.

Therefore, if "0" is written in the additional bit in advance, the character pattern data read from the character generator memory CG-ROM or CG-RAM is sent as is to the parallel-to-serial conversion circuit PSC. As a result, characters (or symbols) in the same manner as before are displayed at the corresponding positions on the display screen, as shown in FIG. 2(A).

On the other hand, if '1' is written in the additional bit in advance,
Character pattern data read from the character generator memory CG-ROM or CG-RAM is inverted by the exclusive OR gate G1 or G2 and sent to the parallel-to-serial conversion circuit PSC. the result,
At the corresponding position on the display screen, as shown in Figure 2 (B), black and white inverted characters (or symbols) of the characters in Figure 2 (A) are displayed.
is displayed.

In the above embodiment, the character generator RAM (
Although the present invention has been described for a controller equipped with a CG-RAM (CG-RAM), it goes without saying that the present invention can also be applied to a liquid crystal controller that does not have such a RAM.

Further, in the above embodiment, the liquid crystal controller LSI has a built-in display data RAM (DD-RAM), a character/two-way generator ROM, etc., but the present invention is not limited thereto; The present invention can also be applied to the case where a system is configured by externally attaching a data RAM or a character generator ROM to the controller LS.

[Effect] For example, an additional bit is provided in the RAM where display data is stored to specify whether it is a normal character or an inverted character for each character code, and when driving the display, this additional bit is read out along with the character code, Since the exclusive OR of that signal and the signal read from the character generator memory using the above character code is performed, if tz 1 ## is written in the additional bit in advance, the character
By automatically inverting the character pattern data read from the generator memory and outputting it, the RA for display data can be created with a simple hardware change.
This has the effect that black and white inverted characters can be easily and freely displayed without changing the display data stored in M.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above Examples, and it should be noted that various changes can be made without departing from the gist of the invention. Not even. For example, in the above embodiment, an example has been described in which the black and white of normal characters are inverted, but the present invention is not limited to this, and if the display data includes color information, additional bits may be inverted to other colors. Alternatively, it is also possible to use it as information for changing the font color or background color.

[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to an LSI such as an LCD controller driver that controls the display of a liquid crystal device, which is the field of application that formed the background of the invention. The invention is not limited to the above, but can be applied to a display control device that controls a Rusk type display device such as a CRT display device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment in which the present invention is applied to an LCD controller driver, and FIG. 2(A) is an explanatory diagram showing a normal display character mode in a dot matrix type liquid crystal display device. CB) is an explanatory diagram showing the aspect of black and white inverted characters. DD-RAM...display data memory, CG-RO
M, CG-RAM...Character generator
Memory, IR...instruction register,
ID...Instruction decoder, AC...
・・Address counter + BUS・・・・Internal bus,
G1-Gx...Logic circuit (exclusive OR gate).

Claims (1)

[Claims] A display device having a one- or two-dimensional display screen, and display data displayed on the display screen of this display device is stored in the form of a code, and each of the stored codes or a display data memory having additional bits provided corresponding to a plurality of codes; a character generator memory for generating a corresponding display pattern based on codes read from the display data memory; a logic circuit that outputs the data read from the character generator memory as is or inverted according to the contents of the additional bits read together with the code from the display data memory, the contents of the additional bits; A display control system characterized in that a reversal symbol can be displayed on the display screen in accordance with the above. 2. A patent claim characterized in that the logic circuit is an exclusive OR gate circuit that takes an exclusive OR of the data from the character generator memory and the contents of the additional bits of the display data memory. The display control system according to item 1.