JPS62174792A - Display control system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] This invention relates to display control technology and technology that is particularly effective when applied to display shift control. This invention relates to techniques that are effective for use in liquid crystal display controller drivers.

[Prior art] L for controlling and driving a dot matrix type liquid crystal display device
A liquid crystal controller driver (hereinafter referred to as a liquid crystal controller) that is implemented as an SI (large scale integrated circuit) includes, for example, a display data RAM (random access memory) that stores display data as a code internally, and this display data RAM. A character generator ROM that forms a display pattern based on the code read out.
(read-on memory), and the parallel data read from this character generator ROM is converted into serial data and sent to the liquid crystal drive circuit to be displayed on the display panel of the liquid crystal display device. (Hitachi M
O8LSI Data Book LCD Driver LSIJ No. 52
(See pages 85-85).

[Problems to be Solved by the Invention] In the above-mentioned liquid crystal controller, when shifting characters etc. displayed on the display panel, a shift command for shifting the displayed characters etc. is input from the CPU each time. There must be.

Therefore, the CPU, for example, has a standby control terminal (ST
The object of the invention is that if the CPU enters standby mode, in which the BY terminal is set to low level, all clocks are stopped, and the internals are reset, the displayed characters cannot be shifted. The purpose is to enable display shifting even when the mode is set.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, a flip-flop circuit in which an automatic shift command signal is set in the liquid crystal controller and a frequency dividing circuit that divides the clock pulse in the liquid crystal controller into an appropriate period are provided, and the automatic shift command signal is set in the flip-flop circuit. During this period, the output of the frequency dividing circuit is supplied to the display counter as a shift control signal.

[Function] According to the above-mentioned means, once the flip-flop circuit is set by the automatic shift command signal, the shift control signal is supplied from the frequency dividing circuit to the display counter at regular intervals, so that the CPU is put into standby mode. The above object of being able to perform a display shift even if the display is set to

[Embodiment] FIG. 1 shows an embodiment in which the present invention is applied to a liquid crystal controller LSI.

Although not particularly limited, each circuit block surrounded by a two-dot chain line A in the figure is formed on one semiconductor chip such as a single crystal silicon substrate.

A power supply voltage Vce and a ground potential GND for internal circuits are applied from the outside to the semiconductor chip A, and oscillation signals osc1. os
c, and power supplies V to V for driving the liquid crystal display are supplied.

In FIG. 1, the circuit symbol IR is an instruction register that holds instructions supplied to the liquid crystal controller from an external microprocessor (not shown) via a single input/output buffer IOB. The instructions held in the instruction register IR are decoded by the instruction decoder ID, thereby forming internal control signals corresponding to various instructions such as "write PA", "display shift IT, it display clear", etc.

What is indicated by the circuit symbol AC is an address counter to which an address indicating a write position is set when data is written. This address counter AC includes instruction register IR and instruction register IR.
The instruction and the set write address are set via the decoder ID.

The circuit code DR indicates the input/output buffer IO
This is a data register that holds write data etc. supplied from the microprocessor via B. The data held in this data register DR is stored on the internal bus BU.
The data can be supplied to a display data RAM and a character generator RAM, which will be described later, via S.

In this embodiment, although not particularly limited, instruction codes and write data supplied from the microprocessor via common data input/output terminals DB, -DB3 and DB4 to DB7 are input to the instruction register IR and the data register. Selectively loaded into DR. To switch the data, a switching signal R8 is supplied from the microprocessor to the liquid crystal controller.

By this switching signal R8, the data input/output terminals DB, -
DB3. Signals input to DB, ~DB are taken into a desired register (IR or DR).

What is indicated by the circuit symbol DD-RAM is a display data RAM that can be read and written at any time and stores display data displayed on a display panel of a liquid crystal display device (not shown). This display data RAM (DD-RAM) is, for example, 8
It has a capacity to store 80 characters represented by bit codes.

What is indicated by the circuit code ROM is the above display data R.
This is a read-only character generator ROM in which pattern information for generating a signal (character pattern) corresponding to a character code read from AM (DD-RAM) is stored. Although not particularly limited, in this embodiment, in addition to the character generator ROM, a character generator RAM (CG-RAM) is provided in which the user can set and freely register arbitrary patterns.

The above character generator ROM (CG-RO
M) and character generator RAM (CG-R
AM) is the character code and timing generation circuit TG read out from the display data RAM (DD-RAM).
It is accessed by an address decoder AD which generates a selection signal by decoding a column signal synchronized with a common signal (signal applied to the common electrode of the display panel) supplied from the address decoder AD.

And character generator memory CG-RO
The character pattern data read out in parallel from the M or CG-RAM is converted into serial data in the parallel-to-serial conversion circuit PSC and supplied to the shift register SR1. When the shift register SR accumulates, for example, 40 bits of data supplied from the parallel-to-serial conversion circuit PSC, it sends them all together to a 40-bit latch circuit LTC in response to a synchronization signal CLI. Based on the data held in the latch circuit LTC, the segment signal driver SS
D forms segment signals 5EG1 to 5EG4° for driving segment electrodes of the liquid crystal display panel and outputs them to the outside of the chip.

Note that the circuit symbol TG indicates a timing generation circuit, and this timing generation circuit TG generates signals based on oscillation signals 08C1 and 08C2 supplied from external terminals.
It forms column signals supplied to the address decoder AD and internal clock signals for the aforementioned instruction register IR and other circuit blocks. The timing generation circuit includes a display counter that forms an address for sequentially reading display data in the display RAM.

Further, the timing generating circuit TG forms and outputs a synchronizing signal CL, C:L2°M for a liquid crystal driver LSI etc. externally attached to the liquid crystal controller of this embodiment.

Further, a display counter which constantly performs an address counting operation is provided in the timing generation circuit TO, and display data in the display data RAM is successively read out and displayed based on the address of this display counter. Further, in this embodiment, a 16-bit shift register SR2 which is shifted by a clock signal outputted from the timing generation circuit TG, an output signal of this shift register SR, and a power source V supplied from the outside are used. .about.V, a common signal driver C8D is provided which outputs common signals C0M1 to COM1s by a time division driving method such as 1/16 duty for the liquid crystal display device.

Further, in this embodiment, a cursor (underline for - characters) is displayed at the data writing position on the liquid crystal panel based on the address set in the address counter AC, and A cursor blink control circuit CBC is provided to blink and display characters indicating the position.

Note that the circuit code FLG is a busy flag that indicates the internal status of the liquid crystal controller LSI.By checking this busy flag FLG, the microprocessor can control the liquid crystal display, which operates at a slower speed than the microprocessor. The internal state of the controller can be known and successive accesses to the liquid crystal controller can be made to wait.

The contents of the busy flag FLG are the data input/output terminal D.
Output from one of B, ~DB (for example, DB) to the outside is possible. A signal E supplied from the microprocessor to the liquid crystal controller is an operation activation signal for the liquid crystal controller.

This liquid crystal controller includes a flip-flop circuit FF, a gate G1. G
2 and a frequency divider circuit FD are provided.

A set terminal S and a reset terminal R of the flip-flop circuit FF are connected to an instruction decoder ID, and an output terminal Q is connected to one input terminal of a gate G1. The frequency dividing circuit FD divides the clock generated from inside the liquid crystal controller to a desired period (for example, 0.5 seconds), and supplies the output to the other input terminal of the gate G1.

When the flip-flop circuit FF is set by the automatic shift command signal formed by decoding the automatic shift command taken into the instruction register IR by the instruction decoder ID, the gate G circuit is set by the signal output from the output terminal Q of the flip-flop circuit FF. One input terminal of is maintained at high level. Therefore, the output of the gate G□ is set to a high level only when the clock output from the frequency dividing circuit FD is at a high level. Therefore, a shift control signal is outputted from the output terminal of the gate G2 at a constant cycle, and is supplied to the display counter shown in FIG. 2 built in the timing generation circuit TG. That is,
Automatic shifting of characters, etc. displayed on a display panel becomes possible even if a shift command is not supplied from the CPU every time. Therefore, if an automatic shift command is given to the liquid crystal controller before the CPU enters standby mode, automatic shift 1- of the display will be performed in the display device when the CPU is in standby mode. If there is no need to shift the characters displayed on the display panel during standby, such a command may not be given. When the CPU changes from standby mode to normal operation mode, a new instruction is given from the CPU to the liquid crystal controller, and an automatic shift release signal is generated from the instruction decoder ID, which supplies the reset terminal R of the flip-flop circuit FF. and reset. As a result, the shift control signal is no longer supplied from the output terminal of the gate G2, and the automatic shift ends.

Furthermore, in the liquid crystal controller of this embodiment.

Two automatic shift commands, a right shift and a left shift, are provided, and shifts can be performed in either the left or right direction.

The display counter, which generates an address for reading display data (character code) stored in the display data RAM, is constantly counted up by a clock from an oscillation circuit provided inside the timing generation circuit TO to update the address. It is like that.

The characters displayed on the display panel are shifted as follows. That is, if you want to shift the displayed characters to the left, give an automatic shift command for left shifting. Then, when a shift control signal is supplied from gate G2, a left shift instruction signal is supplied from instruction decoder ID to timing generation circuit TO. Similarly, if you want to shift to the right, give an automatic shift command for right shifting and the instruction decoder ID
A right shift instruction signal is supplied to the timing generation circuit TG.

When the left shift instruction signal is supplied, the 1 display counter is operated to continuously count the same address (79) as shown in FIG. 2(B).

Further, when a right shift instruction signal is supplied, one address is skipped. In other words, as shown in Figure 2 (C), the next address after address (79) is the address (77
) are counted. As a result, the relative position between the address of the display counter and the latch signal CLI supplied from the timing generation circuit TO is shifted, and the display data is read out. As a result, the characters displayed on the display panel are continuously shifted to the left or right.

In the embodiment described above, a flip-flop circuit that is set by an automatic shift command signal, a frequency dividing circuit that generates a clock with a constant period, and a gate G1. By providing G2, once the flip-flop circuit is set by the automatic shift command signal, a shift control signal is output at regular intervals, so that the display can be shifted even if the CPU does not supply a shift command every time. The effect is that it can be done.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above embodiment, the characters displayed on the display panel are shifted by counting the addresses of the display counter and shifting their relative positions. It is also possible to shift the characters displayed on one display panel by supplying a shift clock that shifts the position of character data.

In the above description, the invention made by the present inventor will mainly be described as an LS such as an LCD controller driver that controls the display of a liquid crystal display device, which is the field of application that formed the background of the invention.
Although the present invention has been described with reference to an application to I, the present invention is not limited thereto, and can be applied to a display control device that controls a raster type display device such as a CRT display device.

In this embodiment, in addition to the shift control signal, the input terminal of the gate G2 can be supplied with a shift signal corresponding to a shift command sent by the CPU during normal operation from the infusion decoder ID. And the CPU
During normal operation, when the display is shifted, a shift signal is output each time in response to the shift command. As a result, the characters displayed on the display panel are shifted by one character.

[Effects of the Invention] Representative inventions disclosed in this application are summarized as follows.

That is, the 5TBY terminal of the CPU is set to low level,
The characters displayed on the screen of the liquid crystal display device can be shifted even when the CPU is in a standby mode in which all clocks are stopped and the internal unit is reset.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention applied to a liquid crystal controller LSI, and FIG. 2 is an explanatory diagram showing the relationship between the display address of a one-display counter and the timing of a latch signal. FF...Flip-flop circuit, FD...Divider circuit, G□, G2...Logic gate, DD-RAM...
...Display data memory, CG-ROM, CG-RA
M...Character generator memory, IR...
...Instruction register, ID...Instruction decoder, AC...Address counter, BUS...Internal bus.

Claims (1)

[Claims] 1. A display control system including a display control device whose operation is controlled by a control signal supplied from the outside and outputs a display data signal to be supplied to a display device, the display control system comprising: includes a storage means in which a display movement instruction signal is set based on the control signal, and while the display movement instruction signal is set, the pattern displayed by the display device is sequentially moved on the screen. A display control system characterized in that the display data signal is changed so as to change the display data signal. 2. The display device is a dot matrix type liquid crystal display device, and the display control device includes a readable and writable memory in which display data is stored, and a display pattern data based on the display data supplied from this memory. A display according to claim 1, characterized in that the display comprises a character generator for forming a character generator, and a parallel-to-serial conversion circuit that converts a signal output from the character generator into a serial signal and supplies it to the display device. control system.