JPS61235892A - Display control system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to display control technology, and relates to a technology that is effective when used in a liquid crystal display controller driver that controls and drives, for example, a dot matrix type liquid crystal display device.

[Background Art] As an LSI (Large Scale Integrated Circuit) liquid crystal display controller driver (hereinafter referred to as liquid crystal controller) that controls and drives a dot matrix type liquid crystal display device,
For example, a display data RAM (random access memory) that internally stores display data as a code, and a character generator R that forms a display pattern based on the code read from the display data RAM.
It has an OM (read-only memory), and the parallel data read from this character generator ROM is converted into serial data and sent to the liquid crystal drive circuit to be displayed on the display panel of the liquid crystal display device. There is something (Hitachi MO8LSI Data Book LCD Driver LS published by Hitachi, Ltd. in March 1988)
IJ, pages 52-85).

However, conventional LCD controllers do not have the ability to display an underline under the characters displayed on the LCD panel, and displaying such an underline requires a complicated external device. had the disadvantage of requiring a circuit.

[Object of the Invention] An object of the present invention is to provide a display control technique that allows an underline to be easily and freely displayed under displayed characters by adding simple hardware.

The above and other objects and novel features of the present invention will become clear from the description of the present specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

That is, in a display device such as a liquid crystal display device,
Focusing on the fact that there is generally an area for displaying a cursor under the area that constitutes the characters displayed on the display screen (liquid crystal panel), one example is stored in the display data memory where the display data is stored. An additional bit is provided to specify whether or not to underline each character code.
When driving the display, this additional bit is read together with the character code, and a signal for displaying an underline in the cursor display area is formed based on it and a display control signal such as a common electrode control signal. This achieves the above object of making it possible to easily and freely display underlines under displayed characters by adding simple hardware.

The present invention will be specifically explained below using the drawings.

[Embodiment] FIG. 1 shows an embodiment in which the present invention is applied to a liquid crystal controller LSI.

Although not particularly limited, each circuit block surrounded by a chain line A in the figure is formed on one semiconductor chip such as a single crystal silicon substrate.

A power supply voltage Vcc and a ground potential GND for the internal circuit are applied from the outside to the semiconductor chip A, and an oscillation signal 0SCI for forming an internal clock signal is applied.
03C2 and liquid crystal display driving power supplies v1 to v5 are supplied.

In FIG. 1, the circuit symbol IR is an instruction register that holds instructions supplied to the liquid crystal controller from an external microprocessor via an output buffer IOB. The instruction held in the instruction register IR is decoded by the instruction decoder ID and is
, 'display shift', 'display clear', and other internal control signals corresponding to various commands.

What is indicated by the circuit symbol AC is an address counter to which an address indicating a write position is set when data is written. This address counter AC includes instruction register IR and instruction register IR.
The instruction and the set write address are set via the decoder ID.

The circuit code DR is the human output buffer IO.
This is a data register that holds write data etc. supplied from the microprocessor via B. The data held in this data register DR is transferred to the internal bus BUS.
The data can be supplied to a display data RAM and a character generator RAM, which will be described later.

In this embodiment, although not particularly limited, the instruction code and write data supplied from the microprocessor via the common data input/output terminals DBO to DB3 and DB4 to DB are input to the instruction register IR and the data register. Selectively loaded into DR. To switch the data, a switching signal R3 is supplied from the microprocessor to the liquid crystal controller. By this switching signal R3, the data input/output terminal DB
o=DBae The signals input to D84 to DB7 are taken into a desired register (IR or DR).

What is indicated by the circuit symbol DD-RAM is a display data RAM that can be read and written at any time and stores display data displayed on a display panel of a liquid crystal display device (not shown). This display data RAM (DD-RAM) is, for example, 8
It has a capacity to store 80 characters represented by bit codes. Moreover, in this embodiment, an additional bit string BIT consisting of 80 bits is stored in the display data RAM in correspondence with the number of characters that can be stored, "80".
(DD-RAM), and when each 8-bit character code is read out, the information of one corresponding bit in this additional bit string BIT is read out at the same time.

However, writing to the additional bit string BIT is as follows:
Writing of the character code is performed via an internal bus BUS using a separate command.

What is indicated by the disconnection code ROM is the above display data R.
This is a read-only character generator ROM in which pattern information for generating signals (character patterns) corresponding to character codes read from AM (DD-RAM) is stored. Although not particularly limited, in this embodiment, in addition to the character generator ROM, a character generator RAM (CG-RAM) is provided in which the user can set and freely register arbitrary patterns.

The above character generator ROM (CG-ROM
) and character generator RAM (CG-RA
M) is the character code and timing generation circuit TG read out from the display data RAM (DD-RAM).
It is accessed by an address decoder AD that generates a selection signal by decoding a column signal synchronized with a common signal (signal applied to the common electrode of the display panel) supplied from the address decoder AD. , among the column signals supplied from the timing generation circuit TG to the address decoder AD, a column signal synchronized with a common signal corresponding to the cursor display position on the display panel, and an additional bit string BIT of the display data RAM (DD-RAM). An AND gate G is provided to take a logical product with a signal read out from the signal, and its output is supplied as an underline display signal to the parallel-to-serial conversion circuit PSC. The parallel-to-serial conversion circuit PSC is supplied with character pattern data read out in parallel from a character generator RAM and a ROM (hereinafter referred to as character generator memory) CG-ROM or CG-RAM, and here, Together with the underline display signal, it is converted into serial data and supplied to the shift register SRI.

When the shift register SR accumulates, for example, 40 bits of data supplied from the parallel-to-serial conversion circuit PsC, it sends them all together to a latch circuit LTC having a 40-bit configuration.

Segment signals 5EG1 to 5EG40 are used by the segment signal driver SSD to drive the segment electrodes of the liquid crystal display panel based on the data held in the latch circuit LTC.
is formed and output to the outside of the chip.

The circuit code TG indicates a timing generation circuit, and this timing generation circuit TG generates column signals supplied to the address decoder AD based on oscillation signals O8C□, 0SC2 supplied from external terminals. It also forms internal clock signals for the aforementioned instruction register IR and other circuit blocks. Further, the timing generation circuit TG generates a synchronization signal C for a liquid crystal driver LSI etc. externally attached to the liquid crystal controller of this embodiment.
L1. CL2. Form M and output.

Furthermore, in this embodiment, the timing generation circuit TG
A 16-bit shift register SR2 which is shifted by a clock signal output from
A common signal driver CSD is provided that outputs common signals COM and COM16 using a time division driving method such as a 16 duty cycle.

In addition, in this embodiment, a cursor (underline for - characters) is placed at the data writing position on the liquid crystal panel based on the address set in the address counter AC.
A cursor blink control circuit CBC is also provided for displaying the characters indicated by the address counter AC in a blinking manner.

Note that the circuit code FLG is a busy flag that indicates the internal status of the liquid crystal controller LSI.By checking this busy flag FLG, the microprocessor can control the liquid crystal display, which operates at a slower speed than the microprocessor. The internal state of the controller can be known and successive accesses to the liquid crystal controller can be made to wait.

The contents of busy flag FLG are data output terminal D.
Output from one of BO to DB (for example, DB7) is possible. A signal E supplied from the microprocessor to the liquid crystal controller is an operation activation signal for the liquid crystal controller.

In the liquid crystal controller of the above embodiment, if there is a character to be underlined under a character displayed on the liquid crystal panel, the additional bit corresponding to the address containing the character code is set to "1" in advance. If underlining is not required, write "0".

If you do this, display data RA when driving 5 displays.
The character code and the underline information of the corresponding additional bit are simultaneously read out from M (DD-RAM) and supplied to one input terminal of the AND gate G. AN
The other input terminal of the D gate G receives the common signals COM, ~COMto, which are output from the common signal driver C3D.
Among these, a common signal COM corresponding to the common electrode at the cursor display position and a column signal synchronized with COMx 6 (in the case of two-row display) are applied.

Therefore, if "1" is read from the additional bit, the output of the AND gate G is set to high level only when driving the common electrode at the cursor display position, and this signal performs parallel-to-serial conversion of the 5-bit configuration. All input signals of the circuit PSC are set to "1" and converted into serial data. As a result, if FIG. 2(A) shows the character pattern read out from the character generator memory CG-ROM or CG-RAM, the character pattern shown in FIG. 2(B) will appear on the liquid crystal panel. The underlined characters are displayed as shown below.

On the other hand, if ax O## is written in the additional bit, the output of the AND gate G is not changed to a high level, so the underline is not displayed.

In the above embodiment, an underline is displayed in the cursor display area. Therefore, it is not possible to display the cursor under an underlined character. Therefore, for example, an exclusive OR gate circuit is provided to take the exclusive OR of the cursor control signal output from the cursor blink control circuit in the above embodiment and the output signal of the AND gate circuit G.
The gate output is supplied to the parallel-to-serial conversion circuit PSG. With this, when the cursor is moved under a character that is already underlined, a white cursor can be displayed. Alternatively, it is also possible to display a blinking cursor instead of a white cursor.

In addition, in the above embodiment, a character generator RA, in which the user can arbitrarily register character patterns, is used.
Although the present invention has been described with reference to a controller equipped with CG-RAM (CG-RAM), it goes without saying that the present invention can also be applied to a liquid crystal controller that does not have such a RAM.

Furthermore, in the above embodiment, the display data RAM (DD-RAM) and character memory are stored inside the liquid crystal controller Lsr.
Although the description has been given of a device with a built-in generator ROM, etc., the present invention is not limited thereto, and may include a RAM for display data and a ROM for a character generator.
It can also be applied to a case where a system is configured by externally attaching the controller LSI to a controller LSI.

[Effect: For example, an additional bit is provided in the display data memory where display data is stored to specify whether or not to draw an underline for each stored character code, and when driving the display, this additional bit is added along with the character code. Since the bit is read out and a signal for displaying an underline in the cursor display area is generated based on it and the common electrode control signal, all you need to do is write 111 ## to the additional bit in advance. Underlining automatically generates an underline display signal synchronized with the common signal without the need for any circuitry, so it is possible to easily and freely underline the displayed characters by making simple hardware changes. This has the effect of being able to be displayed.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above embodiment, a case has been described in which it is possible to specify whether or not to draw an underline for each - character, but normally it is often desired to draw an underline across two or more characters. Therefore, instead of providing an additional bit string for each character code in the display data RAM, a register for specifying the position of the character where underlining starts and a register specifying the position of the character where underlining ends may be provided.

[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to an LSI such as an LCD controller driver that controls the display of a liquid crystal device, which is the field of application that formed the background of the invention. The invention is not limited thereto.

It can be used in a display control device that controls a Rusk type display device such as a CRT display device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment in which the present invention is applied to an LCD controller driver, and FIG. (B) is an explanatory diagram showing an example of a character pattern in which an underline is displayed below the character. DD-RAM...display data memory, CG-RO
M, CG-RAM...Character generator
Memory, IR...instruction register,
ID...Instruction decoder, AC...
...Address counter, BUS-. ...Internal bus, G...Signal circuit (AND gate).

Claims (1)

[Claims] A display device having a one- or two-dimensional display screen, and display data displayed on the display screen of this display device is stored in the form of a code, and each of the stored codes or A display data memory having additional bits provided corresponding to a plurality of codes, and a character generator memory generating a corresponding display pattern based on the codes read from the display data memory. ,
A signal circuit is provided for forming an underline display signal based on a control signal for reading data from the character generator memory and the contents of the additional bits read from the display data memory. display control system. 2. It has a cursor control circuit for displaying a cursor below the displayed characters on the display screen, and the signal circuit is supplied with a cursor control signal from this cursor control circuit, so that the underline and the cursor are the same. 2. The display control system according to claim 1, wherein the display control system is capable of being displayed in a display area.