JPS62183488A - Display control unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a display control technology, and relates to a technology that is effective for use in, for example, a liquid crystal display controller driver that controls and drives a dot matrix type liquid crystal display device.

[Prior Art] As an LSI (Large Scale Integrated Circuit) liquid crystal display controller driver (hereinafter referred to as liquid crystal controller) that controls and drives a dot matrix type liquid crystal display device,
For example, a display data RAM (random access memory) that internally stores display data as a code, and a character generator RO that forms a display pattern based on the code read from the display data RAM.
M (read-only memory), and the parallel data read from this character generator ROM was converted into serial data and sent to the liquid crystal drive circuit to be displayed on the display panel of the liquid crystal display device. There is something (published by Hitachi, Ltd. in March 1982)
Hitachi MO8LSI Data Book LCD Driver LSI
J pages 52-85).

[Problems to be Solved by the Invention] The liquid crystal controller has a blinking function that causes specified characters (or codes) on the display screen to blink. However, the blinking function was a blinking function that alternately displayed designated characters and a black background pattern. In other words, one of the blinking patterns is fixed to a black background (or white), and there is no room for the user to select it.

Therefore, there is an inconvenience in that it is not possible to enhance the display effect and improve the display function by freely setting the blinking pattern and blinking characters on the display screen that are particularly desired to draw attention.

An object of the present invention is to provide a display control technique that can improve editing functions and display functions by simply adding hardware.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

In other words, it detects whether the address register that stores the address of the character to be displayed blinking on the display screen and the address signal that accesses the display data memory during display drive match the address set in this register. and a circuit for forming a blink control signal based on the address detection signal and a clock signal of an appropriate period, and a pattern RA for one character into which any pattern can be written from the outside.
M is provided, and by registering an appropriate pattern in this pattern RAM in advance, the signal and pattern read from the character generator ROM can be controlled by the control signal generated from the blink control circuit when performing a blinking display. A gate circuit is provided to alternately send signals read from the RAM.

[Operation] According to the above-described means, when the display data corresponding to the address set in the register is read, the pattern of the display character and the pattern registered in the pattern RAM are matched by the gate circuit controlled by the blink control signal. Due to the effect of alternating output, characters at a specified position on the display screen can be displayed blinking in any pattern, thereby enhancing the display effect and improving the editing and display functions. can be achieved.

The present invention will be specifically explained below using the drawings.

[Embodiment] FIG. 1 shows an embodiment in which the present invention is applied to a liquid crystal controller LSI.

Although not particularly limited, each circuit block surrounded by a chain line A in the figure is formed on one semiconductor chip such as a single crystal silicon substrate.

A power supply voltage Vec and a ground potential GND for the internal circuit are applied from the outside to the semiconductor chip A, and oscillation signals ○SC1, ○S for forming internal clock signals are applied to the semiconductor chip A.
C2 and liquid crystal display drive power supply V.

~v5 is now supplied.

In FIG. 1, one circuit numbered IR is an instruction register that holds instructions supplied to the liquid crystal controller from an external microprocessor via an output buffer IOB. The instruction held in the instruction register IR is decoded by the instruction decoder ID and is
u Display blinking 1j, l (forms internal control signals corresponding to various commands such as display clear'').

What is indicated by the circuit symbol AC is an address counter to which an address indicating a write position is set when data is written. A write address set with an instruction is set in this address counter AC via an instruction decoder.

The circuit code DR indicates the input/output bumper circuit ○
This is a data register that holds write data etc. supplied from the microprocessor via B. The data held in this data register DR is transferred to the internal bus BUS.
The data can be supplied to a display data RAM and a character generator RAM, which will be described later.

In this embodiment, the instruction code and write data supplied from the microprocessor via the common data input/output terminals DB, -DB3 and DB, to DB7 are transferred to the instruction register IR, which is not particularly limited.
and selectively loaded into data register DR.

To switch the data, a switching signal RS is supplied from the microprocessor to the liquid crystal controller.

By this switching signal R3, the data input/output terminals DB, -
DB3. Signals input to DB4 to DB are taken into a desired register (IR or DR).

What is indicated by the circuit symbol DD-RAM is a display data RAM that can be read and written at any time and stores display data displayed on a display panel of a liquid crystal display device (not shown). This display data RAM ([)p-RAM) is
For example, the memory is designed to have a capacity to store 80 characters represented by 8-bit codes.

The circuit code CG-ROM is a read-only memory that stores pattern information for generating a signal (character pattern) corresponding to the character code read from the display data RAM (DD-RAM). This is a character generator ROM.

Although not particularly limited, in this embodiment, in addition to the character generator ROM (CG-ROM), there is also a character generator RAM (CG-RAM) in which the user can set and freely register arbitrary patterns.
is provided.

The above character generator ROM (CG-ROM
) and character generator RAM (CG-RA
M) decodes the character code read from the display data RAM (DD-RAM) and the column signal synchronized with the common signal (signal applied to the common electrode of the display panel) supplied from the timing generation circuit TG. is accessed by an address decoder AD which generates a selection signal.

In this embodiment, a pattern RAM (
P-RAM) and a blink control circuit BLC are provided, and the display data RAM (
When the address signal supplied to the DD-RAM matches the address set in the register inside the blink control circuit BLC, a blink control signal is formed and output.

Further, column signals supplied from the timing generation circuit TG to the address decoder AD are supplied to the pattern RAM (P-RAM), so that pattern data is read out column by column. and.

Based on the blink control signal output from the blink control circuit BLC, the character generator RA
M and ROM (hereinafter referred to as character generator
), CG-ROM or CG-RA
M output signal or the above pattern RAM (p-RAM
) is provided with a gate circuit G2 which selectively sends out one of the signals outputted from the circuit G2, and its output is supplied to the parallel-to-serial conversion circuit PSC.

In the drawing, gate circuits G and G2 are shown one by one, but in reality each character generator memory C
A number corresponding to the number of bits of data read out in parallel from the G-ROM and CG-RAM are provided. The character pattern data read out in parallel from the character generator memory CG-ROM or CG-RAM.

The data is supplied as is to the parallel-to-serial conversion circuit PSC, where it is converted into serial data and supplied to the shift register SR1.

When the shift register SR1 accumulates, for example, 40 bits of data supplied from the parallel-to-serial conversion circuit PSC, it sends them all together to a latch circuit LTC having a 40-bit configuration.

Based on the data held in the latch circuit LTC, the segment signal driver SSD forms segment signals 5EG1 to 5EG4° for driving the segment electrodes of the liquid crystal display panel and outputs them to the outside of the chip.

Note that the circuit symbol TG indicates a timing generation circuit, and this timing generation circuit TG generates an oscillation signal SC supplied from an external terminal.

o Based on SC2, a column signal supplied to the address decoder AD and an internal clock signal for the aforementioned instruction register IR and other circuit blocks are formed. Furthermore, the timing generation circuit TG generates synchronization signals CL, CL2. Form M and output.

Further, a display counter that constantly performs an address counting operation is provided in the timing generation circuit TO, and display data in the display data RAM is successively read out and displayed based on the address of this display counter.

FIG. 2 shows the blink control circuit BLC and the gate circuit G1. An example of G is shown. In this embodiment, an address register REGs for setting the address of a character to be displayed blinking and a blinking counter CNT are provided. Further, a one-number output circuit CIN is provided corresponding to this register REG, and the -number output circuit CIN contains the address set in the register REG and the display counter DC in the timing generation circuit TG. A display address signal outputted from the display address signal is inputted to each of the display address signals. The minus number output circuit CIN outputs a coincidence detection signal when the address signal supplied from the display counter DC to the display data RAM (DD-RAM) matches the address set in the register REG. The AND gate G0 is opened by this minus number output signal, and the clock C with a period of 2 to 3 seconds is output from the blinking counter CNT.
K is supplied to the gate G1 (and G,). The blinking counter CNT divides the frequency of the clock from the timing generation circuit TG to form a clock OK with a period suitable for blinking.

On the other hand, if the address signal output from the display counter DC does not match the address set in the register REG, it is ANDed by the output from the -number construction circuit CIN.
The output of the gate G0 is fixed at a low level, and the blinking clock CK is no longer supplied to the gate circuits G and G2.

Gate circuit G to which blinking clock GK is supplied
clock C (or G2), as shown in Figure 2.
AND gate G11 that is opened and closed by K to pass or block the output of the pattern RAM (P-RAM), and the inverted output of the clock CK (output of the inverter INV)
AND gate G1□ which is opened and closed by and passes through or blocks the output of the character generator memory CG-ROM or CG-RAM;
Gate G11. ○R gate G1. which supplies the output of G gate 2 to the subsequent parallel-to-serial conversion circuit PsC. It is composed of.

Therefore, the output from the blink control circuit BLC, that is, the A'ND gate G. While the output of the character generator memory CG-RAM or CG-ROM is fixed at a low level, the AND gate G1□ is opened and the output of the character generator memory CG-RAM or CG-ROM is directly supplied to the parallel-to-serial conversion circuit PSC. Also, when the display address matches the address in the address register REG, the blinking clock CK is switched to the gate circuit G□ (G2) by the detection signal of the one-digit circuit CIN.
AND gates G1□ and 0□2
and are opened alternately every 2 to 3 seconds. Therefore, the character generator memory CG-RAM or C
The output of the G-ROM and the output of the pattern RAM (P-RAM) are alternately supplied to the parallel-to-serial conversion circuit PSC. As a result, for example, if a black background pattern is registered in the pattern RAM, the specified character on the screen will be
As shown in Figure (a), a blinking display is performed in which the character display "A" and the display of a black background pattern are repeated.

Further, when a white pattern is registered in the pattern RAM (P-RAM), the display character "A" and the white pattern are alternately displayed on and off as shown in FIG. 3(b). In addition, in this embodiment, the pattern RAM
Any pattern registered in (P-RAM) and display characters can be displayed alternately.

To set the address to the above address register REG,
For example, this can be done by writing the instruction and the set address via the instruction register IR and instruction decoder ID in the same way as setting the address in the address counter AC. Internal bus BUS via data register DR
It is also possible to set the register REG via the route.

In the embodiment shown in FIG. 1, the timing generation circuit T
A 16-bit shift register SR2, which is shifted by a clock signal output from O, and a 17-bit shift register for the liquid crystal display device based on the output signal of this shift register SR and externally supplied power supplies v1 to v5.
A common signal driver C3D is provided that outputs common signals C0M1 to COM□6 using a time-division driving method such as a 16-duty drive system.

Further, in this embodiment, a cursor control circuit CSC is provided to display a cursor (underline for - characters) at a corresponding position on the liquid crystal panel based on the address set in the address counter AC. There is.

Furthermore, what is indicated by the circuit symbol FLG is a busy flag that indicates the internal state of the liquid crystal controller LSI.
By checking this busy flag FLG, the microprocessor can learn the internal state of the liquid crystal controller, which operates at a slower speed than the microprocessor, and is made to wait for successive accesses to the liquid crystal controller. There is.

The contents of the busy flag FLG are the data input/output terminal D.
Output from one of B, ~DB (for example, DB) to the outside is enabled. A signal E supplied from the microprocessor to the liquid crystal controller is an operation activation signal for the liquid crystal controller.

As explained above, in the above embodiment, the address register that stores the address of the character to be displayed blinking on the display screen and the address signal that accesses the display data memory when driving the display are set in this register. A blink control circuit consisting of a means for detecting whether the address matches the address detected, and a circuit for forming a blink control signal based on the address detection signal and a clock signal of an appropriate period, and writing an arbitrary pattern from outside. A pattern RAM for one character is provided, and by registering an appropriate pattern in this pattern RAM in advance, the control signal generated from the blink control circuit when displaying one blink can be used to transfer data from the character generator memory. Since a gate circuit is provided that alternately sends out the read signal and the signal read out from the pattern RAM, when the display data at the set address position is read out, the gate controlled by the blink control signal Due to the effect that the display data pattern and the pattern registered in the pattern RAM are output alternately by the circuit, it is possible to perform a blinking display of characters at a specified position on the display screen and an arbitrary pattern. This has the effect that the display effect can be enhanced and the editing function and display function can be improved.

Although the invention made by the present inventor has been specifically explained above based on Examples, it is to be noted that the present invention is not limited to the above-mentioned Examples, and that various changes can be made within the scope without departing from the gist thereof. Not even.

In the above description, the invention made by the present inventor was mainly applied to an LSI such as an LCD controller driver that controls the display of a liquid crystal device, which is the background field of application of the invention, but the invention is not limited to that. It can also be used as a display control device for controlling a Rusk type display device such as a CRT display device.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

In other words, with the addition of simple hardware, it is possible to display specified characters on the display screen alternately with an arbitrary pattern, making editing work easier by blinking the character position you want to insert, for example. By flashing the characters you want to draw attention to on the display screen,
It is possible to enhance the display effect and thereby improve the display function.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an example of the case where the present invention is applied to an LCD controller driver, Fig. 2 is a circuit configuration diagram showing an example of a blink control circuit, and Figs. FIG. 3 is an explanatory diagram showing a blinking display on a display screen when the invention is applied. DD-RAM...display data memory, CG-RO
M, CG-RAM...Character generator
Memory, P-RAM...Pattern RAM, IR...
...Instruction register, ID...Instruction decoder, AC...Address counter, BLC...Blink control circuit, BUS...
・Internal bus, G1. G2...Gate circuit, RE
G: address register, CIN: - number configuration circuit.

Claims (1)

[Claims] 1. A pattern memory that can register an arbitrary pattern for at least one character, a register that can set the address of an arbitrary character to be displayed on the display screen of a display device having a two-dimensional display screen, and display data. A display data memory to be stored, a coincidence detection means for detecting whether the address signal supplied to the display data memory matches the address set in the register, and a detection signal from the coincidence detection means and a predetermined a signal forming means for forming a blink control signal for display blinking control based on a clock signal with a period of , and a gate circuit for selectively outputting display data or data in the pattern memory based on the blink control signal. A display control circuit comprising: