JPS6142683A - Crt display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a CR that is connected to an electronic computer and displays dot patterns, characters, symbols, etc. in raster format.
This invention relates to a T display device.

[Prior art]

Generally, this 417) CRT display device has a built-in screen memory for storing dot patterns and a synchronization signal generation port for driving the CRT's deflection circuit.

The dot pattern read from the screen memory is converted into a serial video signal and then supplied to a circuit that controls the amount of electron beam of the CRT, but if this control timing does not match the operation of the deflection circuit, , the correct display will not be performed. Therefore, the synchronization signal generation circuit normally generates the synchronization signal using the read address of the screen memory as a supply source.

As shown in FIG. 1, there are two types of synchronizing signals for driving the deflection circuit: horizontal synchronizing signals and vertical synchronizing signals.

Conventionally, these synchronization signals have been generated by a synchronization signal generation circuit as shown in FIG. The generation level wL of these synchronization signals is defined by the performance of the deflection circuit used. As shown in FIG. 1, the generation positions of the horizontal synchronizing signal and the vertical retrace period are set within the horizontal retrace period and the vertical retrace period, respectively. That is, as shown in FIG. 2, the horizontal synchronization signal is generated by decoding a column address signal that counts up in response to horizontal scanning of the screen as a part of the readout address of the screen. The vertical synchronization signal is a part of the address and is generated by decoding a line address signal that counts up in response to scanning in the vertical direction of the screen. For this reason, in a device with a large display capacity, the column address signal and line address signal increase, resulting in a disadvantage that the decoding circuit used becomes complex.

[Summary of the invention]

This invention was made in order to eliminate the above-mentioned drawbacks of the conventional device, and includes a built-in area in the screen memory that can be read during both the horizontal and vertical retrace periods, so that the storage bits of display information can be stored. Bits for storing external horizontal synchronization information and vertical synchronization information are added, and significant information is written in advance from the electronic total 31 to those at predetermined addresses among these bits. 11? Generate a horizontal synchronization signal and a vertical synchronization signal when the is read out? It is an object of the present invention to provide a CRT display device in which a synchronizing signal generating circuit, which was conventionally necessary, can be omitted.

[Embodiments of the invention]

An embodiment of the present invention will be explained below with reference to the drawings. Third
The figure is a block diagram showing the configuration of the main parts of the device according to the embodiment of the present invention.
is an address counter that generates a screen memory read address, which will be described later.
This is a selector that selects the read address from ) and supplies it to the screen memory. Control is performed so that the input address is divided into two within the 1-column display length cycle and alternately applied to the screen memory.

(Kohiro) is the screen memory, and this screen memory (Yuri) has an area that can also store the horizontal retrace area for the horizontal period, and also the vertical retrace area for the vertical period, and further , it is possible to store horizontal synchronization information and vertical synchronization information in addition to display information. It is a step. Also, (ko b), (x
7) respectively, the horizontal synchronization signal and the vertical synchronization signal which are the output of the screen mesori (Yup), and the CRT (not shown) from the (Yup) video signal generation time 36C2K.
This is the video signal supplied by K.

FIG. 1I is an exemplary diagram of a memory map of the screen memory (YUlI) shown in FIG. 3. Also, Figures 5 and 6 are
FIG. 4 is a timing chart diagram for explaining the operation of the embodiment of the present invention. In the following explanation, the display capacity will be expressed as horizontal columns, vertical n lines, and horizontal return area! The case of column, vertical retrace area m line will be explained as an example.

First of all, in Figure 3, (a) shows the storage area of the screen memory (lily) in Figure 3 from above in the vertical scanning direction.
It is a diagram in which each line is arranged in order. However, the middle line is omitted due to the grinding surface. The /H part shown in Figure DA (A) indicates the scanning line of information displayed at the top of the screen, and the nH section means the scanning line of information displayed at the bottom. ing. In this figure reference (a)/H
An enlarged view of the section in the column direction is shown in the same figure (b). In this figure (b), the horizontal display area is columns 1 to 1, and the horizontal retrace area is 1 columns from column (k+t) to column (k+j). Komata de l
The column is configured with lO bits, and t of bQ-bt
The bits are used as display information of the dot pattern, b
t is assigned as horizontal synchronization information, and b is assigned as vertical synchronization information. Both bt and bγ are
It is treated as significant when ``l'' stands,
In this diagram (b), the (k+/)th column and (
The horizontal synchronization information is "/"K in the k+uno column.

Although this horizontal synchronization information is not shown, the (k+/)th column and (k+
``/' is inscribed in all the parts corresponding to the column number. In Figure 1 (/-1), (n + /) is written in the vertical retrace area in Figure (A). From a part of H (
The range corresponding to a part of H is shown expanded in the column direction. The meanings given to the bits in this figure (c) are the same as in the case of the same figure (b). Here, b? The vertical synchronization information in (n +
/ ) H's (k+2) column giant to (njuhiro) H's r
11'' is written continuously up to the k+/) column.

As mentioned above, the screen memory (KODA) stores horizontal synchronization information and vertical synchronization information in addition to display information. First, looking at the horizontal period, screen memory
The output (bo-by) is shown in Figure 5 (5K), and in the horizontal display area, the memory contents of columns 1 to 1 are as follows:
Furthermore, in the horizontal display area, the stored contents of columns (k10 to (k+J)) are read out.

Then, in the /- column, a dot pattern corresponding to % by is output as shown in FIG. 5(E). Also, in the (k+co) column and (k+J) column, the horizontal synchronization information corresponding to It is supplied to the CRT as a synchronizing signal (26).

Next, during the vertical retrace period, the outputs (bo to bt) of the screen memory (Judas) are output as shown in Figure 6 (g). In this case, the vertical display period has elapsed. ℃
Because it is closed, K, dratonoku turn (bo-bγ)
60" is output as shown in FIG. Therefore, the output is as shown in FIG. 6(IJ)K.

And for the vertical synchronization signal (br), (n+/)
From the (k+)th column of H to (njuhiro) (k+/) of H
Since * and * are continuously inserted up to the column, the signal is output as shown in Figure 1 (Figure 1), and that signal is the vertical synchronization signal (2) shown in Figure 3. It will be supplied to the CRT as a

In the above embodiment, the explanation code may be stored in the case where the dot pattern is stored in the screen memory as display information.

〔Effect of the invention〕

As explained above, according to the present invention, since the information corresponding to the horizontal synchronization signal and the vertical synchronization signal is stored on the screen menu, the synchronization signal generation circuit that was conventionally required is unnecessary. Furthermore, these synchronization signals can be generated at any desired position within the retrace period, making it possible to quickly respond to changes in specifications on the deflection rotation side, for example. There are effects such as being able to do it.

[Brief explanation of the drawing]

FIG. 1 is a general timing chart of synchronization signals, FIG. 2 is a schematic diagram of a conventional synchronization signal generation circuit, and FIG. 3 is a block diagram of the main parts of a CRT display device according to an embodiment of the present invention. The figure is an exemplary diagram of a memory map of the screen memory according to an embodiment of the present invention, and FIGS. S and 6 are timing charts for explaining the operation of the embodiment of the present invention. In the figure, (L) is a timing generation circuit, (Y) is an address kakunta, (J) is a selector, (Y) is a screen memory, (2) is a video generation circuit, and (26) is a horizontal synchronization circuit. The signal (near) is the vertical synchronization signal. In the figures, the same symbols indicate the same or corresponding parts.

Claims (1)

[Claims] In a CRT display device that converts display information stored in a screen memory into a video signal and causes the CRT to perform a display operation using a predetermined synchronization signal, the screen memory has a storage area for the display information and a storage area for the display information. A storage area that can be read even during the retrace period of the CRT is provided, horizontal synchronization information and vertical synchronization information are stored in addition to the display information, and the synchronization signal used for the display operation is stored in the additional storage area. 1. A CRT display device, characterized in that the display is created from horizontal synchronization information and vertical synchronization information.