JPH05341727A - Display control system - Google Patents

Abstract

PURPOSE:To automatically discriminate a specification of various flat panel displays with simple constitution. CONSTITUTION:A ROM 401 is provided in a flat panel display 40, since various status data required for display and control is stored in the ROM 41, specifications of various flat panel displays can be discriminated by reading out the status data, and display and control can be performed in accordance with specifications of various flat panel display. Also, since a data line 101 in which video data is transferred is made as a bidirectional data line and read out of control information is performed by switching the direction of the bidirectional data line, increasing of numbers of signal lines between a display controller 10 and the flat panel display 40 cannot be caused.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device for a portable computer, and more particularly to a display control device capable of performing display control corresponding to various flat panel displays.

[0002]

2. Description of the Related Art Recently, various portable laptop or notebook type portable computers have been developed.

A typical portable computer of this type is equipped with a flat panel display such as a plasma display (PDP) or a liquid crystal display (LCD) as standard equipment. This flat panel display is rotatably provided in the range between the closed position and the open position with respect to the computer body. When the flat panel display is set to the closed position, the flat panel display is positioned to cover the keyboard integrated with the computer body, which makes the computer easy to carry. Therefore, the flat panel display is suitable for a portable computer in terms of improving its portability.

Further, recent portable computers are equipped with a video output terminal to a color CRT display so that a color CRT display can be connected if necessary. Since the color CRT display has been widely used as a monitor of a desktop type personal computer, many application programs for the color CRT display have been developed. Therefore, the portable computer that can use the color CRT display can effectively use the existing software resources, and can perform the same operation as the desktop type personal computer.

By the way, the flat panel display and the color CRT display require separate display control. In particular, in the case of flat panel displays, there are various types, and the specifications of each flat panel display {resolution, color / gradation, display color number / gradation number, panel type (TFT-LCD, ST
Display control suitable for N-LCD, PDP, etc., timing (horizontal / vertical sync signal), polarity (horizontal / vertical sync signal, video data, clock, etc.) is required.

Therefore, the conventional display controller is configured so that the display timing and the like can be switched in accordance with the flat panel display to be used in order to perform display control corresponding to various flat panel displays. Conventionally, this switching is done with a dip switch etc. provided in the display controller,
It was done by setting the on / off according to the flat panel display used.

However, such an ON / OFF setting by the DIP switch causes a problem such as an increase in the hardware configuration, so that there is a limit to the kind of display that can be discriminated. Therefore, it is obvious that it will not be possible to cope with the ever-increasing types of flat panel displays.

[0008]

Conventionally, since the type of the flat panel display is discriminated by the ON / OFF setting of the DIP switch, etc.,
There was a drawback that there were few types of flat panel displays that could be identified.

The present invention has been made in view of the above circumstances, and enables the specifications of various flat panel displays to be automatically determined with a simple structure, and the display control according to the flat panel display to be used. An object is to provide a display control system that can be performed.

[0010]

A display control system according to the present invention includes a flat panel display and a memory provided in the flat panel display for storing various control information necessary for display control of the flat panel display. A display control device for generating a display timing control signal for controlling display data to be displayed on the flat panel display and its display timing; and a display control device provided in the display control device for storing the control information from the memory device. Means for generating a read control signal for reading and supplying the read control signal to a memory device of the flat panel display; and the video data generated from the display control device or the video data provided between the flat panel display and the display control device. Read from memory device A bidirectional data line to which the control information is transferred, and the video data is transferred from the display control device to the flat panel display so that the control information is transferred from the flat panel display to the display control device. And a transfer direction switching means for switching the data transfer direction of the bidirectional data line.

In this display control system, a memory device is provided in the panel, and various control information necessary for display control is stored in the memory device. Therefore, various flat information can be read by reading the control information. The panel display can be automatically identified, and display control can be performed according to the specifications of various flat panel displays. Further, since the data line to which the video data is transferred is a bidirectional data line and the control information is read by switching the direction of the bidirectional data line, the signal line between the display control device and the flat panel display is read. It does not increase the number. Therefore, it is possible to determine the flat panel display with a simple configuration.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the overall structure of a display control device according to an embodiment of the present invention. This display control system 4 is, for example, 1024 × 768 dots, 256
XGA (eXtended G) with a display mode for simultaneous color display
It is a display control system of the raphics Array specification and is connected to the system bus 3 of the portable computer.
The display control system 4 includes a flat panel display 40 that is standard equipment in a portable computer and a color CRT display 5 that is optionally connected.
Display control for both 0 is performed. As the flat panel display 40, resolution, color / gradation, display color number / gradation number, panel type (TFT-LCD, ST
Various types having different specifications can be used in terms of N-LCD, PDP, etc.), timing (horizontal / vertical synchronizing signal), polarity (horizontal / vertical synchronizing signal, video data, clock, etc.). In this case, these panels are interchangeable, for example from low resolution to high resolution
Alternatively, the gradation display can be replaced with the color display.

The flat panel display 40 is provided with a ROM 401 in which various status information necessary for display control of the panel is stored. As described above, the status information includes resolution, color / gradation, display color number / gradation number, panel type (TFT-LCD, STN).
-LCD, PDP, etc.), timing (horizontal / vertical sync signal), polarity (horizontal / vertical sync signal, video data, clock, etc.). The configuration around the ROM 401 of the flat panel display 40 will be described later with reference to FIG.

The display control system 4 includes a display controller 10 and a dual port image memory (VRA).
M) 30 and a DAC (D / A converter) 35 are provided. These display controllers 10,
Dual port image memory (VRAM) 30, and D
The AC 35 is mounted on a circuit board (not shown).

The display controller 10 is an LSI realized by a gate array, and is a main part of the display control system 4. The display controller 10 uses a dual port image memory (VRAM) 30 and a DAC 35 in accordance with an instruction from the CPU 1, and uses a flat panel display 40 and a color CR.
The display control for the T display 50 is executed. Further, the display controller 10 functions as a bus master and can directly access the system memory 2.

Dual port image memory (VRAM) 3
0 has a serial port (serial DATA) used for serial access and a parallel port (DATA) for random access. The serial port (serial DATA) is used to read data for refreshing the display screen, and the parallel port (DA).
TA) is used to update the display data. The dual-port image memory (VRAM) 30 is composed of a plurality of dual-port DRAMs and has 1 Mbyte to 4 Mbytes.
It has a storage capacity of M bytes. Display data to be displayed on the flat panel display 40 or the color CRT display 50 is drawn on the dual port image memory (VRAM) 30.

In this case, drawing data of XGA specifications created by an application program or the like conforming to XGA specifications is stored in the dual port image memory (VRAM) 30 by the packed pixel method. The packed pixel method is a color information mapping format in which one pixel is represented by consecutive bits on a memory, and for example, a method in which one pixel is represented by 1, 2, 4, 8 or 16 bits is adopted. On the other hand, the VGA specification drawing data is created by a conventional application program or the like conforming to the VGA specification, and is drawn in the dual port image memory (VRAM) 30 by the memory plane method.
The memory plane method is a method in which a memory area is divided into a plurality of planes designated by the same address and color information of each pixel is assigned to these planes. For example, 4
If you have planes, one pixel is 1 for each plane.
It is represented by a total of 4 bits of data, bit by bit.

A dual port image memory (VRA
Text data is also stored in M) 30. The text data for one character has a total size of 2 bytes including an 8-bit code and an 8-bit attribute in both the XGA and VGA specifications. The attribute is composed of 4-bit data that specifies the foreground color and 4-bit data that specifies the background color.

The DAC 35 converts the CRT video data generated by the display controller 10 into analog R, G, B signals and supplies them to the CRT display 50.

The display controller 10 includes a register control circuit 11, a system bus interface 12,
Drawing coprocessor 13, memory data bus control circuit 14, CRT controller (CRTC) 15, memory address bus control circuit 16, memory control circuit 18, sprite memory 19, serializer 20, latch circuit 21,
Foreground / background multiplexer 22,
The graphic / text multiplexer 23, color palette 24, sprite color register 25, CRT video multiplexer 26, sprite control circuit 27, and flat panel emulation circuit 28 are included.

The register control circuit 11 receives an address and data from the system bus 3 via the system bus interface 12, decodes the address, and performs read / write control on various registers designated by the decoding result. The system bus interface 12 controls the interface with the host system via the system bus 3, and supports a bus interface conforming to various specifications such as ISA, EISA, micro channel, and local bus.

The drawing coprocessor 13 is responsive to an instruction from the CPU 1 to generate a dual port image memory (VRA).
M) provides various drawing functions for drawing data in 30. Block transfer of pixels, line drawing, area filling, logical / arithmetic operation between pixels, screen cutout, map mask, X -It has a memory management function by addressing at the Y coordinate and paging.
The drawing coprocessor 13 includes a VGA / XGA compatible data operation circuit 131 and a two-dimensional address generation circuit 13.
1 and a paging unit 133 are provided.

The data operation circuit 131 performs data operations such as shift, logical arithmetic operation, bit mask and color comparison, and also has a VGA compatible BITBLT function. The two-dimensional address generation circuit 131 generates an XY two-dimensional address for accessing a rectangular area or the like. The two-dimensional address generation circuit 131 also performs a region check and a conversion process to a linear address (real memory address) using segmentation or the like. The paging unit 133 is for supporting the same virtual memory mechanism as the CPU 1, and converts the linear address created by the two-dimensional address generation circuit 131 into a real address by paging when paging is enabled. Further, when paging is invalid, the linear address becomes the real address as it is. The paging unit 133 has a TLB for paging.

The memory data bus control circuit 14 is for controlling the data bus of the parallel data port (DATA) of the dual port image memory (VRAM) 30, and has four map data of source, pattern, mask and destination. It is equipped with a buffer for collectively accessing in the page mode. This buffer also functions as a write data buffer.

The CRT controller 15 is an XGA CRTC that generates various display timing signals for displaying a screen on the flat panel display 40 or the CRT display 50 at a high resolution (for example, 1024 × 768 dots) conforming to the XGA specifications. And a flat panel display 40 or a CRT display 5 with a medium resolution (for example, 640 × 480 dots) that meets VGA specifications.
A CRTC for VGA that generates various display timing signals for displaying a screen is displayed. These display timing signals are generated using a horizontal / vertical counter provided in the CRT controller 15. Also,
The CRT controller 15 synchronizes with a display timing for XGA or VGA, and an XY pixel address indicating a coordinate position on a display screen corresponding to the display target position in a pixel unit or a dual port image memory (VRA).
M) A display address for reading drawing data to be displayed on the screen from the serial port (serial DATA) of 30 is generated.

The display timing signals supplied to the CRT display 50 include a horizontal synchronization signal HSYNC and a vertical synchronization signal VSYNC, and the display timing signals supplied to the flat panel display 40 include a horizontal synchronization signal LP and a vertical synchronization signal LPSYNC. There is a signal FP and a shift clock SCK. The generation timings and polarities of the horizontal synchronizing signal LP, the vertical synchronizing signal FP, and the shift clock SCK for the flat panel display 40 are changed according to the specifications of the flat panel display 40.

The memory address bus control circuit 16 is supplied with CP via the system bus interface 12.
The address from U1, the address from the drawing coprocessor 13, and the address from the CRTC controller are selected and supplied to the dual port image memory (VRAM) 30. The memory control circuit 18 has various control signals (Cont) for read / write access to the dual port image memory (VRAM) 30, a clock SCK for controlling data read timing from the serial data port, and an output enable signal SOE. To occur. In addition, the memory control circuit 18 uses the sprite memory 1
9 access control and sprite display timing control.

In the sprite memory 19, sprite data is written in the graphic mode, and fonts are written in the text mode. In this case, the sprite data is 1
Not only one, but a plurality of, for example, four sprite data are written in the sprite memory 19. In the text mode, the code of the text data read from the dual port image memory (VRAM) 30 is supplied to the sprite memory 19 as an index, and the font corresponding to the code is read. This sprite memory 1
9 has a storage capacity of 8 Kbytes. Since each sprite data is 1 Kbyte, 4 Kbytes (1 Kbyte × 4) of the sprite data are used for the sprite data storage area in the graphic mode.

The serializer 20 is a parallel / serial conversion circuit for converting parallel pixel data for a plurality of pixels into pixel units (serial), and in the graphic mode, a dual port image memory (VRAM) 30.
The memory data read from the serial data port (serial DATA) and the sprite data read from the sprite memory 19 are parallel-serial converted, and the font data read from the sprite memory 19 is parallel-serial converted in the text mode.

The latch circuit 21 is for delaying the attribute output timing by the delay time of conversion from code data to font data, and is a dual port image memory (VRAM) in the text mode.
The attribute of the text data read from 30 is held. The foreground / background multiplexer 22 selects one of the foreground color (front color) and the background color (background color) of the attribute in the text mode. This choice is for serializer 2
The value of the font data output from 0 is controlled by "1" (foreground) and "0" (background). The graphic / text multiplexer 23 is for switching between the graphic mode and the text mode. In the graphic mode, the memory data output from the serializer 20 is selected, and in the text mode, the foreground / background multiplexer 22 is selected. Select an output.

The color palette control circuit 24 is for performing color conversion of graphic or text data to generate video data. The color palette control circuit 24 includes a two-stage color palette table. The first color palette table is composed of 16 color palette registers. 6-bit color palette data is stored in each color palette register. The second color palette table is composed of 256 color palette registers. Each color palette register stores 18-bit color data consisting of 6 bits for each of R, G, and B.

In the graphic mode, 8-bit / pixel XGA specification memory data is sent directly to the second color palette table without passing through the first color palette table, where R, G and B are each 6 Converted to color data composed of bits. Also,
The 4-bit / pixel VGA specification memory data is first sent to the first color palette table, where it is converted into 6-bit color data and output. And
To the 6-bit color data, 2-bit data output from the color selection register built in the color palette control circuit 19 is added, whereby a total of 8-bit color data is obtained. After that, the 8-bit color data is sent to the second color palette table, where it is converted into color data of 6 bits for each of R, G, and B.

On the other hand, in the text mode, XG
Text data of both A and VGA can be read through R, R, and R via the first and second two-stage color palette tables.
It is converted into color data composed of 6 bits for each of G and B.

In the XGA graphics mode, there is a direct color mode in which one pixel is composed of 16 bits. In this case, the memory data of 16 bits / pixel does not go through the color palette control circuit 24. Are directly supplied to the CRT video multiplexer 26.

The sprite color register 25 specifies the sprite display color. The sprite color register 25 is provided with eight sprite color registers. Two sprite color registers are assigned to every four sprite data. The CRT video multiplex operation circuit 26 selects the CRT video display output, and outputs the output of the color palette control circuit 24.
Alternatively, direct color output from the serializer 20 is selected, and further video switching and calculation of sprite display are performed. The sprite control circuit 27 uses the CRT video multiplex operation circuit 2 according to the sprite data that is parallel / serial converted by the serializer 20.
6 to control video switching during sprite display.

Flat panel emulation circuit 28
Converts the CRT video output to produce flat video data VD for flat panel display 40.
In this case, the flat video data VD becomes large depending on whether the flat panel display 40 is color display or gradation display. In the case of color, the number of display colors and the panel are different depending on whether they are TFT or STN, and in the case of gray scale display, the number of gray scales or PDP or LCD is different. The data format of the flat video data VD is changed according to the specifications of such a panel. Next, FIG.
A configuration for identifying the specifications of the flat panel display 40, which is a feature of the present invention, will be described with reference to.

As shown in FIG. 2, the interface between the display controller 10 and the flat panel display 40 includes a data line 101, a horizontal synchronizing signal line 102, a shift clock signal line 103, and a vertical synchronizing signal line 104. , Direction control lines 105 are provided.
The data line 101, the horizontal synchronizing signal line 102, the shift clock signal line 103, and the vertical synchronizing signal line 104 are provided conventionally. In this embodiment, the data line 101 is transferred from the video data and the ROM 401. Data line 1 to be shared for status data transfer
01 is used as a bidirectional data line.

Since the data line 101 is used as a bidirectional data line, the display controller 10 is provided with a 3-state output buffer 201 and an input buffer 202, and the flat panel display 40 is provided with an input buffer 402 and a 3-state output. A buffer 403 is provided. The transfer direction of the data line 101 is switched by the direction control line 105.

That is, the signal DI on the direction control line 105
When R is “1”, the 3-state output buffer 201 is active, and the output of the 3-state output buffer 403 becomes high impedance. Therefore, the transfer direction of the data line 101 is the direction from the display controller 10 to the flat panel display 40. Become. This transfer direction is used when the video data VD generated by the flat panel emulation circuit 28 is transferred to the display circuit in the flat panel display 40 via the data line 101, that is, for normal data display.

The signal DIR on the direction control line 105 is "0".
In this case, the output of the 3-state output buffer 201 is high impedance, and the 3-state output buffer 403 is active, so the transfer direction of the data line 101 is from the flat panel display 40 to the display controller 10. This transfer direction is the ROM 401
Status data (STATUS) read from the display controller 10 via the data line 101.
This is used when transferring the data to the inside, that is, at the time of initial setting for determining the specifications of the flat panel display 40.

The horizontal synchronizing signal line 102 is a horizontal synchronizing signal L for a flat panel display generated by the CRT controller 15 of the display controller 10.
P for supplying P to the flat panel display 40, and the status read clock R at the time of initial setting for determining the specifications of the flat panel display 40.
It is used for transferring CK. The status read clock RCK is generated by the CRT controller 15 based on the I / O read signal from the CPU 1, for example. The horizontal synchronizing signal LP and the status read clock RCK are supplied to the selector 203, and the output of this selector 203 is supplied to the horizontal synchronizing signal line 102. The selector 203 selects the horizontal synchronizing signal LP when the signal DIR is "1", and selects the status read clock RCK when the signal DIR is "0". That is, the status read clock RCK is output during the initial setting for determining the specifications of the flat panel display 40, and the horizontal synchronizing signal LP is output during the display operation. This status read clock RCK is stored in the ROM 4
Counter 404 for generating 01 read address
Is supplied to. The counter 404 increments the read address of the ROM 401 according to the number of status read clocks RCK.

The shift clock signal line 103 and the vertical synchronizing signal line 104 are connected to the display controller 10 respectively.
The CRT controller 15 supplies the shift clock SCK and the vertical synchronizing signal FP to the flat panel display 40. The vertical synchronizing signal FP is also used as a reset signal for the counter 404.

Further, the CRT controller 15 of the display controller 10 has a counter 204, a decoder 205, a resolution status register 206, and a color / gradation as a configuration for temporarily holding the status data read from the ROM 401. A plurality of status registers including the status register 207 are provided. The counter 204 counts the number of status read clocks RCK and supplies the count value to the decoder 205. The decoder 205 has status registers 206, 20 according to the count value.
.. are sequentially set to enable. The resolution status register 206 holds status data indicating the resolution read from the ROM 401, and the color / gradation (gray) status register 207 is stored in the ROM 401.
The status data indicating the color / gradation distinction read from is held.

The contents of these status registers are I
The data is read by the CPU 1 through the / O lead or the like, and the specifications of the flat panel display 40 are determined by software. Then, according to the determination result, the generation format (color / gradation) of the video data, the output format (the number of pixels to be simultaneously output, the number of bits per pixel, etc.), the horizontal synchronization signal LP, the vertical synchronization signal FP, the shift clock The timing and polarity of SCK are controlled. As a control method, a plurality of data generation circuits and timing signal generation circuits are provided in advance, the configuration to select the circuit to be used according to the determination result and the parameter according to the determination result are set in the register, and the register contents A configuration in which the output format of the video data and the timing / polarity of the sync signal are variably set according to the above can be used. Next, the operation of reading the status data from the ROM 401 will be described with reference to the timing chart of FIG.

At the time of initial setting for determining the specifications of the flat panel display 40, the signal DIR is at "0" level, and the 3-state output buffer 201 for outputting the video data VD is in a high impedance state. , 3-state output buffer 4 for outputting status data read from the ROM 401
02 becomes active. In this state, the status read clock RCK is sequentially generated. The counters 204, 40 are synchronized with the status read clock RCK.
The count value of 4 is sequentially counted up as "0", "1", "2", ....

From the ROM 401, the resolution status data, the color / gradation status data, ... Are sequentially read according to the count values “0”, “1” ... Of the counter 404, which is displayed via the data line 101. It is transferred to the controller 10. When the count value of the counter 204 is “0”, the resolution status register 206
Is set to the enable state, the resolution status data is latched in the resolution status register 206 when the register latch clock is input. .. When the count value of the counter 204 is "1", the color / gradation status register 207 is set to the enable state, so that the color / gradation status data is changed to color / gradation status data when the register latch clock is input. It is latched in the gradation status register 207. In this way, various status data in the ROM 401 are sent to the display controller 10 via the data line 101 and stored in the corresponding registers.

These status registers 206 and 207
Is read by the CPU 1, and the specification of the flat panel display 40 is determined by this. Then, the display timing and the data output format are controlled according to the determination result.

As described above, in this embodiment, the ROM 401 is provided in the flood panel display 40, and various status data necessary for display control is stored in the ROM 401, so the status data is read out. As a result, the specifications of various flat panel displays can be automatically determined, and display control can be performed according to the specifications of various flat panel displays. Further, since the data line 101 to which the video data is transferred is a bidirectional data line and the control information is read by switching the direction of the bidirectional data line, the display controller 10 is read.
Also, the number of signal lines between the flat panel display 40 and the flat panel display 40 does not increase. Therefore, it is possible to determine the flat panel display with a simple configuration.

[0050]

As described above, according to the present invention, it is possible to automatically determine the specifications of various flat panel displays with a simple structure, and perform display control according to the flat panel display used. You can

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of a display control system according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of an interface section between a display controller and a flat panel display in the embodiment.

FIG. 3 is a timing chart illustrating an operation of reading status data from a ROM provided in the flat panel display in the embodiment.

[Explanation of symbols]

1 ... CPU, 4 ... Display control system, 10 ... Display controller, 15 ... CRT controller, 40 ... Flat panel display, 101 ... Data line, 206
... resolution status register, 207 ... color / gradation status register.

Claims (1)

[Claims] 1. A flat panel display, a memory device provided in the flat panel display for storing various control information necessary for display control of the flat panel display, display data to be displayed on the flat panel display, and its display data. A display control device that generates a display timing control signal for controlling display timing; and a flat panel display that is provided in the display control device and that generates a read control signal for reading the control information from the memory device. Supplying means to the memory device, and the video data generated from the display control device or the control information read from the memory device, which is provided between the flat panel display and the display control device. Bidirectional data line, Transfer direction switching means for switching the data transfer direction of the bidirectional data line so that the data is transferred from the display control device to the flat panel display and the control information is transferred from the flat panel display to the display control device. A display control system comprising: