JPH0659652A - Display control device - Google Patents

Abstract

PURPOSE:To improve the efficiency of performance evaluation by enabling video data to be transferred to a host CPU. CONSTITUTION:The pixel position of inspection object on the display screen designated by CPU is retained by an inspection object pixel address register 101 and the position is compared with the address of display object pixel position generated by a pixel address generation circuit 102. When conformity of address is detected by a comparison circuit 103, the video data corresponding to the inspection object pixel position is subjected to latch by a latch circuit 105. Consequently, the video data is read out according to requirement of I/O lead and the like from CPU and thereby evaluation of video data is carried out easily by program control and the like in a computer system.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device for a portable computer, and more particularly to a display control device having a video data check function.

[0002]

2. Description of the Related Art Recently, XGA (eXtended Gr)
A variety of high-resolution graphics display controllers, such as the Apics Array) specification, have been developed.
The evaluation of this type of display controller has traditionally been
This is done by visually confirming the data displayed on the CRT or the like, or by using a circuit such as a screen buffer for taking the video data into the memory.

However, the visual check takes time, and particularly the evaluation of the high resolution graphics display requires a huge amount of time. In addition, when a screen buffer is used, a test-dedicated board is required, which increases the cost of the display controller and is unsuitable for evaluating mass-produced products.

[0004]

Conventionally, the video data is checked visually or using a screen buffer, which has the drawbacks that it takes a lot of time for evaluation and the cost is increased. An object of the present invention is to provide a display control device which can read generated video data and transfer it to a host CPU, and can perform performance evaluation at a low cost and at a sufficiently high speed.

[0005]

According to the present invention, in a display control device of a computer system,
A means for holding a pixel position to be inspected on the display screen designated by the CPU of the computer system;
Address generating means for sequentially generating pixel addresses indicating pixel positions to be displayed in pixel units in synchronization with display timing; and video data converting means for converting display data stored in the image memory into video data in pixel units. Means for supplying video data output from the video data converting means to a display, comparing means for comparing the pixel position of the inspection object with the pixel address, and video data output from the video data converting means, The comparison means includes a latch means for latching the video data when an address match is detected, and a means for reading the video data latched by the latch means in response to a request from the CPU.

In this display control device, when the pixel position to be inspected on the designated display screen matches the pixel position to be displayed, the video data corresponding to the pixel position to be inspected is latched by the latch means. The latched video data is read in response to a request from the CPU. Therefore, when the pixel position to be inspected on the display screen is designated, the video data corresponding to the pixel position can be read from the display control device.
If the display screen does not change, the same video data corresponding to the designated pixel position to be inspected can be read. Therefore, evaluation of the video data generated by the display controller by program control or the like in the computer system (eg, whether the data written in the VRAM is garbled, whether it is written in the correct pixel position, etc.) Etc.) can be performed easily, and performance evaluation can be performed at a low cost and at a sufficiently high speed as compared with evaluation by visual inspection or a screen buffer.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the overall configuration of a display control device according to an embodiment of the present invention. The display control system 4 is, for example, an XGA (eXtended) having a display mode of 1024 × 768 dots and simultaneous display of 256 colors.
This is a display control system of the Graphics Array) specification and is a system bus 3 of a portable computer.
Connected to. The display control system 4 includes a flat panel display 40 that is standard equipment in a portable computer body and a color CRT that is optionally connected.
Display control is performed on both the displays 50.

The display control system 4 includes a display controller 10 and a dual port image memory (VRA).
M) 30 and a DAC (D / A converter) 35 are provided. These display controllers 10,
Dual port image memory (VRAM) 30, and D
The AC 35 is mounted on a circuit board (not shown).

The display controller 10 is an LSI realized by a gate array and is a main part of the display control system 4. This LSI is, for example, a display controller chip (model number ***
**) is applicable. This display controller 1
0 uses the dual port image memory (VRAM) 30 and the DAC 35 in accordance with the instruction from the CPU 1,
Display control for the flat panel display 40 and the color CRT display 50 is executed. Further, the display controller 10 functions as a bus master and can directly access the system memory 2.

Dual port image memory (VRAM) 3
0 has a serial port (serial DATA) used for system access and a parallel port (DATA) for random access. The serial port (serial DATA) is used to read data for refreshing the display screen, and the parallel port (DA).
TA) is used to update the display data. The dual-port image memory (VRAM) 30 is composed of a plurality of dual-port DRAMs and has 1 Mbyte to 4 Mbytes.
It has a storage capacity of M bytes. Display data to be displayed on the flat panel display 40 or the color CRT display 50 is drawn on the dual port image memory (VRAM) 30.

In this case, drawing data of XGA specifications created by an application program or the like conforming to XGA specifications is stored in the dual port image memory (VRAM) 30 by the packed pixel method. The packed pixel system is a color information mapping system in which one pixel is represented by consecutive bits on a memory, and for example, a system in which one pixel is represented by 1, 2, 4, 8 or 16 bits is adopted. On the other hand, the VGA specification drawing data is created by a conventional application program or the like conforming to the VGA specification, and is drawn in the dual port image memory (VRAM) 30 by the memory plane method.
This memory plane method is a method in which a memory area is divided into a plurality of planes designated by the same address and color information of each pixel is assigned to these planes. For example, 4
If you have planes, one pixel is 1 for each plane.
It is represented by a total of 4 bits of data.

A dual port image memory (VRA
Text data is also stored in M) 30. The text data for one character has a total size of 2 bytes consisting of an 8-bit code and an 8-bit attribute in both XGA and VGA specifications. The attribute is composed of 4-bit data that specifies the foreground color and 4-bit data that specifies the background color.

The DAC 35 converts the CRT video data generated by the display controller 10 into analog R, G, B signals and supplies them to the CRT display 50.

The display controller 10 includes a register control circuit 11, a system bus interface 12,
Drawing coprocessor 13, memory data bus control circuit 14, CRT controller (CRTC) 15, memory address bus control circuit 16, memory control circuit 18, sprite memory 19, serializer 20, latch circuit 21,
Foreground / background multiplexer 22,
It is composed of a graphic / text multiplexer 23, a color palette 24, a sprite color register 25, a CRT video multiplexer 26, a sprite control circuit 27, and a flat panel emulation circuit 28.

The register control circuit 11 receives an address and data from the system bus 3 via the system bus interface 12, decodes the address, and performs read / write control on various registers designated by the decoding result. The system bus interface 12 controls the interface with the host system via the system bus 3, and supports a bus interface conforming to various specifications such as ISA, EISA, Micro Channel, and local bus.

The drawing coprocessor 13 is responsive to the support from the CPU 1 and has a dual port image memory (VRA).
M) provides various drawing functions for the drawing data in 30. Image block transfer, line drawing, area filling, logical / arithmetic operation between pixels, screen cutout, map mask, X -It has a memory management function by addressing at the Y coordinate and paging.
The drawing coprocessor 13 includes a VGA / XGA compatible data operation circuit 131 and a two-dimensional address generation circuit 13.
1 and a paging unit 133 are provided.

The data operation circuit 131 performs data operations such as shift, logical arithmetic operation, bit mask, color comparison, and the like, and also VGA compatible BITBLT (Bi).
It also has a tBlock Transfer function.
The two-dimensional address generation circuit 132 generates an XY two-dimensional address for accessing a rectangular area or the like. Also, 2
The dimensional address generation circuit 132 also performs area checking and conversion processing into a linear address (real memory address) using segmentation or the like. The paging unit 133 is for supporting the same virtual memory mechanism as the CPU 1, and when paging is valid, it converts the linear address created by the two-dimensional address generation circuit 132 into a real address by paging. Further, when paging is invalid, the linear address becomes the real address as it is. This paging unit 133 is used for paging.
LB (Translation Lookaside B)
is provided.

The memory data bus control circuit 14 is for controlling the data bus of the parallel data port (DATA) of the dual port image memory (VRAM) 30, and has four maps of source, pattern, mask and destination. It has a buffer for accessing data collectively in page mode. This buffer also functions as a write data buffer.

The CRT controller 15 has various display timing signals (horizontal synchronization signal, vertical synchronization signal) for displaying a screen on the flat panel display 40 or the CRT display 50 at a high resolution (for example, 1024 × 768 dots) that conforms to the XGA specifications. XGA for generating signals, etc.
Display timing signals (horizontal sync signal, vertical sync signal, etc.) for displaying the screen on the flat panel display 40 or the CRT display 50 at a medium resolution (for example, 640 × 460 dots) that meets the VGA specifications for the CRT. It has a CRTC for VGA that generates These display timing signals are generated using a horizontal / vertical counter provided in the CRT controller 15. Further, the CRT controller 15 synchronizes with the display timing for XGA or VGA, and an XY pixel address indicating a coordinate position on the display screen corresponding to the display target position in a pixel unit or a dual port image memory (VRAM). ) 30 serial ports (serial D
The display address for reading the drawing data to be displayed on the screen from the ATA) is generated.

Further, the CRT controller 15 is a CP
When the coordinate position on the display screen is designated by U1, it has a function of holding the CRT video data corresponding to the coordinate position and reading the video data according to a request from the CPU 1. The CRT video data is generated by the serializer 20 and the color palette control circuit 24 described later. In this way, the CRT video data displayed at the coordinate position on the specified display screen is displayed as CP.
The function of reading out to U1 is a feature of the present invention, and a specific configuration for realizing this function will be described later with reference to FIG.

The memory address bus control circuit 16 is supplied with CP via the system bus interface 12.
The address from U1, the address from the drawing coprocessor 13, and the address from the CRTC controller are selected and supplied to the dual port image memory (VRAM) 30. The memory control circuit 18 includes various control signals (Cont) for read / write access to the dual port image memory (VRAM) 30, a clock SCK for controlling the timing of reading data from the serial data port, and an output enable signal SOE. To occur. In addition, the memory control circuit 18 uses the sprite memory 1
9 access control and sprite display timing control.

Sprite data is written to the sprite memory 19 in the graphic mode, and fonts are written in the text mode. In this case, the sprite data is 1
Not only one, but a plurality of, for example, four sprite data are written in the sprite memory 19. In the text mode, the code of the text data read from the dual port image memory (VRAM) 30 is supplied to the sprite memory 19 as an index, and the font corresponding to the code is read. This sprite memory 1
9 has a storage capacity of 8 Kbytes. Since each sprite data is 1 Kbyte, 4 Kbytes (1 Kbyte × 4) of the sprite data are used for the sprite data storage area in the graphic mode.

The serializer 20 is a parallel / serial conversion circuit that converts parallel pixel data for a plurality of pixels into pixel units (serial), and in the graphic mode, a dual port image memory (VRAM) 30.
The memory data read from the serial data port (serial DATA) and the sprite data read from the sprite memory 19 are parallel / serial converted, and the font data read from the sprite memory 19 is parallel / serial converted in the text mode.

The latch circuit 21 is for delaying the attribute output timing by the delay time of conversion from code data to font data, and is a dual port image memory (VRAM) in the text mode.
The attribute of the text data read from 30 is held. The foreground / background multiplexer 22 selects one of the foreground color (front color) and the background color (background color) of the attribute in the text mode. This choice is for serializer 2
The value of the font data output from 0 is controlled by "1" (foreground) and "0" (background). The graphic / text multiplexer 23 is for switching between the graphic mode and the text mode, selects the memory data output from the serializer 20 in the graphic mode, and selects the memory data of the foreground / background multiplexer 22 in the text mode. Select an output.

The color palette control circuit 24 is for performing color conversion of graphic or text data to generate video data. The color palette control circuit 24 includes a two-stage color palette table. The first color palette table is composed of 16 color palette registers. 6-bit color palette data is stored in each color palette register. The second color palette table is composed of 256 color palette registers. Each color palette register stores 18-bit color data composed of 6 bits for each of R, G, and B.

In the graphic mode, the memory data of the XGA specification of 8 bits / pixel is directly sent to the second color palette table without passing through the first color palette table, and the R, G and B are each 6 Converted to color data composed of bits. Also,
The 4-bit / pixel VGA memory data is first sent to the first color palette table, where it is converted into 6-bit color data and output. And
To this 6-bit color data, 2-bit data output from the color selection register built in the color palette control circuit 19 is added, whereby a total of 8-bit color data is obtained. After that, the 8-bit color data is sent to the second color palette table, where it is converted into color data of 6 bits for each of R, G, and B.

On the other hand, in the text mode, XG
Text data of both A and VGA can be read via R, R, and R via the first and second two-stage color palette tables.
It is converted into color data composed of 6 bits for each of G and B.

In the XGA graphics mode, there is a direct color mode in which one pixel is composed of 16 bits. In this case, the memory data of 16 bits / pixel is the color palette control circuit 24.
Directly to the CRT video multiplexer 26 without going through.

The sprite color register 25 specifies the sprite display color. The sprite color register 25 is provided with eight sprite color registers. Two sprite color registers are assigned to every four sprite data. The CRT video multiplex operation circuit 26 selects the CRT video display output, and outputs the color palette control circuit 24.
Alternatively, a direct color output from the serializer 20 is selected, and video switching and calculation of sprite display are performed. The sprite control circuit 27 uses the CRT video multiplex operation circuit 2 in accordance with the sprite data that is parallel / serial converted by the serializer 20.
6 to control video switching during sprite display.

Flat panel emulation circuit 28
Converts the CRT video output to produce flat video data for flat panel display 40. Figure 2
1 shows an example of a configuration for realizing the video data reading function of the CRT controller 15, which is a feature of the present invention.

As shown in the figure, the CRT controller 15 includes a pixel address register 101 to be inspected, a pixel address generating circuit 102, a comparing circuit 103, video data latch circuits 104 and 105, a status flag flip-flop 106, multiplexers 108 and 10.
9, a selection signal holding register for the multiplexers 108 and 109, and an AND gate 110 are provided.

Inspected pixel address register 101
Is for holding a pixel address indicating a pixel position to be inspected on the display screen.
Specify the dot. The pixel address to be inspected is given by the CPU 1, for example, 2
The pixel position to be inspected is specified by the dimension (X, Y) address.

The pixel address generation circuit 102 is an address generation circuit which sequentially generates pixel addresses indicating the positions of display target pixels in synchronization with the display timing.
The pixel address is indicated by, for example, a two-dimensional (X, Y) address.

The comparison circuit 103 compares the pixel address set in the inspection target pixel address register 101 with the pixel address generated by the pixel address generation circuit 102, and outputs a latch signal when they match (see FIG. 5). . This latch signal is applied to the multiplexer 10
8 and is also supplied to the latch circuit 104 in synchronization with the clock signal (FIG. 5). Latch circuit 104
Is a delay latch circuit, which delays the latch signal from the comparison circuit 103 by a predetermined amount and then the multiplexer 108
Output to.

The video data latch circuit 105 latches either the video data output from the serializer 20 or the output from the palette control circuit 24. As mentioned above, 1
The drawing data of 6 bits / pixel or more is directly used as the video data in the DAC 3 without using the palette control circuit 24.
5 (direct color mode). Therefore, the latch circuit 105 outputs the output of the serializer 20 to the delay flip-flop 1 in the direct color mode.
Latch via 11.

On the other hand, when the number of display colors is small (8 bits /
Pixels or less) are color-converted by the color palette built in the palette control circuit 24 to be video data. Therefore, the video data latch circuit 105 is
In the case of A specification drawing data or XGA specification drawing data other than the direct color mode, the output of the palette control circuit 24 is latched with the video data output via the delay flip-flop 112.

As described above, the delay amount of video data differs depending on whether the latch circuit 105 latches the video data from the serializer 20 or the video data from the palette control circuit 24. Therefore, the latch signal supplied to the latch circuit 105 also needs to be delayed in synchronization with the delay of the video data. Therefore, when the latch circuit 105 latches the video data from the serializer 20, the multiplexer 108 operates in the comparison circuit 10
When the latch circuit 105 latches the video data from the palette control circuit 24, the multiplexer 108 is configured to select the latch signal output from the latch circuit 104.

The register 107 is a multiplexer 108.
And hold the select signals to 109. That is, in the register 107, the data indicating the drawing data of 16 bits / pixel or more or the data indicating the drawing data of 8 bits / pixel or less is written by the I / O write signal from the CPU 1. If the selection signal supplied from the register 107 is data indicating that it is drawing data of 16 bits / pixel or more, the multiplexer 108
Is the AND gate 11 that receives the latch signal from the comparator 103.
When the data is output to 0 and indicates that the drawing data is 8 bits / pixel or less, the latch signal from the latch circuit 104 is output. The AND gate 110 supplies the latch signal output from the multiplexer 108 to the latch circuit 105 in synchronization with the clock signal (see FIG. 5).

The multiplexer 109 has a register 107.
When the selection signal supplied from is data indicating that the drawing data is 16 bits / pixel or more, the video data obtained by delaying the output of the serializer 20 by the F / F 111 is selected, and the drawing data of 8 bits / pixel or less is selected. In the case of data indicating that, the video data in which the output of the palette control circuit 24 is delayed by the F / F 112 is selected.

The video data latched by the video data latch circuit 105 is transferred to the system bus interface 1
It is output to the multiplexer 113 in the No. 2. In the flip-flop (F / F) 106, the video data output from the latch circuit 105 is input to the multiplexer 1 (see FIG. 5).
A status flag indicating that the data has been captured in 13 is held. (See FIG. 5) F / F 106 is AND gate 11
Set by the latch signal output from 0, CPU
I / O write signal (IO
W) (see FIG. 7). CPU1
Referring to this status flag, the multiplexer 11
If 3 shows that the video data has been captured,
The I / O read signal and the address decode signal are output as selection signals to the multiplexer 113, and the video data is read via the system bus 3. At this time, as shown in FIG. 7, the CPU 1 polls the F / F 106 to read the status information, and when the status flag becomes “1”, the video data is transferred to the memory 2 or the HDD, for example.
Save to 60. This video data is read at a rate of, for example, 1 pixel (the X coordinate position of the pixel is the same) for 1 horizontal line.

For example, as shown in FIG.
To control the display of a high-resolution screen of 1024 × 768 dots of A specification, the pixel address generation circuit 10
2 shows the data display period (H
-X-address (XGA X-ADDR) indicating the pixel position of the display target in synchronization with the display timing at which 1024-dot video data is output in (DISPLAY)
= 0, 1, 2, ..., 1023) and Y address (Y = 0, Y
, 1, ... Y = 767) is generated.

Here, assuming, for example, that the pixel position to be inspected (X, Y) = (400, 200) is specified, the Y address generated by the pixel address generation circuit 102 is (Y = 200). At some time, when the X address becomes (XGA X-ADDR = 400), the comparison circuit 103 outputs a latch signal. Then, the inspection target pixel position (X, Y) = (400, 200)
The video data corresponding to is latched by the latch circuit 105.

FIG. 6 is a flow chart showing the control when the CPU 1 takes in the video data. Step 13
In 1, the CPU 1 holds a pixel address indicating a pixel position to be inspected on the display screen. Step 123
At 1, the CPU 1 reads the status flag held in the F / F 106, and determines whether the status flag read in step 125 is “1”. If the status flag is "1", the pixel data is read in step 127 and saved in the memory 2 or HDD 60 in step 129. In step 131, the CPU 1 determines whether all pixel data to be inspected have been read. If all reads have not been completed, the CPU 1 proceeds to step 13
In step 3, the next address + offset (the same X coordinate position one horizontal line below) is calculated, and steps 121 to 13 are executed.
Repeat 1. When it is determined in step 131 that reading of all pixel data has been completed, the CPU 1 compares the saved data with the expected value in step 135, and outputs the comparison result as a report in step 137.

As described above, in this embodiment, C
The comparison circuit 10 indicates that the pixel position to be inspected and the pixel position to be displayed on the display screen designated by PU1 match.
3, the video data corresponding to the pixel position to be inspected is latched by the latch circuit 105. Therefore, by reading the latched video data in response to a request such as an I / O read from the CPU 1, ,
The video data can be easily evaluated by program control or the like in the computer system.

In this embodiment, the case where the address designating the pixel position to be inspected is a two-dimensional XY address has been described, but the pixel position to be inspected is designated by a one-dimensional linear address. Of course, it is also good. In this case, the pixel address generation circuit 102
May be configured to start from 0 at the start of display of each frame, count up by 1 for each pixel, and count up to 1024 × 768 dots.

[0046]

As described above, according to this pawl,
Read the generated video data and send it to the host CPU
Therefore, it becomes possible to evaluate the performance of video data at a low cost and at a sufficiently high speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of a display control device according to an embodiment of the present invention.

FIG. 2 is a diagram showing an extracted configuration of a video data reading function of the embodiment.

FIG. 3 is a diagram showing an example of an inspection target pixel position on a display screen designated by a CPU in the embodiment.

FIG. 4 is a timing chart showing generation timing of a pixel position address of a display target in the embodiment.

FIG. 5 is a waveform diagram of signals at various parts of the configuration shown in FIG.

FIG. 6 shows pixel data output to the system bus as C
Flowchart showing control when PU reads;

FIG. 7 is a waveform diagram of an I / O write signal and an I / O read signal output from the CPU 1.

[Explanation of symbols]

1. ． ． CPU, 4. ． ． Display control system, 1
0. ． ． Display controller, 15. ． ． CRT
Controller, 101. ． ． Inspection target pixel address register, 102. ． ． Pixel address generation circuit, 1
03. ． ． Comparison circuit, 105. ． ． Latch circuit.

Claims (12)

[Claims] 1. A display control device for a computer system, means for holding an inspection target pixel position on a display screen designated by a CPU of the computer system, and a pixel address indicating the display target pixel position in synchronization with display timing. Address generating means for sequentially generating pixel data in units of pixels, video data converting means for converting display data stored in the image memory into video data in pixel units, and video data output from the video data converting means for display. Supplying means, comparing means for comparing the pixel position to be inspected with the pixel address, video data output from the video data converting means are input, and when the comparing means detects a match of the addresses, Latching means for latching video data, And a means for reading out the video data latched by the latch means in response to a request from the CPU. 2. The display control device according to claim 1, wherein the display control device is configured by a one-chip LSI. 3. The display control device according to claim 1, further comprising means for transferring the video data read by said reading means to a host CPU. 4. The address generating means is a VGA (Vi
deo Graphics Array) or XGA
(Extended Video Graphics
2. A means for generating a pixel address in synchronism with a display timing for an array) is included.
The display control device described. 5. The latch means includes means for latching video data in direct color mode, drawing data of VGA specifications, or video data corresponding to drawing data of XGA specifications excluding direct color mode. Item 3. The display control device according to item 1. 6. The display control according to claim 1, wherein the latching means includes means for latching n bits / pixel (n is a positive integer) video data or 2n bits / pixel video data. apparatus. 7. A system bus and a central processing unit (CP)
U); memory means for storing video data read by the CPU via a system bus; and a display control device, the pixel position being inspected on the display screen designated by the CPU of the computer system. Holding means, address generating means for sequentially generating pixel addresses indicating pixel positions to be displayed in pixel units in synchronization with display timing, video for converting display data stored in the image memory into video data in pixel units. Data conversion means, means for supplying the video data output from the video data conversion means to the display, comparison means for comparing the pixel position to be inspected with the pixel address, and video output from the video data conversion means Data is input, and the comparison means The display control device includes a latch means for latching the video data when a match is detected, and a means for reading the video data latched by the latch means in response to a request from the CPU. A computer system characterized by the above. 8. The apparatus according to claim 7, further comprising means for comparing the read video data with an expected value.
The described computer system. 9. The computer system according to claim 7, wherein the display control device comprises a one-chip LSI. 10. The address generating means is a VGA (V
video graphics array) or XG
A (Extended Video Graphics)
8. The computer system according to claim 7, further comprising means for generating a pixel address in synchronization with a display timing for an array. 11. The latch means includes means for latching video data in direct color mode, drawing data of VGA specifications, or video data corresponding to drawing data of XGA specifications excluding direct color mode. Item 7. The computer system according to Item 7. 12. The latch means comprises n bits / pixel (n is a positive integer) of video data or 2n bits / pixel.
8. The computer system of claim 7, including means for latching pixel video data.