JPH08286649A - Display device - Google Patents

Abstract

PURPOSE: To provide a low cost display device by using relatively low cost DRAM for an image memory. CONSTITUTION: This device is provided with a graphic controller 5, a display controller 20, an image memory 22 and a visible indicator 7, and the display controller 20 has a stack structure 26 consisting of plural flip-flop stages in image data transmitting part 23 outputting image data inputted from image memory to the visible indicator 7, and is also constituted so that transmission of the image memory 22 to the stack structure 26 is performed by cycle-stealing an access timing of the graphic controller and the image memory 22.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device for visually displaying characters and figures, and more particularly to the transfer of image data from a display controller.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing a display device for displaying characters and graphics on the screen of a visible display such as a liquid crystal display. Such a display device is a central processing unit (hereinafter, "CPU").
Say. ) ROM3, R on bus line 2 connected to
The AM 4, the graphic controller 5, and the display controller 6 are connected to each other, and the display controller 6 is connected to the visual display 7 and the image memory 8. The visual display 7 stores the image data written in the image memory 8. It is configured to be read out and displayed.

As is well known, the graphic controller 5 generates control signals for the visual display 7, such as horizontal and vertical blanking interval signals, write and read signals to the image memory 8 and image data, and outputs them to the display controller 6. To do. The display controller 6 receives the signal generated by the graphic controller 5 at the timing generation unit 10, and outputs the access timing between the graphic controller 5 and the image memory 8 and the data in the image memory 8 to the output unit 13 to the visual display 7. The read timing and the output timing to the visual display 7 are generated and output to the access unit 12, the address generation unit 11, and the image data output unit for the image memory 8.

In the case of this display device, the visual indicator 7 is
It is composed of two upper and lower screens, and image data in the image memory 8 is simultaneously displayed from a predetermined position on both upper and lower screens. The image memory 8 provided corresponding to the screen of the visual display 7 is composed of a plurality of dual port memories.

In such a display device, the image data in the image memory 8 is read out, the graphic controller 5 performs appropriate image processing, and the image data is written in the image memory 8 again.
The graphic controller 5 frequently accesses the image memory 8 such as newly creating image data by the graphic controller 5 and writing it in the image memory 8. On the other hand, since the visual display 7 displays the image data at the display timing, it is required to read the image data from the image memory 8 at the display timing.

As described above, the dual port memory is used as the image memory 8 in order to respond to both accesses and requests. The operation of the display controller 6 in this case is as shown in FIG.
The head address of the image memory 8 to be output to the visual display 7 is input from the graphic controller 5 at an appropriate timing according to the command signal from the graphic controller 5, and the address is set in the image memory 8.

Correspondence of the image memory 8 to the visual display 7 is sequentially read from the set address in accordance with the display timing (timing of the three columns from the top of FIG. 6), and the multiplexer (MUX) of the output unit 13 Output to the visual display 7 via the. Then, in parallel with this reading, the graphic controller 5 and the image memory 8 are accessed.
In addition, in FIG. 6, the visual display 7 is composed of two upper and lower screens, and two screens are simultaneously displayed.
The address set of the image memory 8 for the screen (timing in the upper two columns in FIG. 6) and the output timing of image data for the upper and lower two screens (timing in the lowermost column in FIG. 6) are shown.

[0008]

As described above, the display device using the dual port memory as the image memory is extremely expensive, and as a result, the visual display device is expensive.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a visual display device that enables a relatively inexpensive DRAM to be used as an image memory and has a low cost.

[0010]

The above object of the present invention is to provide a display device comprising a graphic controller, a display controller, an image memory and a visual display device, wherein the display controller provides image data from the image memory to the visual display device. The output section for outputting to the display has a stack structure composed of a plurality of stages of flip-flops, and the transfer of the image data of the image memory to the stack structure is cycle stealed at the access timing between the graphic controller and the image memory. This can be achieved by providing a display device characterized by being performed by the following.

[0011]

According to the above-mentioned structure of the present invention, the display timing is carried out by the cycle steal of the drawing timing, and the transfer of the image data to the visual display is of a flip-flop stack (queue) structure. Therefore, even if a relatively low-cost RAM is used as the image memory, the waiting time for the access between the graphic controller and the image memory is shortened, and the high-speed transfer of the image data to the visual display is sufficiently supported. be able to.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. In addition, the same reference numerals are given to common portions throughout the drawings.

FIG. 1 is a block circuit diagram of a visual display device according to an embodiment of the present invention, and FIG. 2 is a block diagram of an image (including character) data transfer section to a visual display device of the display controller of FIG. It is a block circuit diagram. In FIG. 1, 1 is CP
U and 2 are bus lines connected to the CPU 1, and the ROM 3, RAM 4, graphic controller 5, and display controller 20 are connected to the bus line 2, and
The visual display 7 and the image memory 22 are connected to the display controller 20.

CPU 1 and RO connected to bus line 2
The system including the M3, the RAM 4, and the graphic controller 5 mainly functions at the time of processing image data and the like, and is the same as a known system, and a detailed description thereof will be omitted here. The visual display 7 is configured to operate based on a control signal generated by the graphic controller 5 and the display controller 20 and receive and display the image data written in the image memory 22 to display the image data.

As in the conventional case, the graphic controller 5 generates control signals for the visual display 7, such as horizontal and vertical blanking interval signals and write / read command signals to the image memory 8, and at the same time, the visual display 7 displays. Image data to be displayed is generated and output to the display controller 20.

The display controller 20 includes a timing generation unit 25, a display address generation unit 24, an image memory access unit 21, and an image data transfer unit 23, and the timing generation unit 10 receives the signal generated by the graphic controller 5. And forms an operation timing signal for each unit and outputs it to each unit.

Here, the timing generation unit 25 manages the access state between the graphic controller 5 and the image memory 22 (hereinafter referred to as "drawing timing" in this specification), and the graphic controller 5 is managed.
The image memory 22 in the free space between the image memory 22 and
, A timing signal for performing so-called cycle steal transfer for transferring one memory cycle to the image data transfer unit 23.

That is, in this embodiment, the visual indicator 7
Is composed of upper and lower two screens, and one data is formed with 16 bits for one screen. Timing of reading the one data from the image memory 22 and transferring to the image data transfer unit 23 (hereinafter, in this specification Is referred to as "display timing", but is not limited to 16 bits.) A signal is generated. The screen is not limited to the two-screen configuration.

FIG. 4 shows the relationship between the drawing timing and the display timing. 4A is a display timing for the upper screen, FIG. 4B is a display timing for the lower screen,
(C) drawing timing, (d) display (high level)
Drawing (low level) status is shown, and (e) shows the output state of the multiplexer (MUX) of the image data transfer unit 23, respectively.

The display address generator 24 is connected to the bus line 2 for address, data and read / write signals of the CPU 1, and the CPU 1 sets the display start address of the screen to be displayed. Further, the address of the image memory 22 is generated based on the timing signal from the timing generation unit 25 and the input display start address and is output to the memory access unit 21 to read the image data of the image memory 22 or the data from the CPU 1. Write.

The memory access unit 21 is connected to the bus line for address, data, etc. of the graphic controller 5 and reads out the image data of the image memory 22 based on the timing signal of the timing generation unit 25 and outputs it to the graphic controller 5. Alternatively, the data writing from the graphic controller 5 is performed, and the image data read based on the timing signal of the timing generation unit 25 is output to the image data transfer unit 23.

The image memory 8 is a DRAM in this embodiment.
And is connected to the memory access unit 21.
Further, the visual display 7 is composed of two upper and lower screens of 640 dots × 240 dots in this embodiment, and the image data of the image memory 22 connected to the image data transfer unit 23 and read by the memory access unit 21 is an image. It is sent and displayed via the data transfer unit 23.

The image data transfer unit 23 of the display controller 20 has a stack (queue) structure 26 consisting of a plurality of stages of flip-flops. In this embodiment, as shown in FIG. To 4 and F.
It has a two-stage stack (queue) structure of F5 to F8, and the display data is transferred at the timing shown in FIG.

The flip-flops (FF) 1 to F.F. F8 two-stage stack (queue) structure and FIG.
CLK0 is a clock and UT
0 is the image data for the upper screen of the image memory 22 (D1 to 1
5) to Flip Flop (FF) 1 and FF. The timing signal LT0 to be latched in F2 is the image data for the lower screen of the image memory 8 (D0 to 15). F3 and F.I. It is a timing signal to be latched in F4. This timing signal is synchronized with the above-mentioned display timing signal.

B TO is F. F1 and F. F3, that is, the lower 8-bit image data (D0 to 7) of the upper and lower screens is set to F.F. F5 and F. Timing signal to be latched in F7,
AT0 is F.O. F2 and F. F4, the top 8 of the upper and lower screens
The image data (D8 to 15) of the bit is the F. F6
And F. This is a timing signal to be latched in F8.

F. F1 to F. Each of F8 operates at the rising edge of the timing signal. Also, ST0 and S
T1 is a timing signal that forms the output logic of the multiplexer MUX.

The image data (D0 to 15) for the upper screen of the image memory 22 is transferred to the flip-flop (FF) 1 and FF. The timing signal UT0 latched in F2 is synchronized with the end of the upper screen display access timing of the image memory 22 every 8 clocks CLK0, and the image memory 22 also receives the timing signal UT0.
The image data (D0 to 15) for the lower screen of F. F3 and F.I. The timing signal LT0 latched in F4 is generated every 8 clocks CLK0 in synchronization with the end of the upper screen display access timing of the image memory 22, and there is a difference of 4 clocks between UT0 and LT0. Has been

BT0 is generated every eight clocks CLK0 from the clock CLK0 next to LT0, and AT0 is generated every eight clocks CLK0 two clocks CLK0 after BP0. ST0 is high level for 2 clocks CLK0 from the clock CLK0 next to BT0, high level for the next 2 clocks CLK0 and 2 clocks CLK
High and low are repeated every 0, and ST1 is high level of ST0 and low level period High level Next high level of ST0 and low level period Low level and 4 clocks CLK0
High and low are repeated every time.

In the visual display device having the image data transfer section 23 driven as described above, the visual display 7
The multiplexer (MUX) output of the image data transfer unit 23 is output to the upper screen data U_D0 to 3 and the lower screen data L_D0 to 0 as shown in the bottom of FIGS.
3, upper screen data U_D4 ~ 7 and lower screen data L_D4
~ 7, upper screen data U_8 ~ 11 and lower screen data L_D
8 to 11, upper screen data U_D12 to 15 and lower screen data L_D12 to 15, upper screen data U_D0 to 3 and lower screen data L_D0 to 3 ...

The graphic controller 5 and the image memory 22 are accessed in parallel with the transfer timing period of the image data. The number of bits of one data, the number of flip-flop stages, and the number of screen configurations can be appropriately determined according to the scale of the visual display device.

[0031]

As described above, according to the present invention, the display timing is cycle steal of the drawing timing, and the transfer of the image data to the visual display is of the flip-flop stack (queue) structure. . Therefore, even if a low-cost DRAM is used as the image memory,
It is possible to provide a low-cost visual display device which can shorten the waiting time for access between the graphic controller and the image memory and can sufficiently cope with high-speed transfer of image data to the visual display device. it can.

[Brief description of drawings]

FIG. 1 is a block circuit diagram of a visual display device according to an embodiment of the present invention.

FIG. 2 is a block circuit diagram of an image data transfer unit of the display controller of FIG.

3 is a diagram showing a timing of the image data transfer unit of FIG.

FIG. 4 is a timing diagram for explaining the operation of the display controller of the visual display device of FIG.

FIG. 5 is a block circuit diagram of a conventional visual display device.

6 is a timing diagram for explaining the operation of the display controller of the visual display device of FIG.

[Explanation of symbols]

 1 CPU 2 Bus line 3 ROM 4 RAM 5 Graphic controller 7 Visual display device 20 Display controller 21 Image memory access unit 22 Image memory 23 Image data transfer unit 24 Image memory address generation unit 25 Timing generation unit 26 Flip-flop stack structure F. F flip-flop MUX multiplexer

Claims (1)

[Claims] 1. A display device comprising a graphic controller, a display controller, an image memory and a visual display, wherein the display controller has a plurality of stages in an output section for outputting image data from the image memory to the visual display. A display device having a stack structure composed of flip-flops, wherein transfer of image data of the image memory to the stack structure is performed by cycle stealing the access timing between the graphic controller and the image memory.