KR20030027303A - Data driver ic and liquid crystal display with the same - Google Patents

Abstract

PURPOSE: A data driver IC and liquid crystal display device having the same is provided to simplify a liquid crystal module structure irregardless of a driving method and an interface signal of an external image source system. CONSTITUTION: A timing control part(110) receives a picture signal via one end and a control signal for displaying the picture signal to write and read the picture signal to and from a line memory(120). The timing control part generates the first and second timing signals based on the control signal. A data driver part(130) outputs a plurality of data signals for outputting the read picture signal to a plurality of data lines based on the second timing signal. A level shifter part(140) outputs a control signal for driving a gate driver part based on the second timing signal. A common electrode voltage generating part(150) outputs a common electrode voltage based on a common electrode voltage control signal from the timing control region.

Description

Data driver IC and liquid crystal display having the same {DATA DRIVER IC AND LIQUID CRYSTAL DISPLAY WITH THE SAME}

The present invention relates to a liquid crystal display, and more particularly, to a one-chip data driver IC having a timing controller, a line memory, a level shifter, and a common electrode voltage generator, and a liquid crystal display having the same.

In general, in the interface of the liquid crystal display, signals provided by an external graphic controller cannot directly drive the data driver and the gate driver in the liquid crystal module.

Therefore, FPGA or ASIC is used to make the timing controller to convert the signal between the graphic controller and each driver and to make the necessary control signal. In addition, when special driving is required, a line memory must be separately provided in the timing controller.

As such, the timing controller changes the output signal of the graphic controller to drive the drive IC in the liquid crystal module, and makes a signal for converting the common electrode voltage according to one line or one frame. It is possible to change according to.

For example, a signal for driving the drive IC may be directly provided depending on the type of graphic controller, or a driving signal may be provided through a timing controller.

In addition, when the line memory is used to reduce the number of data drive ICs, a timing controller separately provided is required.

In this way, the interface method with the system and the timing controller are determined depending on the type and driving method of the graphic controller.

In addition, in a liquid crystal display device using low temperature polysilicon (LTPS) or special amorphous silicon (a-Si), the gate clock and the start pulse are integrated in the liquid crystal panel without using a separate gate drive IC. Since the level of is to be changed to the gate on / off level, a level shifter IC must be used inside the driving circuit or inside the liquid crystal panel, and a separate common electrode voltage generator is required.

As such, there is a problem in circuit configuration because additional circuits are included in the driving circuit portion of the liquid crystal module in some cases. In addition, different types of products and timing control ICs in various combinations of vendors and systems may be required.

Accordingly, the present invention has been made in an effort to solve such a conventional problem, and an object of the present invention is to include a timing control region, a memory region, a level shifter region, and a common electrode voltage generation region in a drive IC. It is to provide a data driver IC for simplifying the structure of the liquid crystal module irrespective of the interface signal and the driving method of the original system.

Another object of the present invention is to provide a liquid crystal display device comprising the one-chipized data driver IC.

1 is a view for explaining a liquid crystal display device according to the present invention.

2 is a waveform diagram illustrating data stored in each data driver IC according to an exemplary embodiment of the present invention.

3 is a block diagram illustrating the data driver IC of FIG. 1 described above.

<Description of the symbols for the main parts of the drawings>

10: data driver section 20: gate driver section

110: timing controller 120: line memory

130: data driver 140: level shifter

150: common electrode voltage generator

According to one aspect of the present invention, there is provided a data driver IC.

Line memory area;

Timing control which receives an image signal input through one end and a control signal for display thereof, writes and reads the image signal into the line memory area, and generates and outputs first and second timing signals based on the control signal. domain;

And a data driver area for outputting a plurality of data signals for outputting an image signal read out from the timing control area to a plurality of data lines based on the second timing signal.

The data driver IC may include a level shifter region configured to output a control signal for driving a gate driver based on the second timing signal; And a common electrode voltage generation region configured to output a common electrode voltage based on the common electrode voltage control signal provided from the timing control region.

In addition, a liquid crystal display device according to another aspect for realizing the above object of the present invention includes a plurality of data lines, a plurality of gate lines, a switching element, and a pixel electrode.

An image corresponding to the image signal according to a first timing signal generated based on the control signal by receiving a control signal for controlling the image signal and its display from an external graphic controller including a plurality of one-chip data driver ICs; A data driver unit outputting a voltage to the data line and outputting a second timing signal generated based on the control signal;

And a gate driver configured to sequentially output a scan signal to the gate line based on the second timing signal.

Here, the data driver unit,

One master data driver IC operating as a master; And a plurality of slave data driver ICs operating as slaves depending on the master data driver IC.

At this time, the master data driver IC,

Line memory area;

Timing control which receives an image signal input through one end and a control signal for display thereof, writes and reads the image signal into the line memory area, and generates and outputs first and second timing signals based on the control signal. domain;

A data driver area for outputting a plurality of data signals for outputting an image signal read out from the timing control area to a plurality of data lines based on the second timing signal;

A level shifter region configured to output a control signal for driving a gate driver based on the second timing signal; And

It is preferable to include a common electrode voltage generation region for outputting a common electrode voltage based on the common electrode voltage control signal provided from the timing control region.

In addition, the slave data driver IC,

Line memory area;

Timing control for receiving an image signal input through one end and a control signal for display thereof, writing and reading the image signal into the line memory area, and generating and outputting first and second timing signals based on the control signal. domain; And

And a data driver area for outputting a plurality of data signals for outputting image signals read out from the timing control area to a plurality of data lines based on the second timing signal.

According to such a data driver IC and a liquid crystal display including the same, an interface signal and a driving method of an external image source source system by embedding a timing control region, a memory region, a level shifter region, and a common electrode voltage generation region in a drive IC; The structure of the liquid crystal module can be simplified regardless of the resolution of the display.

Then, embodiments will be described so that those skilled in the art can easily implement the present invention.

1 is a view for explaining a liquid crystal display device according to the present invention.

Referring to FIG. 1, a liquid crystal display according to the present invention, in particular, a liquid crystal display module, includes a data driver unit 10 including a plurality of data driver ICs, a gate driver unit 20 including a plurality of gate driver ICs, and a plurality of data. And a pixel electrode (not shown) provided between the line and the plurality of gate lines.

The data driver unit 10 includes a master data driver and a slave data driver. The data driver 10 receives an RGB image signal together with an RGB image signal from an external graphic controller and outputs the RGB image signal to a data line. The timing signal for driving the unit 20 is output to the gate driver 20. Here, the master data driver and the slave data driver are preferably composed of one one-chip IC, and the IC that performs the master operation is called a master data driver IC, and operates in dependence on the master data driver IC. The data driver is called a slave data driver IC.

More specifically, the master data driver IC outputs a timing signal for driving the gate driver unit which receives the RGB image signal and the control signal provided from an external graphic controller and outputs a scan signal to the gate driver unit 20, and displays the display. An image signal for is output to a data line, and a first status signal Status1 is output to an adjacent slave data driver IC.

The first slave data driver IC receives an RGB image signal and a control signal provided from an external graphic control, outputs an image signal for display to a data line, and outputs a second status signal Status2 adjacent to the second slave data. Output to the driver IC.

FIG. 2 is a waveform diagram illustrating data stored in each data driver IC according to an exemplary embodiment of the present invention. In particular, FIG. 2 illustrates data stored according to input of a data enable signal from a graphic controller.

1 and 2, when the data enable signal is applied from the graphic control, the data driver IC (or master data driver IC) located first stores data for applying to the first to 240 th data lines. The first state signal is then output to the data driver IC (or first slave data driver IC) located second.

The first slave data driver IC receiving the first state signal stores data for applying to the 241 th through 480 th data lines, and then places the second state signal in the third data driver IC (or the second slave). Data driver IC).

3 is a block diagram illustrating the data driver IC of FIG. 1 described above.

Referring to FIG. 3, a data driver IC according to an exemplary embodiment of the present invention may include a timing controller 110, a line memory 120, a data driver 130, a level shifter 140, and a common electrode voltage generator 150. It is preferable that it consists of one IC.

The timing controller 110 receives an image signal RGB provided from an external graphic controller and control signals RESET, MCLK, HSYNC, VSYNC, and DE that control the display thereof, and stores the image signal in the line memory 120. do.

In addition, the timing controller 110 outputs the first timing signals STH, TP, and MCLK controlling the output thereof together with the image signal DATA to the data driver 130, and outputs a common electrode voltage control signal Vcom control. The common electrode voltage generator 150 is provided.

In addition, the timing controller 110 provides the gate driver driving signals STV and CKV to the level shifter 140 to control the output of the second timing signal for driving the gate driver 20. At this time, the level shifter 140 receives the gate-on voltage V _ON and the gate-off voltage V _OFF from the outside together with the gate driver driving signals STV and CKV, and operates the gate driver 20. The signals STV, CKV, and CKVB for controlling the signals are output to the gate driver 20.

In addition, the timing controller 110 outputs an address and an enable signal to the line memory 120, and performs a write and read operation of data.

The line memory 120 is activated by an enable signal input from the timing controller 110 to write or read data at a specified address. Here, the capacity of the line memory is determined by the number of channels, preferably a multiple of the number of channels of the data driver 130. If the output is 360 channels, 2 lines of 360 × 3 × 6 × 2 = 12,960 bits of memory are built-in.

The data driver 130 converts an image signal input from the timing controller based on the first timing signals STH, TP, and MCLK provided from the timing controller, and outputs the converted image signal to a data line provided in the liquid crystal panel.

The common electrode voltage generator 150 is activated by the common electrode voltage control signal Vcom control input from the timing controller 110 to output the common electrode voltage to the common electrode line provided in the liquid crystal panel.

2, the timing controller 110, the line memory 120, the data driver 130, and the level shifter 140 when the one-chip data driver IC shown in FIG. The common electrode voltage generator 150 operates in an active state.

On the other hand, when the one-chip data driver IC is positioned at the second or later position of the data driver unit and operates as a slave depending on the master data driver IC, the level shifter 140 and the common electrode voltage generator 150 are described. Is preferably inactive.

Of course, it is easy for a person skilled in the art to distinguish between the master data driver IC and the slave data driver IC by simply selecting the control signal.

In addition, it is obvious that the manufacturing process may be performed separately depending on whether the master data driver IC or the slave data driver IC is used at the manufacturing stage of the data driver IC.

In the above description, the timing controller 110 configured in the data driver IC according to the present invention integrates the gate driver IC into the liquid crystal module and drives the gate driver through the level shifter 140 to drive the integrated gate driver IC. An example of outputting was described.

In addition, the timing controller 110 configured in the data driver IC may output the driving signal of the transmission gate in the liquid crystal module. Here, the transmission gate is connected between the output terminal of the data driver IC and the data line to set the switching path so that the data signal is input to the data line.

If a transmission gate is used and the data driver IC outputs a data signal through n output terminals, it can output more than n, for example, 2n data lines.

This transmission gate drive can reduce the number of data driver ICs to, for example, 1/2. That is, there is no restriction on the interface method of the graphic controller and a simplified module structure can be made.

As described above, according to the present invention, the main clock (MCLK), the data enable signal (DE), the horizontal synchronization signal (HSYNC), which are signals that can be supported by both the existing graphic controller and the main processor unit (MPU), The vertical synchronizing signal VSYNC is directly provided by the integrated data driver IC in the liquid crystal module, and the output is output to the data line by an operation of a timing controller configured inside the data driver IC. In other words, when MCLK, DE, HSYNC, and VSYNC are received from an external graphic controller, they exist inside each IC, and the corresponding data is stored in the line memory designed for the number of channels, and the output can be directly exported at the required timing.

In addition, the common electrode voltage VCOM is also output directly to the common electrode line in the liquid crystal module by the timing controller and the common electrode voltage generator 150 configured inside the data drive IC.

Further, even when a line memory is used to reduce the number of data drive ICs and when the gate driver IC is integrated into the liquid crystal panel, the image can be displayed even if the driver circuit is not provided with a separate drive IC.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

As described above, according to the present invention, the timing control function, the line memory function, the level shifting function, and the common electrode voltage generation function are incorporated in the driver IC, so that the control signal for the image signal and its display from an external image source source system can be obtained. It is possible to simplify the structure of the liquid crystal module because it is possible to directly output the scan signal for display to the liquid crystal module with the corresponding image signal, and simply by adding or reducing the number of chips of the present invention regardless of the resolution of the display Can be implemented.

Claims (11)

Line memory area; Timing control which receives an image signal input through one end and a control signal for display thereof, writes and reads the image signal into the line memory area, and generates and outputs first and second timing signals based on the control signal. domain; A data driver region for outputting a plurality of data signals for outputting image signals read out from the timing control region to a plurality of data lines based on the second timing signal Data driver IC comprising a. The method of claim 1, A level shifter region configured to output a control signal for driving a gate driver based on the second timing signal; And A common electrode voltage generation region that outputs a common electrode voltage based on the common electrode voltage control signal provided from the timing control region. Data driver IC further comprising. The method of claim 1, wherein the timing control region, And an R / L terminal, and determining a shift direction of data through the R / L terminal. The method of claim 1, wherein the timing control region, A C / S_R input terminal for connection with a timing control region configured in a previous data driver IC; And And further including a C / S_L output terminal for connecting to a timing control region configured in the data driver IC thereafter, and inputting / outputting a status signal through the C / S_R input terminal and the C / S_L output terminal. Data driver IC. The method of claim 1, wherein the line memory, And a data driver output pin number outputted from the data driver area. The method of claim 2, wherein the timing control region, Further comprising an M / S terminal, when activating the M / S terminal to activate the level shifter region and the common electrode voltage generation region to control the data driver IC to perform a master operation, And deactivating the level shifter region and the common electrode voltage generation region to control the data driver IC to perform a slave operation when the M / S terminal is deactivated. The method of claim 2, wherein the timing control region, And a signal for controlling an operation of a transmission gate for controlling an output path of a data signal output from the data driver region to the level shifter region. In a liquid crystal display device comprising a plurality of data lines, a plurality of gate lines, a switching element, and a pixel electrode, An image corresponding to the image signal according to a first timing signal generated based on the control signal by receiving a control signal for controlling the image signal and its display from an external graphic controller including a plurality of one-chip data driver ICs; A data driver unit outputting a voltage to the data line and outputting a second timing signal generated based on the control signal; A gate driver unit sequentially outputting a scan signal to the gate line based on the second timing signal Liquid crystal display comprising a. The method of claim 8, wherein the data driver unit, One master data driver IC operating as a master; And A plurality of slave data driver ICs operating as slaves depending on the master data driver IC. Liquid crystal display comprising a. The method of claim 9, wherein the master data driver IC, Line memory area; Timing control which receives an image signal input through one end and a control signal for display thereof, writes and reads the image signal into the line memory area, and generates and outputs first and second timing signals based on the control signal. domain; A data driver area for outputting a plurality of data signals for outputting an image signal read out from the timing control area to a plurality of data lines based on the second timing signal; A level shifter region configured to output a control signal for driving a gate driver based on the second timing signal; And A common electrode voltage generation region that outputs a common electrode voltage based on the common electrode voltage control signal provided from the timing control region. Liquid crystal display comprising a. The method of claim 9, wherein the slave data driver IC, Line memory area; Timing control which receives an image signal input through one end and a control signal for display thereof, writes and reads the image signal into the line memory area, and generates and outputs first and second timing signals based on the control signal. domain; And A data driver region for outputting a plurality of data signals for outputting image signals read out from the timing control region to a plurality of data lines based on the second timing signal Liquid crystal display comprising a.