JPH04315893A - Memory circuit - Google Patents

Abstract

PURPOSE:To realize a memory circuit not requiring a refreshing operation, with small number of circuit elements and with high data processing speed. CONSTITUTION:This system is provided with a data storage block 1 vertically connected with data latch circuits 11 to 14 which retain an inputted data DTI and transmit them to a post-stage when latch signals L1 to L4 are at low level and stops the input of the data DTI and retain them when the latch signals L1 to L4 are at high level. A latch signal supply circuit 2 is provided which supplys the latch signals L1 to L4 which change from the low level to the high level each time the level of a clock signal changes from the final stage to the side prestage of the respective data latch circuits 11 to 14.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory circuit, and more particularly to a memory circuit that stores discrete value information in synchronization with a clock signal.

0002

2. Description of the Related Art Conventional memory circuits are basically a dynamic type, which stores information using the charge of a capacitor C1, as shown in FIG. 4, and a flip-flop circuit or data latch, as shown in FIG. There is a static type. The dynamic type allows a large capacity random access memory (DRAM) to be easily obtained, but requires a refresh operation. The static type is also used in random access memory (SRAM) and does not require a refresh operation, but requires a large area per memory cell.

The dynamic memory circuit shown in FIG. 4 configures a 1-bit memory cell MC1 using an N-channel MOS transistor Q1 and a capacitor C1. By setting the word line WL to a high level in response to an address signal and applying data to the data line DL, the MOS transistor Q1 is turned on and information is stored by accumulating charge in the capacitor C1.

Memory cell MC2 of the static type memory circuit shown in FIG. 5 includes MOS transistors Q21 to Q21.
Q24 forms a CMOS type flip-flop,
Data is transmitted using switching MOS transistors Q25 and Q26. Word line WL
Information is stored by setting MOS transistors Q25 and Q26 to a high level and applying complementary data to data lines DL1 and DL2, respectively.

These memory circuits generate address signals externally or internally for all data to provide one-to-one correspondence.
The data can be written using . Furthermore, when the capacity increases, large data buffers are required for the data lines DL, DL1, and DL2. In addition, first-in first-out (FI) has an address counter built into the chip.
FO) memory is also an application of these memory circuits.

[0006] Furthermore, a clock having one cycle per data period is used as the synchronization clock. In other words, writing was performed using a clock having a frequency twice the maximum data frequency.

[0007]

[Problems to be Solved by the Invention] These conventional memory circuits have the problem that the dynamic type is suitable for increasing capacity, but requires a refresh operation, and the static type requires a large area per cell, which hinders high integration. was there.

Furthermore, in either case, when the capacity increases, a large data buffer is required for the data line, and address signals must be created externally or internally for all data on a one-to-one basis, resulting in a large circuit size. There was a problem that the chip area became large.

Furthermore, the maximum data frequency is half the synchronized clock frequency, and when handling high-speed data, the maximum frequency of the data (data speed) is determined by the maximum frequency of the clock.
The problem was that it was limited.

0010

[Means for Solving the Problems] A memory circuit of the present invention includes:
When the corresponding latch signal is at the first level, the data at the input terminal is held and transmitted to the output terminal, and when the corresponding latch signal is at the second level, the input of data from the input terminal is stopped and the held data is continued. a data storage block in which a plurality of data latch circuits to be held are successively connected in cascade, and data is inputted from the input terminal of the data latch circuit at the frontmost stage; and a clock signal is at a second level when a reset signal is at a first level. Then, each of the latch signals corresponding to each of the data latch circuits is set to the first level, and when the reset signal is at the second level, each of the latch signals is set to the plurality of data sets every time the level of the clock signal changes. The latch circuit includes a latch signal supply section that sequentially changes the latch signal to level 2 from the latch signal corresponding to the last stage of the latch circuit to the previous stage side.

Furthermore, a plurality of data storage blocks are provided, data is inputted to each of these data storage blocks in parallel, and a latch signal is supplied from a latch signal supply section to each of the data storage blocks.

0012

[Operation] In the present invention, when the latch signal is at the first level, the input data is held and transmitted to the subsequent stage, and when the latch signal is at the second level, the data input is stopped and the held data is continued. A data storage block is provided in which a plurality of stages of data latch circuits to be held are connected in cascade, and each data latch circuit moves from the last stage to the previous stage, and from the first level to the second level each time the level of the clock signal changes. Since the configuration supplies latch signals that change sequentially, data can be sequentially written to each data latch circuit every time the level of the clock signal changes. Compared to the conventional example, when the clock signal frequency is the same, Data can be written at twice the speed.

Furthermore, since the memory cell is a data latch circuit, there is no need for a refresh circuit, and the number of circuit elements is smaller than that of a static type memory cell using flip-flops, making the circuit simpler. Furthermore, even if the capacity is increased, there is no need to increase the size of the data buffer of the data line, so the chip area can be reduced.

[0014]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

In this embodiment, when the corresponding latch signals L1 to L4 are at a low level, data at the input terminal is held and transmitted to the output terminal, and when the corresponding latch signals L1 to L4 are at a high level, input of data from the input terminal is stopped and held. A plurality of data latch circuits 11 to 14 that continue to hold data are sequentially connected in cascade, and the data D is output from the input terminal of the data latch circuit 11 at the forefront stage.
A data storage block 1 that inputs TI, a plurality of cascade-connected clock latch circuits 21 to 24, and a buffer B1.
, and an inverter IV1, and when the clock signal CK becomes high level when the reset signal RST is low level, each latch signal L1 to L4 corresponding to each data latch circuit 11 to 14 is set to low level, and the reset signal RS
When T is at a high level, each latch signal L1 to L4 is connected to the last stage of the plurality of data latch circuits 11 to 14 and the corresponding latch signal L every time the level of the clock signal CK changes.
1 to the previous stage side and a latch signal supply section 2 that sequentially brings the corresponding latch signals L2, L3, and L4 to a high level.

Next, the operation of this embodiment will be explained. FIG. 2 is a timing diagram of signals of various parts for explaining the operation of this embodiment.

Data DTI is input in synchronization with clock signal CK, and changes every time the level of clock signal CK changes.

The latch signal supply section 2 supplies a reset signal RS.
When T is at a low level, when the clock signal CK goes to a high level, all of the latch signals L1 to L4 are set to a low level, and the data storage block 1 is placed in a reset state. At this time, each of the data latch circuits 11 to 14 sequentially transmits the first input data DTI-0 to the subsequent stage side (data through) and holds the data, respectively.

[0020] The latch signal supply section 2 supplies a reset signal RS.
When T goes high, each time the level of the clock signal CK changes, the latch signal L1 input to the data latch circuit 14 is first set to high level, and then the latch signal L2 input to the data latch circuit 13 is set high. Similarly, the latch signal L3 and the latch signal L4 are sequentially set to high level.

When the latch signals L1 to L4 successively become high level, the data latch circuit 14 stops inputting data from the input terminal and continues to hold the data, so the first data DTI-0 is output to the data latch circuit. The next data DTI-1 passes through to the data latch circuit 13 and is continuously held there. Similarly, data DTI-2 is passed to the data latch circuit 12 and the data DT
I-3 is continuously held in the data latch circuit 11.

In this way, each time the level of the clock signal CK changes, the data latch circuits 14, 13, 12, 11
Data DTI-0, DTI-1, DTI-2, D
TI-3 is held (written) respectively, and the data holding (writing) state continues.

The data held in these data latch circuits 11-14 are output from the output terminals of each data latch circuit 11-14 as output data DTO1-DTO4.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

In this embodiment, a plurality (n) of data storage blocks 1 of the embodiment shown in FIG. 1 are provided, and data DTI is inputted in parallel to each of these data storage blocks 1-1 to 1-n. A latch signal is supplied from a latch signal supply section 2a to data latch circuits 11 to 14 of each data storage block 1-1 to 1-n.

In the first embodiment, a buffer for data DTI was not required, but when the number of data storage blocks increases as in this embodiment, a buffer B2 for data drive is required.
may be necessary.

Furthermore, the latch signal is reset at the first stage of the latch signal supply section 2a for the data storage blocks 1-1 to 1-n.
This can be realized by changing the level of the clock signal CK by the number of data latch circuits in the data latch circuit. That is, data initialization and writing reset need only be controlled by the latch signal supply section 2a, and all data can be easily initialized at once. Additionally, resetting can be performed selectively for each data storage block.

[0028]

As explained above, the present invention uses data latch circuits connected in series in a data storage section (data storage block), and the latch signal supply section corresponding to the conventional address generation section is also clocked. Since it can be configured with a latch circuit, the number of transistors that make up the data storage section is halved compared to a similar conventional memory circuit that uses flip-flops, and the number of transistors that make up circuits such as data buffers and address management can also be significantly reduced. Moreover, since no refresh circuit is required and the circuit configuration is simple, the chip area can be significantly reduced.

Furthermore, since the period of the data cycle and the period of the level change of the clock signal are the same, there is an effect that the data processing speed can be twice that of the conventional method.

Furthermore, by reducing the number of cascade-connected data latch circuits in the parallel-connected data storage sections, there is also the effect that the frequency of the synchronization clock can be further increased.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a first embodiment of the invention.

FIG. 2 is a timing diagram of signals of various parts for explaining the operation of the embodiment shown in FIG. 1;

FIG. 3 is a block diagram of a second embodiment of the invention.

FIG. 4 is a circuit diagram mainly consisting of memory cells of a first example of a conventional memory circuit.

FIG. 5 is a circuit diagram mainly consisting of memory cells of a second example of a conventional memory circuit.

[Explanation of symbols]

1, 1-1 to 1-n data storage block 2, 2
a Latch signal supply units 11 to 14 Data latch circuits 21 to 24 Clock latch circuit C1 Capacitors DL, DL1, DL2 Data lines MC1, MC2
Memory cells Q1, Q2 to Q26 MOS transistor WL
word line

Claims (2)

[Claims] 1. When the corresponding latch signals are at a first level, data at the input terminal is held and transmitted to the output terminal, and when the corresponding latch signals are at a second level, input of data from the input terminal is stopped and held. A data storage block has a data storage block in which a plurality of data latch circuits that continuously hold data are sequentially connected in cascade, and data is input from the input terminal of the data latch circuit in the first stage, and a clock signal is input when the reset signal is at the first level. When the level is set to the second level, each of the latch signals corresponding to each of the data latch circuits is set to the first level, and when the reset signal is at the second level, each of the latch signals is set to the first level each time the level of the clock signal changes. 2. A memory circuit comprising: a latch signal supply unit that sequentially sets the latch signal to level 2 from the latch signal corresponding to the last stage of the plurality of data latch circuits to the previous stage side. 2. The device according to claim 1, wherein a plurality of data storage blocks are provided, data is inputted to each of these data storage blocks in parallel, and a latch signal is supplied from a latch signal supply section to each of the data storage blocks. memory circuit.