KR920001615B1 - Micro computer - Google Patents

Abstract

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Description

Microcomputer

1 is a block diagram of an input / output processing unit according to the present invention.

2 is a block diagram of a single chip microcomputer according to the present invention.

3 is a format of a task command according to the present invention.

4 is an operation timing diagram of the input / output operation unit of FIG.

5 is an example of input processing (reset after transmission) using the format of FIG.

6 shows an example of input processing using the format of FIG. 3 (no reset after transmission).

7 is an example of input processing using the format of FIG. 3 (reset after matching).

8 is an example of input processing using the format of FIG. 3 (no reset after matching).

The present invention relates to a microcomputer, and more particularly, to a microcomputer suitable for a counter / timer of a single chip microcomputer that performs pulse input processing and pulse output processing by a counter / timer.

Conventionally, for the counter / timer of a single-chip microcomputer, the design and design of a VLSI microprocessor (“Motorola's MC 68 HC 11: Definition and Design of a VLSI Microprocessor” by IEEE MICRO, February 1984, JMSibigtroth) It is mentioned in the literature titled. The functions of the counters / timers described in this document include the number of counters / timers, the number of capture registers that hold the data that counts the pulse inputs, and the number of the comparators that hold the data that determine the time width of the pulse output generation. Is fixed, and when applied to the control of various devices, the degree of freedom is not considered.

In addition, the pin arrangement of the I / O is also fixed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a single chip microcomputer which has freedom in the number of counter / timers, the number of capture registers and the number of comparators, which is not considered in the related art, and which is applicable to the control of various devices.

The counter / timer is composed of an AU (Arithmetic Unit) and a designated register of a register group, which is incremented by the AU to return the data to its original state. The capture register is performed by transferring the counter / timer data to a designated register in the register group such as the counter / timer. Similarly, the comp register is performed by comparing the data of the designated register in the register group with the data of the counter / timer by AU.

In addition, in order to give the number of counter / timers, capture registers, and comp registers to have a degree of freedom, the CPU has instructions for setting functions at the time of initializing the program of the CPU. Run

2 shows a configuration of a single chip microcomputer showing an embodiment of the present invention. The microcomputer unit 100 includes a central processing unit (CPU) 200, a data memory unit (RAM) 201, and a program memory unit (ROM) 202.

The input / output processing unit 100 ′, which is a counter / timer device, includes an input / output task register unit 205, a task decoder unit 206, and an input / output operation unit 207.

The interface between the microcomputer unit 100 and the input / output processing unit 100 'is performed by the data bus 203, the address and the control bus 204.

The input / output task register unit 205 is a register group having software for defining input / output functions, and the microcomputer unit 100 defines the input / output function to the input / output task register unit 205 via the data bus 203. To fill in. The software written in the input / output task register unit 205 is sequentially read out for each input / output task forming a basic input / output function, and the input / output operation unit 207 is controlled by the task decoder unit 206 according to the input / output task.

The task decoder 206 has a function of generating a signal for controlling the input / output operation unit 207 according to the input / output task and the signal state of the input group 208.

The input / output operation unit 207 transfers the increment for the counter / timer, transfers the data of the counter / timer to the capture register, compares the data of the counter / timer with the data in the comparator, and outputs the output signal to the output group 209. Generation occurs. Therefore, the input / output processing unit 100 'can perform a pulse processing function dedicated to input / output, input or output only, and can also perform counter / timer operation as a counter / timer device.

Here, the detailed block structure of the input / output processing part 100 'which is a counter / timer device is shown in FIG. The input / output task register unit 205 is composed of an input / output task signal generation circuit 101, a task address decoder 102, and a task register group 103. In order to control various devices, it is necessary to execute a plurality of input / output processing tasks. Many input / output processes are stored in the task register group 103. Therefore, the task number is generated by the input / output task signal generation circuit 101, and the task register decoder 102 reads and executes the input / output task corresponding to the task number from the task register group 103. The task register group 103 is a storage unit for RLDR an input / output task that defines each input / output function to perform each input / output function by using each selected register for each input / output terminal pin, and a control function for the input / output operation unit 207. It can also be configured to include a control unit corresponding to the input and output tasks that define the. For each I / O task, as shown in Fig. 3, the I / O task number, I / O designation, the register number of the counter / timer, the register number of the capture / compare, the counting condition, the capture / compart condition, and the pin number of the clock input. The pin number of the capture / reset input and the pin number of the output are data. The read input / output task is the control signal 113 and the input / output pin control signal of the input / output operation unit 207 J through the input / output operation decoder 104. 114). Reference numeral 115 denotes a pin number control circuit for inputting the input group 208. The pin number control circuit 115 and the input / output operation unit 207 form an input / output processing operation unit.

The input / output operation unit 207 includes a register group 105 including a plurality of general purpose registers consisting of a counter / timer, a capture register and a comparator register, a first source latch 106, a second source latch 107, and an input / output operation. And an AU 108, a destination latch 109, an output latch group 110, a write data buffer 111 and a read data buffer 112.

The register specified by each input / output task of the register group 105 is accessed to perform input / output processing. The AI 108 performs calculations such as increments and comparisons.

In addition, the register group 105, the first source latch 106, the second source latch 107, the AU 108, the destination latch 109, the write data buffer 111 and the read data buffer 112 As shown in FIG. 1, the first input / output lead bus 116, the second input / output lead bus 117, the input / output light bus 118, and the data bus of the microcomputer unit 100, respectively. It is connected to an input / output interface bus 119 that interfaces with 203. The write data buffer 111 and read data buffer 112 are buffers for writing and reading the write data and read data from the microcomputer unit 100 into the registers of the register group 105. The write data buffer 111, the read data buffer 112, and the input / output interface bus 119 constitute an input / output interface bus means.

The output latch group 110 is a latch which holds a comparison result when a comparison is made, and the output of this latch is connected to an output pin, and outputs a signal to the output group 209.

4 is a timing diagram of the input / output operation unit 207. The input / output operation unit 207 operates by a two-phase clock signal represented by the first clock signals? 1 and (b) indicated by (a) and without overlapping of the second clock signals? 2. Further, the first clock signal? 1 (a) is an internal clock signal of the microcomputer unit 100 (first, the operation will be described in the mode of comparing with the data of the comparator after counting the counter / timer. Take the i-th I / O task, which is read in the cycle.) (c) shows the state of the first input / output lead bus 116. When the first clock signal? 1 (a) is "1", that is, in each T ₁ period, the first input / output lead bus 116 is precharged.

The clock signal of 2 ψ2 (b) is when a "1", that is, the first of the C1 when the T ₃ duration of the cycle, the i-th register group 105 specified by the counter / timer of claim 1 by a single input-output tasks According to the data U of the register (h-1), the first input / output read bus 116 starts discharge, and during the period when the second clock signal? 2 (b) is "1", that is, the C1 period. During the period T ₃ , data U is established. The data U on the first input / output lead bus 116 is latched in the T ₃ first source latch 106 during the period in which the second clock signal? 2 (b) is "1", that is, in the C1 period. (d) shows the state of the first source latch 106. The data is latched in the first source latch 106 (d) at the time of the broken line, that is, at the transition time from the T ₃ period to the T ₄ period of the C1 cycle. The data U latched in the first source latch 106 (d) is precharged in the period in which the second clock signal ψ 2 (b) is "1", that is, in the period T ₃ of the C1 period, AU 108. It is input to the A terminal of. On the other hand, in the data input to the B terminal of the AU 108, each bit is 0, that is, the binary value is 0, and the AU 108 outputs the counting operation necessary for the counter / timer of the input / output operation decoder 104. It performs in accordance with the control signal 113.

That is, it increments the counter / timer. The state of the AU 108 is shown as (e). The data U + 1 incremented by the AU 108 (e) is inputted to the destination latch 109, and during the period in which the first clock signal ψ1 (a) is "1", that is, T ₁ of the C2 period. It is latched to the destination latch 109 during the period. (F) shows the state of the destination latch 109. Next, the output of the destination latch 109 is made up of the input / output light bus 118 and the _first precharged during the period in which the first clock signal? 1 (a) is "1", that is, during the T1 period of the C2 period. It is input to the input / output lead bus 116 of 1. (g) and (c) show these states. That is, the second clock signal ψ2 (b) is "1" in the inter popular, that is, input and output leads for of the C2 to destination latch 109, the data U + 1 of (f) in the T ₃ duration of the cycle so that the first The bus 116 (c) and the light bus 118 (g) for input / output are discharged, and data is established on each bus. Data U + 1 on the first input / output lead bus 116 (c) is latched to the first source latch 106 (d). The data U + 1 on the input / output light bus 18 (g) is written to the first register h-1 of the register group 105 in which the first is designated as a counter / timer. In other words, this data U + 1 is written in the first source latch 106 (d) for comparison. In the first register h-1 of the register group 105, this data U + 1 is written in the period T ₃ of the C2 period to make the register itself a first counter / timer.

On the other hand, the reference data for comparison, which is the basis of the comparison, is read out from the fourth register m of the register group 105 designated as the comparator by the ith input / output task and the second read / output lead bus 117 is used. Is written into the second source latch 107. The operation is explained by (j) and (k).

The second input / output read bus 117 is precharged during the period in which the _first clock signal? 1 (a) is "1", that is, during the T1 period of the C2 period. The clock signal of the next second of ψ2 (b) is "1" during the period, that is, data of the C2 cycle register (m) of the fourth of the register group 105, which holds the reference data in the T ₃ duration W Is discharged accordingly, and reference data is established on the second input / output lead bus 117 (j). The data W on the second input / output read bus 117 (j) has a second source latch 107 during the period in which the second clock signal ψ2 (b) is "1", that is, during the period T ₃ of the C2 period. (k).

The output of the first source latch 106 and the output of the second source latch 107 are respectively input to the A terminal and the B terminal of the AU 108, and the comparison operation indicated by the i < th > during the of period of the clock signal ψ1 (a) of the first is "1", that is, the pin number of the output group 209 specified by the being at the same time, the comparison result is output task single i-th end the T ₁ period of the C3 cycle It is held in the latch of the corresponding latch group 110 for output.

Next, as an example of the input function, the i + 1th I / O task read out at the C2 cycle following the ith I / O task transfers the data of the counter / timer to the capture register after counting the second counter / timer. Describe the operation.

The coefficient of the second counter / timer in the i + 1th input / output task is the same operation as the coefficient of the first counter / timer in the i-th input / output task to be compared after the coefficient. By this coefficient, the data of the second counter / timer is changed from V to V + 1 in the period T ₃ of the C4th cycle. The data register V + 1 after the count of the second register (h-2) of the register group 105 designated as the second counter / timer by the i + 1th input / output task is captured by this input / output task. In order to transfer to the third register (i) of the register group 105 designated by, from the destination latch 109 (f) in which the counted data V + 1 is temporarily held in the course of counting the I / O task. This is performed by writing the data V + 1 counted in the third register i of the register group 105 through the first input / output read bus 116 (c) in the period T ₃ of the C4 period. .

If this is explained in more detail as follows. Destination latch 109 (f) during the period when the second clock signal ψ 2 (b) is "1" on the first input / output lead bus 116 (c), that is, during the period T ₃ of the C4 period. The data V + 1 is established in accordance with the output of the data, and the data is written into the first source latch 106 (d). The written data V + 1 is input to the A terminal of the AU 108, and the AU 108 (e) inputs the same data V + 1 as the data V + 1 input to the A terminal in the T ₁ period of the C4 period. It is written to the destination latch 109 (f). Next, the clock signal ψ1 (a) is "1" during the period, that is, T pre of (g) output light bus 118 for up to _one period of the C4 cycle is the clock signal of the second of the first ψ2 ( During the period in which b) is "1", that is, in the period T ₃ of the C4th period, it is discharged in accordance with the data V + 1 of the destination latch 109 (f), and the data V + 1 is established. Data V + 1 on the input / output light bus 118 (g) is written to the third register of the register group 105 designated by the capture register by the i + 1th input / output task.

In summary, the plurality of I / O tasks written in the task register group 103 by the CPU 200 are sequentially read out in one ratio every two cycles, and each I / O task is four cycles in execution. Need. Here, the operation for a certain I / O task is executed every two cycles of appearance by using a continuous operation method of starting the operation for the next I / O task from the finished component. The input / output processing unit 100 'sequentially executes a plurality of input / output tasks in sequence, and repeats again from the first input / output task once again. This repetition achieves a count for every fixed period required for the timer. Also, even if a plurality of state changes occur simultaneously in the input group 208, all the set I / O tasks are repeatedly executed in the order from the first, so that the I / O tasks corresponding to all these state changes must be executed. And the desired input / output function is achieved.

The above-described input / output task of FIG. 3 controls the input / output operation unit 207. The format of the specification is shown in detail below.

The input / output task number is an address assigned to the task register group 103. The input / output designation specifies the input function for transferring the counter / timer data to the capture register and the output function for comparing the counter / timer data and the data of the comparator. The specification is shown below.

I / O designation = 0. … … Input function specification

I / O designation = 1. … … Output function specification

The counter / timer register number represents the number of the register to be the counter / timer in the register group 105. For example, when the counter / timer register number is "3", the third register of the register group 105 becomes the counter / timer of the input / output task.

The capture / compartment register number represents a register number which becomes a capture register or a comparator in the register group 105. For example, when the capture / compartment register number is “5”, the fifth register in register group 105 is the capture register (in the case of input function) or the comparator (in case of output function) of the input / output task. do.

The counting condition is a condition for counting a counter / timer. The contents are clock designation, counting control and reset control.

Clock designation = 0... … … Internal clock signal.

Clock designation = 1... … … External clock signal.

Coefficient control = 0... … … No counting operation.

Coefficient control = 1... … … Counting operation

Reset control = 0... … … No reset operation.

Reset control = 1... … … There is a reset operation.

The capture / compart condition is a transfer condition of the counter / timer data (in case of an input function) or a comparison condition of a counter / timer data (in the case of an output function). The content is post transfer control as a transfer condition.

Control after transmission = 0. … … No reset operation after transmission.

Control after transmission = 1... … … Reset operation after transmission.

As a comparison condition, control after matching is performed and result logic is determined.

Control after matching = 0. … … There is no reset operation after the counter / timer data matches the data of the comparator.

Control after match = 1... … … There is a reset operation after the counter / timer data matches the data in the comparator register.

Logical result = 0. … … When the data of the counter / timer coincides with or exceeds the data of the comparator, "0" is output to the output latch group 110.

Logical result = 1... … … When the data of the counter / timer coincides with or exceeds the data of the comparator, a "1" is output to the output latch group 110.

The clock input pin number is a pin number that becomes an external clock signal among the pins prepared for the input group 208 when an external clock is specified in an input / output task.

Like the clock input pin number, the capture / reset input pin number is used for the input group 208 or the output group 209 for the capture signal (in the case of the input function) or the reset signal (in the case of the output function) in any input / output task. Pin number to designate among pins prepared for).

The output pin number is a pin number which becomes an output pin among the pins prepared for the output group 209 in the input / output task of a certain output function.

Next, the input / output functions that can be realized using the input / output task of FIG. 3 are shown in FIG. 5, 6, 7, and 8. FIG.

5 shows the operation when the input / output task is set as follows. The figure shows the analog amount of the digital quantity.

That is, the k1-th input / output task of the task register group 103 is an input function, and the counter / timer is register n1 of the register group 105 and register m1 of the capture register group 105.

Counting is performed using the signal p1 of the pin p1 as an external clock input signal, the pin q1 as the capture input signal, and when the signal q1 of the pin q1 becomes "0", the counter / timer (register n1) The data is transferred to the capture register (register m1), and then the data of the counter / timer (register n1) is reset.

6 shows the operation when the input / output task is set as follows.

That is, although the operation in Fig. 5 is approximately the same, the count is continued without resetting the counter / timer data after the transfer.

7 is an output function for use in generating a certain interval, etc., and is an operation when the input / output task is set as follows.

7 is as follows. This input / output task is the k3th input / output task of the task register group 103, and is set as an output function. The counter / timer is register n3 of register group 105 and the comp register is register m3 of register group 105.

Counting is performed using an internal clock input signal. The comparison result shows that when the data of the counter / timer (register n3) matches or exceeds the data of the comparator (register m3), the logic “0” is output to the output pin o3 and the counter / timer (register n3) Reset the data.

8 is an output function used for duty control and the like, and the input / output task is set as follows.

The input / output task is the k4th input / output task of the task register group 103 and is set as an output function. The counter / timer is register n4 of register group 105 and the comp register is register m4 of register group 105.

Counting is performed using an internal clock input signal. The data of the counter / timer (register n4) is reset by pin q4 to which the reset input signal is input.

As a result of comparison, when the data of the counter / timer (register n4) matches or exceeds the data of the comparator (register m4), a logic "0" is output to the output pin o4.

The task register group 103 may be a RAM, an EPROM, an EEPROM, or a ROM, not a register.

According to the present invention, in the input / output function, the counter / timer count, the number of capture registers and the comparator registers are not fixed, and can be set freely by simple software combining a plurality of input / output tasks that realize the input / output function basically. There is an effect that it can be applied to the control of various devices.

In addition, the number of input pins and their roles, and the number of output pins and their roles can be freely set by commands using simple software that combines a plurality of input / output tasks that realize basic input / output functions. It works.

The clock signals? 1 and? 2 can be further speeded up by using a machine cycle instead of the memory cycle of the CPU 200, and there is an effect as a single chip microcomputer.

Simple software that combines a plurality of input / output tasks that realize the basic input / output function can be used to set the function of the input / output processing, and can have a degree of freedom as a system.

Claims (1)

A central processing unit (200) for transmitting a plurality of input / output tasks that define a pulse input / output function to the input / output processing unit (100 ') through buses (203, 204) before starting operation of the input / output processing unit (100'), and the buses (203, 204). And receive and store a plurality of input / output tasks that define the pulse input / output functions transmitted by the central processing unit 200 via the buses 203 and 204, and start operation after receiving the plurality of input / output tasks. And the input / output processing unit 100 'for reading out and executing the stored plurality of input / output tasks one by one, wherein the input / output processing unit 100' includes (a) at least one first terminal pin for receiving a capture signal; And (b) storing a plurality of input / output tasks transmitted through the buses 203 and 204, the input group 208 including at least one second terminal pin for receiving a clock signal. Incoming At least one input / output task of the tasks is an input / output task relating to the capture signal and the clock signal, and a task register group read one by one after the operation of the input / output processing unit 100 'is executed to execute the stored plurality of input / output tasks. 103) and (c) a plurality of registers, each time an input / output task is read from the task register group 103, one register of the plurality of registers is selected and used according to the read-out input / output task, By executing the arithmetic processing according to the input / output task and performing the same arithmetic processing each time the input / output task is read from the task register group 103, the pulse input / output processing prescribed by the input / output task is realized. When an input / output task relating to the capture signal and the clock signal is read out from 103 A capture signal received by the first terminal pin and an operation process according to an input / output task relating to the capture signal and the clock signal, using one register designated by the input / output task relating to the capture signal and the clock signal; And an input / output operation unit (207) for executing according to a clock signal received by the terminal pin of 2.

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