US20020126563A1 - Interleaved memory device for sequential access synchronous reading with simplified address counters - Google Patents
Interleaved memory device for sequential access synchronous reading with simplified address counters Download PDFInfo
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- US20020126563A1 US20020126563A1 US09/774,539 US77453901A US2002126563A1 US 20020126563 A1 US20020126563 A1 US 20020126563A1 US 77453901 A US77453901 A US 77453901A US 2002126563 A1 US2002126563 A1 US 2002126563A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/106—Data output latches
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1069—I/O lines read out arrangements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
Definitions
- the present invention relates in general to memory devices, and, in particular, to an interleaved memory device readable in a synchronous mode for successive locations with a sequential or burst access mode.
- Interleaved memory devices with a sequential (or burst) access mode comprises at least two banks of memory cells provided with their own address counter and independent decoding and sensing circuits.
- the array of memory cells may be subdivided in any number of blocks greater than two.
- FIG. 1 A typical simplified diagram of an interleaved memory device is depicted in FIG. 1.
- the successive addresses of the respective banks at which the read operations must be alternately carried out are sequentially generated automatically by incrementing internal address counters in synchronization with an external clock. This is after a first random access to a certain location on one of the two banks based upon the acquisition of an externally commanded address (first asynchronous read cycle).
- the management of sequential read operations may be designed for any number of banks by reading the different banks according to a scheme while always incrementing the address of the previous location.
- increments for the address counter for the respective banks must be carried out according to whether the start address for a new sequential or burst access synchronous read phase pertains to the even or the odd bank. Also, it may pertain to a certain pre-established bank in case of a number of banks N>2, according to the particular protocol used for managing the memory device.
- the start address is externally acquired and starts the first random access asynchronous read cycle.
- each of the internal address counters of the respective half-arrays or banks is an N-th binary counter formed by N bistable stages, typically flip-flops, and N half-adder stages connected in cascade.
- Each half-adder stage has a carry bit input CARRY for the carry bit coming from the preceding stage and an address input coming from its associated flip-flop.
- the propagation chain of the signal CARRY determines the maximum operating speed.
- carry bits are produced by ANDing the address bit and the carry bit coming from the previous stage. This imposes a wait for the propagation of signals throughout the N ⁇ 1 stages in order to receive the information concerning the carry bit of the N-th stage.
- Such a propagation scheme implies wait times that often are not compatible with a high operating speed, especially in counters having a large number of stages.
- each stage of the single internal address counter of one of the two banks is functionally coupled to a corresponding stage of the internal address register of the bank that follows it in the cycle succession of the sequential read of the data.
- the data is read from the different banks through a pass-gate that is switched to a conduction state by each increment pulse.
- each stage (latch) of the register that follows the counter is coupled to the corresponding stage (latch) of the register that follows it in the succession through a pass-gate that is switched in a conduction state by each increment pulse.
- FIG. 1 is a basic diagram of an interleaved memory device according to the prior art
- FIGS. 2 and 3 are timing diagrams of the main signals involved in accessing the banks of an interleaved memory device according to the prior art
- FIG. 4 depicts the architecture of a common address counter for an interleaved memory according to the prior art.
- FIG. 5 depicts the architecture of the address counter of the memory according to the present invention.
- the stages of the counter are coupled to respective stages of the register through pass-gates driven by the increment clock INC_ODD. This causes the content of the counter EVEN_COUNTER to be stored into the register ODD_REGISTER at each clock pulse.
- a significant hardware simplification is thus advantageously obtained because the number of components used to form a register is smaller than that necessary to form a binary counter.
- the address for the bank ODD_BANK is updated in a shorter time than the time required to increment a binary counter.
- the address of the bank ODD_BANK is updated (incremented) it is no longer necessary to wait for the propagation time of the carry because the new address is more rapidly obtained by copying the content of the counter EVEN_COUNTER.
- the diagram of FIG. 5 does not introduce any limitation or functional difference with respect to a classic realization with two binary counters, and may be conveniently used in all burst access interleaved memory devices.
- the control circuit of the memory device carries out the successive burst readings in a cycle by incrementing the addresses of the various banks in succession up to the N-th bank.
- the memory timing circuit effects the successive increments of the addresses from the K-th to the N-th bank, and thereafter, points again to the first bank.
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Abstract
An interleaved memory includes an array of memory cells divided into a first bank of memory cells and a second bank of memory cells. The interleaved memory operates in a burst access mode. A first address counter is coupled to the first bank of memory cells, and an address register is coupled to the first address counter and to the second bank of memory cells. A timing circuit generates increment pulses to the first address counter so that a first random access asynchronous read cycle starts with the first bank of memory cells. A function of an address counter for the second bank of memory cells is being performed by coping contents of the first address counter to the address register.
Description
- The present invention relates in general to memory devices, and, in particular, to an interleaved memory device readable in a synchronous mode for successive locations with a sequential or burst access mode.
- Interleaved memory devices with a sequential (or burst) access mode comprises at least two banks of memory cells provided with their own address counter and independent decoding and sensing circuits. The array of memory cells may be subdivided in any number of blocks greater than two.
- A typical simplified diagram of an interleaved memory device is depicted in FIG. 1. In a synchronous interleaved memory organized in two banks, the successive addresses of the respective banks at which the read operations must be alternately carried out are sequentially generated automatically by incrementing internal address counters in synchronization with an external clock. This is after a first random access to a certain location on one of the two banks based upon the acquisition of an externally commanded address (first asynchronous read cycle). The management of sequential read operations may be designed for any number of banks by reading the different banks according to a scheme while always incrementing the address of the previous location.
- The fact that an interleaved memory is most commonly divided in two half-arrays or banks of cells allows for a new read cycle to be started on a bank while the read cycle on the other bank has not yet terminated, thus saving time. In order to do this it is essential that address operations to the two banks be independent from each other.
- To maintain synchronization of the interleaved memory, increments for the address counter for the respective banks (EVEN/ODD) must be carried out according to whether the start address for a new sequential or burst access synchronous read phase pertains to the even or the odd bank. Also, it may pertain to a certain pre-established bank in case of a number of banks N>2, according to the particular protocol used for managing the memory device. The start address is externally acquired and starts the first random access asynchronous read cycle.
- In the most typical case of a two-bank interleaved memory, as may be observed in FIGS. 2 and 3, in a burst mode the read cycles successive to the first one are time interleaved between the banks ODD_BANK and EVEN_BANK. The increments of the address counters EVEN_COUNTER and ODD_COUNTER are controlled by two distinct incrementing clocks, labeled with INC_EVEN and INC_ODD in FIG. 4. This is produced by a control logic circuit that controls the timing of a synchronous read phase.
- According to the known technique, each of the internal address counters of the respective half-arrays or banks is an N-th binary counter formed by N bistable stages, typically flip-flops, and N half-adder stages connected in cascade. Each half-adder stage has a carry bit input CARRY for the carry bit coming from the preceding stage and an address input coming from its associated flip-flop.
- In such binary counters the propagation chain of the signal CARRY determines the maximum operating speed. In the propagation chain of the commonly used binary counters, carry bits are produced by ANDing the address bit and the carry bit coming from the previous stage. This imposes a wait for the propagation of signals throughout the N−1 stages in order to receive the information concerning the carry bit of the N-th stage. Such a propagation scheme implies wait times that often are not compatible with a high operating speed, especially in counters having a large number of stages.
- In view of the foregoing background, it is an object of the present invention to provided an approach that addresses the slowness in generating addresses for the banks of an interleaved memory during a sequential access synchronous read phase.
- This and other objects, advantages and features are provided by the fact that, differently from the common interleaved memory devices, only one internal address binary counter of one bank is used, while the function of an internal address counter of any other bank is performed by a common register in which it is copied the content (the internal address) of the binary counter of the first bank or of the content (the internal address) of the respective register of the bank that immediately precedes the considered bank according to the sequential read cycle scheme for all the memory banks, starting from the first one.
- According to a preferred embodiment of the invention, each stage of the single internal address counter of one of the two banks is functionally coupled to a corresponding stage of the internal address register of the bank that follows it in the cycle succession of the sequential read of the data. The data is read from the different banks through a pass-gate that is switched to a conduction state by each increment pulse. Similarly, each stage (latch) of the register that follows the counter is coupled to the corresponding stage (latch) of the register that follows it in the succession through a pass-gate that is switched in a conduction state by each increment pulse.
- The different aspects and advantages of the invention will become even more evident through a detailed description of the invention referring to the attached drawings in which:
- FIG. 1 is a basic diagram of an interleaved memory device according to the prior art;
- FIGS. 2 and 3 are timing diagrams of the main signals involved in accessing the banks of an interleaved memory device according to the prior art;
- FIG. 4 depicts the architecture of a common address counter for an interleaved memory according to the prior art; and
- FIG. 5 depicts the architecture of the address counter of the memory according to the present invention.
- For purposes of illustrating the present invention, reference will be made to a common interleaved memory device split in only two banks (half-matrices). The central point of the invention is the fact that, as it may be noticed from FIGS. 2 and 3, there is always a bank, which in the considered case is the bank EVEN_BANK, whose counter receives first the address increment. When the counter EVEN_COUNTER is incremented, the successive increment of the counter ODD_COUNTER produces exactly the same address stored in the counter EVEN_COUNTER.
- It has been found that in an interleaved memory device it is not necessary to use as many binary counters as the number of banks. Instead, the function of all the other binary counters except a first one may be advantageously performed by simply using registers. An architecture for producing addresses for the two banks of a burst memory device of the invention is depicted in FIG. 5.
- On the bank EVEN_BANK, the current address is pointed by a standard binary counter EVEN_COUNTER, while on the other bank ODD_BANK the address is pointed by a register ODD_REGISTER in which the content of the binary counter of the bank EVEN_BANK is copied as it is produced.
- According to a preferred embodiment of the invention, the stages of the counter are coupled to respective stages of the register through pass-gates driven by the increment clock INC_ODD. This causes the content of the counter EVEN_COUNTER to be stored into the register ODD_REGISTER at each clock pulse. A significant hardware simplification is thus advantageously obtained because the number of components used to form a register is smaller than that necessary to form a binary counter.
- Moreover, the address for the bank ODD_BANK is updated in a shorter time than the time required to increment a binary counter. In fact, when the address of the bank ODD_BANK is updated (incremented) it is no longer necessary to wait for the propagation time of the carry because the new address is more rapidly obtained by copying the content of the counter EVEN_COUNTER. The diagram of FIG. 5 does not introduce any limitation or functional difference with respect to a classic realization with two binary counters, and may be conveniently used in all burst access interleaved memory devices.
- Even in the case of a memory with a number of banks (N) greater than two, after having defined a first bank as reference bank, the control circuit of the memory device carries out the successive burst readings in a cycle by incrementing the addresses of the various banks in succession up to the N-th bank. Should the (asynchronously) addressed bank at each first read phase of a burst access cycle not be the first bank (reference bank) but the K-th (1<K<N) bank, the memory timing circuit effects the successive increments of the addresses from the K-th to the N-th bank, and thereafter, points again to the first bank.
- In practice, only the pre-defined first bank, from which the burst readings start will be provided with an address counter while all the other banks will have address registers functionally interconnected as in the above described example of an interleaved memory device with only two banks.
Claims (2)
1. An interleaved memory device readable in sequential access synchronous mode, having at least two banks of memory cells (EVEN_MATRIX, ODD_MATRIX) each provided with its own address counter, decoding structures (X-DEC-EVEN, X-DEC-ODD, Y-DEC-EVEN, Y-DEC-ODD) and sensing structures (SA, SA_LATCHES, SA_OUT_BUS), a timing circuit (TIMING) producing increment pulses (INC_EVEN, INC_ODD) of said address counters, characterized in that the function of address counter of all banks (ODD_MATRIX) with the exception of a first bank (EVEN_MATRIX) so pre-defined by a memory management protocol as the bank on which the first asynchronous random access read cycle is started, is performed by a register (ODD_REGISTER) in which is copied the content of the address binary counter (EVEN_COUNTER) of said first start bank of each first asynchronous read cycle or the content of the address register of the preceding bank in the cyclic synchronous read sequence at each increment pulse (INC_ODD) of the address of said preceding bank (ODD_MATRIX).
2. The memory device of claim 1 , characterized in that it comprises only two banks (EVEN_MATRIX, ODD_MATRIX), in which each stage of said address binary counter is coupled to a respective stage of said register (ODD_REGISTER) through a pass-gate switched in conduction state at each increment pulse (INC_ODD).
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP00830068 | 2000-01-31 | ||
| EP00830068.3 | 2000-01-31 | ||
| EP00830068A EP1122734B1 (en) | 2000-01-31 | 2000-01-31 | Burst interleaved memory with burst mode access in synchronous read phases wherein the two sub-arrays are independently readable with random access during asynchronous read phases |
| IT2000VA000015A ITVA20000015A1 (en) | 2000-05-30 | 2000-05-30 | INTERLACED MEMORY FOR SYNCHRONOUS READINGS WITH SEQUENTIAL ACCESS CONSEMPLIFIED ADDRESS COUNTERS. |
| ITVA00A0015 | 2000-05-30 | ||
| ITVA2000A000015 | 2000-05-30 |
Publications (2)
| Publication Number | Publication Date |
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| US20020126563A1 true US20020126563A1 (en) | 2002-09-12 |
| US6452864B1 US6452864B1 (en) | 2002-09-17 |
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| US09/774,539 Expired - Lifetime US6452864B1 (en) | 2000-01-31 | 2001-01-31 | Interleaved memory device for sequential access synchronous reading with simplified address counters |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20190117104A (en) * | 2018-04-06 | 2019-10-16 | 에스케이하이닉스 주식회사 | Semiconductor memory device and method of the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6665768B1 (en) * | 2000-10-12 | 2003-12-16 | Chipwrights Design, Inc. | Table look-up operation for SIMD processors with interleaved memory systems |
| US6732253B1 (en) | 2000-11-13 | 2004-05-04 | Chipwrights Design, Inc. | Loop handling for single instruction multiple datapath processor architectures |
| US6931518B1 (en) | 2000-11-28 | 2005-08-16 | Chipwrights Design, Inc. | Branching around conditional processing if states of all single instruction multiple datapaths are disabled and the computer program is non-deterministic |
| US6970985B2 (en) | 2002-07-09 | 2005-11-29 | Bluerisc Inc. | Statically speculative memory accessing |
| US7167942B1 (en) | 2003-06-09 | 2007-01-23 | Marvell International Ltd. | Dynamic random access memory controller |
| US20050114850A1 (en) | 2003-10-29 | 2005-05-26 | Saurabh Chheda | Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control |
| US7996671B2 (en) | 2003-11-17 | 2011-08-09 | Bluerisc Inc. | Security of program executables and microprocessors based on compiler-architecture interaction |
| US8607209B2 (en) | 2004-02-04 | 2013-12-10 | Bluerisc Inc. | Energy-focused compiler-assisted branch prediction |
| US7200693B2 (en) | 2004-08-27 | 2007-04-03 | Micron Technology, Inc. | Memory system and method having unidirectional data buses |
| US7209405B2 (en) * | 2005-02-23 | 2007-04-24 | Micron Technology, Inc. | Memory device and method having multiple internal data buses and memory bank interleaving |
| US20070028027A1 (en) * | 2005-07-26 | 2007-02-01 | Micron Technology, Inc. | Memory device and method having separate write data and read data buses |
| US20080126766A1 (en) | 2006-11-03 | 2008-05-29 | Saurabh Chheda | Securing microprocessors against information leakage and physical tampering |
| US11226909B2 (en) | 2018-08-24 | 2022-01-18 | Rambus Inc. | DRAM interface mode with interruptible internal transfer operation |
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| US5247644A (en) * | 1991-02-06 | 1993-09-21 | Advanced Micro Devices, Inc. | Processing system with improved sequential memory accessing |
| US5559990A (en) | 1992-02-14 | 1996-09-24 | Advanced Micro Devices, Inc. | Memories with burst mode access |
| DE69325119T2 (en) | 1992-03-19 | 1999-11-04 | Kabushiki Kaisha Toshiba, Kawasaki | Clock synchronized semiconductor memory device and access method |
| US5453957A (en) * | 1993-09-17 | 1995-09-26 | Cypress Semiconductor Corp. | Memory architecture for burst mode access |
| US5696917A (en) | 1994-06-03 | 1997-12-09 | Intel Corporation | Method and apparatus for performing burst read operations in an asynchronous nonvolatile memory |
| US5497355A (en) * | 1994-06-03 | 1996-03-05 | Intel Corporation | Synchronous address latching for memory arrays |
| US5596539A (en) | 1995-12-28 | 1997-01-21 | Lsi Logic Corporation | Method and apparatus for a low power self-timed memory control system |
| US5966724A (en) | 1996-01-11 | 1999-10-12 | Micron Technology, Inc. | Synchronous memory device with dual page and burst mode operations |
| KR100245276B1 (en) * | 1997-03-15 | 2000-02-15 | 윤종용 | Burst mode random access memory device |
| US5886930A (en) * | 1997-09-24 | 1999-03-23 | Emc Corporation | Bit interleaving in a memory which uses multi-bit DRAMs |
| JP4060442B2 (en) | 1998-05-28 | 2008-03-12 | 富士通株式会社 | Memory device |
-
2001
- 2001-01-31 US US09/774,539 patent/US6452864B1/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20190117104A (en) * | 2018-04-06 | 2019-10-16 | 에스케이하이닉스 주식회사 | Semiconductor memory device and method of the same |
| KR102570454B1 (en) | 2018-04-06 | 2023-08-25 | 에스케이하이닉스 주식회사 | Semiconductor memory device and method of the same |
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