US20050114850A1 - Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control - Google Patents

Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control Download PDF

Info

Publication number
US20050114850A1
US20050114850A1 US10967989 US96798904A US2005114850A1 US 20050114850 A1 US20050114850 A1 US 20050114850A1 US 10967989 US10967989 US 10967989 US 96798904 A US96798904 A US 96798904A US 2005114850 A1 US2005114850 A1 US 2005114850A1
Authority
US
Grant status
Application
Patent type
Prior art keywords
instructions
instruction
processor
energy
method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10967989
Inventor
Saurabh Chheda
Kristopher Carver
Raksit Ashok
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
III Holdings 2 LLC
Original Assignee
BlueRISC Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00Arrangements for software engineering
    • G06F8/40Transformation of program code
    • G06F8/41Compilation
    • G06F8/44Encoding
    • G06F8/443Optimisation
    • G06F8/4432Reducing the energy consumption
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30076Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30083Power or thermal control instructions
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing
    • Y02D10/40Reducing energy consumption at software or application level
    • Y02D10/41Compilation

Abstract

A method comprising of analyzing and transforming a program executable at compile-time such that a processor design objective is optimized. A method including analyzing an executable to estimate energy consumption of an application component in a processor. A method including transforming an executable to reduce energy consumption in a processor. A processor framework controlled by compiler inserted control that statically exposes parallelism in an instruction sequence. A processor framework to reduce energy consumption in an instruction memory system with compiler inserted control.

Description

    RELATED U.S. APPLICATION DATA
  • This application claims the benefits of U.S. Provisional Application No. 60/515,260, filed on Oct. 29, 2003, and Confirmation No 8574, entitled: ENERGY-FOCUSED RE-COMPILATION OF EXECUTABLES AND HARDWARE MECHANISMS BASED ON COMPILER-ARCHITECTURE INTERACTION AND COMPILER-INSERTED CONTROL, the contents of which are hereby incorporated by reference into this application as if set forth herein in full.
  • TECHNICAL FIELD
  • This invention relates generally to reducing energy and power consumption and improving performance in a microprocessor and, more particularly, to reducing energy and power consumption and improving performance by modifying a program executable. In addition, it relates to hardware mechanisms that use compiler control inserted into selected sequences of instructions to reduce energy consumption. Furthermore, it relates to compiler-exposed parallelism on compiler-selected program sequences that enables energy-efficient parallel execution with minimal hardware support required.
  • BACKGROUND
  • Microprocessors (referred to herein simply as “processors”) consume energy/power during their operation. It is advantageous to reduce the amount of energy consumed, particularly in the case of devices that run off limited power supplies.
  • Various factors affect the amount of energy that a processor consumes. For example, the frequency at which the processor operates, the voltage level that powers the processor, as well as the load capacitances affect processor energy consumption. Reducing the frequency of the processor or the voltage supply may decrease processor energy consumption, however, doing so may also adversely affect the performance of the processor.
  • Other techniques to reduce energy consumption by, for example, reducing load capacitances, may include changes to processor architectures and processor circuits. Some other techniques rely on modifying the application itself, or any other system layer, to improve energy efficiency.
  • An executable is a version of a software application that has been compiled from a programming language into a processor instruction set.
  • A source-level compiler transforms source codes into a sequence of instructions based on a processor instruction set.
  • Incorporating energy awareness into a source-level compiler is a very complex process; it could also negatively affect performance or some other design objective. This is due to the interactions between optimizations that target different objectives.
  • Additionally, not all source codes might be available for source-level compilation of an application, and therefore not all codes could be optimized in order to improve energy efficiency or reduce power consumption.
  • Moreover, the modifications would need to be incorporated in all compilers that aim to optimize energy consumption.
  • For a given processor there are typically many compilers available provided by many different vendors. These compilers have their own advantages and disadvantages.
  • This makes incorporating energy optimizations to source-level compilers a challenging task.
  • Accordingly, if energy-awareness is introduced at the executable-level instead, by transforming the executable itself, significant practical advantages could be achieved.
  • The goal would be to optimize executables that may have been fully optimized previously with a source-level compiler targeting a design aspect such as performance.
  • In general, such an executable-level re-compiling based approach to energy optimizations, could enable keeping optimizations performed during source-level compilation largely intact, could provide access to and optimize all program codes including static and dynamic libraries, and could be used on existing executable codes that have been generated with a variety of different compilers and potentially from different vendors.
  • The executable file itself provides a convenient interface between, for example, performance-oriented optimizations and energy-oriented optimizations. Moreover, one energy optimization tool or layer could be used with many different source-level compilers; this does away the need to retrofit all source compilers to optimize energy consumption.
  • Another aspect of this invention relates to scalability. Reductions in energy consumption should also be scalable, meaning that they are implemented such that processors having different architectures and instruction sets can easily be targeted. An executable-level re-compiling approach could provide such scalability.
  • This aspect may include an energy-aware program representation that encapsulates information reconstructed from executables in an abstract and retargetable manner to achieve scalability.
  • Another aspect of this invention relates to how application parallelism can be exploited in processors without significantly increasing load capacitances. If parallelism is achieved but with an increase in load capacitances, due to hardware complexities, the advantage of improved performance is offset by the resultant much higher power consumption. Current state-of-the-art solutions to expose parallelism are not energy efficient. As such, many of today's low-power processors are single issue.
  • Incorporating compiler information to enable issuing multiple instructions in parallel with a Very Large Instruction Word (VLIW) format has been shown to be detrimental to energy consumption. The term VLIW refers to the size of each instruction that is executed by a processor. This instruction is very long in comparison to the instruction word size utilized by most current processors.
  • Energy inefficiency in a VLIW processor is often attributed to the fixed wide-issue instruction set format; in many applications or program sequences there is not enough parallelism to fill all the instruction slots available in a VLIW instruction.
  • In fact, on average, there is typically very little instruction-level parallelism (ILP) available. As noted in the literature, typical applications have an average ILP level of less than two; thus, a 4-way VLIW would have on average two of its instruction slots unutilized. The unused slots would contribute to unnecessary instruction fetches and instruction-memory energy consumption. Higher ILP levels are fundamentally limited by true data dependencies. While speculation-based techniques can improve ILP levels, runtime speculation has an energy cost that typically offsets the benefits of the higher ILP.
  • As noted in the literature, energy consumed by the instruction memory as well as fetch energy are a significant fraction of a processor energy consumption. For example, a state-of-the-art ARM10 processor has been reported to consume 27% of its total energy in the instruction memory system.
  • Other systems such as superscalar processors attempt to discover parallelism at runtime with significant hardware support. This support reduces the energy benefits obtained with parallel execution. Simply, the performance benefits are more than offset by the increase in load capacitances that increase power consumption.
  • In one aspect, the present invention solves the problem of exposing parallelism without requiring significant hardware support, such as is required in superscalar designs, and without having a fixed wide-issue instruction format, such as in VLIW designs. The solution is adaptive and compiler driven.
  • It works by incorporating control bits into the binary to issue instructions in parallel on only selected sequences of instructions, on compiler demand. The approach could be limited to sequences where there is enough parallelism and when is considered or estimated to be good for energy efficiency. Thus, parallelism encoding can be limited to critical program paths, typically a relatively small fraction of the instructions in a binary, to improve energy efficiency.
  • In addition, if other compiler-managed optimizations are incorporated, such as for energy reduction purposes in the memory system, the added instruction bits for the various optimizations could be encapsulated into one or more new control instructions or control data. If the control is implemented with instructions, both regular instructions that are extensions to the regular ISA or co-processor instructions can be used.
  • In one embodiment, a solution to incorporate control information is to use the co-processor interface, that is, without requiring changes to the processor's regular instruction set. The inserted instructions may be folded, i.e., extracted early, in the prefetch queue before entering the processor pipeline, in a somewhat similar manner to zero-cycle branches in some architectures, e.g., ARM10. Such a solution removes pipeline bubbles that might otherwise be caused by the control instructions. An advantage, therefore, of using co-processor instructions is that one could easily add such control to existing processor cores. In one embodiment that is implemented within an ARM 10 design, each such control instruction would enable the encoding of 21 bits worth of control information.
  • Control information may be added per a sequence of instructions, such that the code dilution overhead of static control could be amortized across several different optimizations and for several instructions in the sequence. The sequence where optimization is applied can be determined with static analysis or other means such as profiling. A control instruction is typically inserted before the controlled instruction sequence.
  • Energy increase due to the extra fetches can be minimized with compiler-driven instruction memory optimizations, for example, by almost always fetching control bits from more energy efficient smaller cache partitions, driven by compiler decisions. One aspect of this invention demonstrates such capability.
  • Due to the compiler-driven nature of the solution, the impact of control overhead can be kept very small. In our experience, in one embodiment, such control energy overhead could be kept below 1%-2% if instruction memory energy optimizations are included, while providing energy optimizations in the range of 30%-68% if several techniques in different processor domains/components are included.
  • SUMMARY
  • The executable-level modification or executable re-compilation, and compiler-architecture interaction based processor framework described herein address the foregoing need to reduce energy consumption in a practical and flexible manner. The approach provides energy savings without adverse effects on performance and with scalability, to different processor instructions sets, and easy integration with other compilation tools. In fact, the framework in its preferred embodiment, when incorporating support for compiler-driven parallel issuing of instructions, improves performance.
  • The framework, in one of its embodiments, eliminates the need for reengineering of source-level compilers to target energy efficiency. The framework can be used in, but is not limited to, converting existing executables where source codes are not always available to achieve a more energy efficient operation.
  • The executable-level re-compilation approach could also transform static libraries that may be part of an executable, or even dynamic libraries. Sources of such libraries are typically not available at the time of source-level compilation of applications, and, therefore, would not be affected by source-level compilation based energy optimizations. In one aspect, this invention enables the global optimization of all application codes together, including libraries, for example, to target energy reduction.
  • In general, there might be several compilers available for one particular processor or an instruction set architecture. The approach based on executables can be easily integrated with some or all of these compilers without requiring changes in the source-level compiler.
  • In one aspect, the framework does this by extracting and utilizing static compile-time information from fully linked and optimized executables, and by modifying the executables according to new design goals such as energy efficiency.
  • In principle, a source-level compiler could augment an executable to support the energy optimization process based on executable re-compilation. The framework may include support for using such information.
  • The framework is also applicable at pre-linking level and on other versions of an executable.
  • The framework could be applied on executables that might contain symbolic information that was inserted for debugging purposes, or, for example, targeting energy optimizations.
  • The framework could be utilized to perform optimizations that are not limited to energy reduction. Examples of optimizations performed may include, but are not limited to, energy, power, performance and security. In general, in one aspect, the framework could be used to improve an application's performance or improve the application's energy-delay product or any other metric that is a combination of execution time and power consumption.
  • The executable-level modifications can be used in combination with added architectural support, or with unchanged architecture, to gain benefits.
  • When used without added architectural support the framework optimizes the instruction stream so as to reduce energy consumption or improve performance on an existing hardware solution.
  • When used with added architecture support, the framework could provide unique opportunities for compiler-architecture based optimizations, by incorporating support for statically-managed architectural mechanisms in a processor, that are typically much more energy-efficient than conventional dynamic mechanisms.
  • Statically-managed access mechanisms use static information to reduce redundancy typically present in conventional instruction execution. In fact, each instruction can be represented as a sequence of micro-operations during execution.
  • Example of such micro-operations may include tag checks in caches, multi-way lookups in associative data arrays, virtual memory related address translations, Translation Lookaside Buffer accesses, and register file accesses. Many of these micro-operations are not necessary if there is related information extracted in the compiler that provides it, or if there is program information that enables a way to replace these micro-operations with more energy-efficient but equivalent ones.
  • Disambiguating an executable is the process of extracting symbolic information and disassembling program instructions from an executable. In one aspect, the invention is directed to a method, for use in a processor, which includes disambiguating the application executable into an intermediate format, performing a number of analyses on this format to statically determine program characteristics, and changing a program's structure and instructions such that the estimated energy consumption of the program after the changes is less than the energy consumption of the original unmodified program. This aspect may include one or more of the following features.
  • The method may include identifying aspects of the program including branches, procedure call points, memory related operations and their locality and reuse patterns, criticality of each instruction in the instruction stream from the point of view of performance, power, and energy consumption, and other similar static information.
  • The method may include static executable disambiguation and late code modification techniques and may include using abstract execution, in addition to static analysis, to help the disambiguation process. Abstract execution is a process based on which short sequences of instructions are executed abstractly using an abstract machine.
  • Abstract execution may be integrated in the compiler and may operate in a forward and/or backward manner. Abstract execution is a process of running a simulation engine during program analysis, to help disambiguate, for example, program-flow or memory access patterns, but is not limited to only those aspects. While in its preferred embodiment this simulation engine is a very small functional simulator kernel optimized to run in a compiler, the framework is not limited to only such a simulator.
  • Furthermore, the method may include inserting a more energy efficient instruction replacing an existing instruction and may include inserting control bits to control hardware structures.
  • In one aspect, the control bits and/or instructions may be implemented as extensions to the regular instruction set of a processor, and/or as co-processor instructions, and/or as data.
  • The control bits may also be implemented as data added to the executable, data that is associated with-segments of instructions and that are accessed during execution by a processor. This aspect may include dedicated architectural support to map instruction sequences to corresponding control bits efficiently. This may include changes to an architecture structure such as the branch target address cache, that would associate the target address with a target static control data, controlling a sequence of instructions such as a basic block, or super block consisting of several basic blocks, starting after the target address. This data could be part of the instruction memory similar, for example, to how constants are used in many instruction sets. A basic block is a sequence of instructions that has no branch instructions except possibly the last instruction and has only one entry point, from other parts of the code, that is at the top of the block.
  • The control bits could control one or several instructions in the instruction stream during execution. A possible objective is to enable energy reduction of these controlled instructions at runtime, by letting the processor know ahead of execution their preferred execution modes to reduce energy.
  • If the control bits refer to controlling several instructions during runtime, such as in a basic block, one control instruction inserted before the block may include control information for a variety of optimizations amortizing its added overhead across many optimizations. The performance overhead of control instructions could be avoided with early folding/removal in processor pipelines with simple pre-decoding logic added to prefetch buffers and instruction fetching. In many predicated architectures a similar early folding is used for example to achieve zero-cycle branches.
  • Another aspect may include optimizing control-bits related fetch energy by compile-time mapping and runtime fetching of the control-bits from an energy optimized memory structure instead of the conventional data and/or instruction cache.
  • In general, in one preferred embodiment, the framework may include modifications to an executable such that dedicated architecture support, that may target energy reduction with the help of static information provided by the framework, can be leveraged.
  • Furthermore, the method may include, but is not limited to, performance-efficient relocation techniques of memory and branch addresses in an executable.
  • As a result, processors using this framework require less energy to operate. Individual instructions may consume less power to execute. Furthermore, the framework is applicable to processors having different architectures and is therefore scalable.
  • The invention can be used to save energy on any type of device that includes a processor. For example, the invention can be used to save energy on personal computers, devices containing embedded controllers, sensor networks, network appliances, hand-held devices, cellular telephones, and emerging applications based on other device technologies.
  • Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Although methods and materials similar or equivalent to those described herein can be used in practice or testing of the present invention, suitable methods and materials are described below. In addition, the materials, methods, and examples are illustrative only and not intended to be limiting.
  • Other features and advantages of the invention will become apparent from the following description, including the claims and drawings.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a block diagram showing the relationship between a source-level compiler, instruction set architecture, and microarchitecture in a processor.
  • FIG. 2 is a block diagram showing the relationship between the executable-level re-compiler, conventional source-level compiler, instruction set architecture, and microarchitecture in a processor.
  • FIG. 3 is a flowchart showing a possible embodiment of an executable-level re-compiler according to the present invention and possible interfacing with source-level compilers.
  • FIG. 4 is a block diagram of an instruction memory system that contains the added extensions for Hotblock access to achieve energy reductions based on compiler-architecture interaction and selective mapping between the L1 I-Cache and the Hotblock cache.
  • FIG. 5 is a flowchart showing an example of a procedure as seen and analyzed by the compiler, in one embodiment, to achieve energy reduction in the instruction memory system.
  • DESCRIPTION
  • In the embodiments described herein, a processor framework uses compile-time information extracted from an executable and the executable is then transformed so as to reduce or enable reduction of energy or power consumption, and/or improve performance in a processor. In one embodiment, a reduction can be achieved without requiring special architecture support. In another embodiment, dedicated architecture support could provide unique optimization opportunities based on compiler-architecture interaction. In one aspect, this includes statically managed energy-efficient access mechanisms, such as in the instruction memory, and energy-efficient compiler-driven parallel instruction issue management techniques. This architectural support may be controlled through either executable compilation or source-level compilation. The executable compilation is a method described in the invention.
  • Referring to FIG. 1, a compiler 10 is a software system that programs circuitry to translate applications from high-level programming languages (e.g., C, C++, Java) into machine specific sequences of instructions. An instruction set architecture (ISA) 12 is a set of rules that defines the encoding of operations into machine specific instructions. The ISA acts as the interface between compiler (10) and the microarchitecture (14). A computer program is a collection of machine level instructions that are executed to perform a desired functionality. Micro-architectural (or architectural) components 14 comprise primarily hardware and/or software that are used during execution of the program. The actual machine can be a microprocessor or any other device that is capable of executing instructions that conform to the encoding defined in the ISA.
  • Compile-time refers to the time during which the program is translated from a high-level programming language into a machine-specific stream of instructions, and it is not part of execution or runtime. Runtime is the time it takes to execute translated machine instructions on the machine. Compilation is typically performed on a different host machine than execution and it is done on the source program. Energy consumed during compilation does not therefore contribute to the energy consumption of the device targeted.
  • Executable-level re-compilation is a process that uses an application's executable as input and performs analysis and modifications at the executable-level. Executable-level compilation is similar to source-level compilation in that it is performed on a different host machine than execution and that during compilation one does not consume energy in the device targeted with the compiled application.
  • Referring to FIG. 2, an executable-level re-compiler or executable-level compiler 24 is a software system that programs circuitry to translate applications from executable-level into machine-specific sequences of instructions 26. Components 26 and 28 are similar to the components 12 and 14 in a conventional compiler system as shown in FIG. 1.
  • Scanning an Executable
  • In a preferred embodiment, a module provides a simple interface for extracting program information from a program executable—refer to 34 in FIG. 3. Apart from the instructions and static data, section and symbolic information may also be extracted. This could be information that is available in an executable as part of the instruction stream or that is inserted during source-level compilation to facilitate optimizations at the time of executable-level compilation.
  • There are a handful of executable file formats used in the industry today, such as ELF, COFF and PECOFF. For example, ARM-ELF defines ARM-specific extensions to the ELF (Executable and Linking Format) standard. In a preferred embodiment, such a module would provide a common interface for accessing executable files in some of these different formats. In one embodiment of this invention, these extensions have been supported.
  • Disambiguating an Executable
  • In one embodiment of this invention the executable file is analyzed by a binary scanning tool in order to gain information about the various sections and any other symbolic information that may be available. This information is used in order to create a version of the program based on an energy-focused Binary Intermediate Format or BIF, shown as 36 in FIG. 3.
  • BIF is an abstract representation that facilitates easy retargetability of the analysis and transformation techniques to different instruction sets. It provides necessary information organized in inter-related structures to help perform sophisticated program analyses and transformations.
  • Once program analyses and optimizations have been run, the optimized BIF object can be converted back into an executable of the same type as the original one or possibly another type with a different instruction set—see 42 in FIG. 3.
  • In general, the BIF object may be made up of many procedures or similar program constructs. These procedures may contain a graph of basic blocks or super-blocks, their edges denoting the control flow of the program.
  • The basic blocks contain the instructions that are executed in the application. Various information, such as registers, immediates, instruction type, addressing types, condition flags, energy-efficient execution/strength related conditions, etc., may be included about each instruction.
  • Once the BIF object has been created, the generated Control Flow Graph (CFG) of the program is subject to many different types of analyses to collect further static program information, shown as 52 in FIG. 3. During later analysis, other types of representations may be constructed to enable for example detection of program dependencies and ease program transformations. These representations might include dependence trees, dominator trees, and representations that enable removal of false dependencies, e.g., single state assignment form.
  • One of the initial analyses may be the loop analysis. This analysis may use a dominator algorithm to find all of the natural loops in the program. Additionally, induction variables, loop footers, step functions, loop-carried dependencies, early exit points, and memory access stride patterns may be identified and the BIF object updated with that information.
  • The idea of criticality may now be introduced. Criticality is used to estimate which of the program blocks are more critical to optimize. For example, blocks in loops are often more critical than blocks outside loops. In one embodiment, blocks in loops are assigned an initial local criticality and a global weight for example based on the depth of the loop they exist in, the procedure context in which they might be used, their probability of being run based on static branch prediction, their contribution to overall energy consumption, and additional heuristics.
  • With all of the local criticalities set, a global pass may be run to create a final global criticality value for each of the basic blocks in the program. The blocks in the procedures are updated on the basis of the criticalities of the blocks that call their respective procedures. Once this global criticality is set, a weight analysis may be run. This analysis assigns blocks in a program a global weight.
  • In one embodiment, weight may be based on the procedure it is in and its static probability of the block being run, assuming a start point at the beginning of its procedure.
  • After a BIF object is created that contains disambiguated symbolic information and the CFG, other analyses are run. FIG. 3 shows general analyses 52 which may be run on a BIF object before power-specific analyses 38 are run. Along with the specific analyses, the ability to use abstract symbolic execution 40 also exists.
  • Abstract execution may be used during various disambiguation phases. It may be used, but not limited to, in forward mode as a fast functional simulation kernel, or as a back-tracking tool on the CFG to disambiguate ambiguous program structures such as call points and branches that have register operands.
  • Referring to FIG. 3, the executable re-compiler 30 can be integrated with various source-level compilers in the front-end 48 that have source files 46 as inputs. The output of the front-end system is in various binary executable formats, such as used in input 32. The backend system 50 is responsible for transforming the executable input into an energy-aware binary 44 through a number of analysis and transformation passes.
  • Energy-Efficient Modifications Requiring no Architecture Support
  • In general, the framework could be used without requiring any modifications in a processor hardware.
  • In one embodiment, after a BIF object is created that may contain some or all of the disambiguated symbolic information and the CFG, energy-related analyses may be run. Along with the specific analyses, the ability to use abstract symbolic execution, for example, to determine data memory access patterns, can exist.
  • In one aspect, these analyses may include local and global analyses to perform instruction scheduling. In one aspect, the blocks that have been determined as consuming more energy, during criticality analyses, may be optimized in favor of blocks that are determined as less critical. As such, energy consumption may be increased on blocks that are determined as less critical or such blocks may not be targeted at all. Such increase in fact is to reduce the consumption elsewhere in blocks that are more critical to overall energy consumption.
  • Energy-focused instruction scheduling aims to arrange instructions or modify sequences of instructions to reduce energy. This could include rearranging instructions such that pipeline bubbles between dependent instructions are removed, such that instructions with lower energy/power consumption are used whenever possible, and such that architecture support that is present in a processor and that could reduce energy consumption can be better utilized.
  • In one embodiment, an example of such existing architecture support includes tag reduction techniques, such as used for example in an ARM 10 processor, where tag access can be removed to save energy whenever the instruction or data access is found in the same cache line as the previous memory access. Instruction scheduling may optimize for such scenarios.
  • Additional techniques can take into consideration branch folding scenarios to remove branching related overhead. Branch folding is a mechanism that requires folding the condition of a branch into a following instruction and removing the branch from the processor pipeline. If the branch is predicted correctly, typically determined when the following instruction reaches the execute stage, the branch effectively takes zero cycles to execute.
  • Other techniques group memory accesses together from several iterations to utilize more energy-efficient load-store multiple operations instead of individual loads and stores, such as present in some instruction sets.
  • Additional techniques may include energy-focused software pipelining and loop transformations. Such techniques can be applied to remove pipeline bubbles between dependent instructions with issue-distances larger than one cycle.
  • In such analyses, critical loop iterations may be transformed such that instructions from various loop iterations are pipelined or interleaved to reduce energy and/or improve performance. Loop iterations could be rearranged in a manner that reduces energy. False dependencies might be removed both within and across iterations. This can be accomplished with software register renaming, occasional loop-unrolling, hyperblock formation to eliminate non-critical control-flow, and other techniques. These techniques may be followed by a register allocation pass.
  • In one aspect, such transformations may be combined with an energy-focused global instruction scheduling, that involves code motion, to further reduce energy consumption on blocks that are on critical paths.
  • A global instruction scheduling rearranges instruction order such that estimated total energy consumption is reduced. It may increase energy consumption on non-critical paths in order to reduce energy on critical execution paths.
  • In one embodiment of the executable-level compilation for energy efficiency that has been implemented, targeting a leading 32-bit embedded microprocessor design from ARM, significant energy reduction could be achieved without requiring added architecture support. This reduction has been noticed for a wide range of important applications including video, audio, graphics, security, office automation, compressions and decompression.
  • Energy Optimizations Using Architecture Support
  • A number of analyses and optimizations could be performed targeting reduction of energy consumption based on dedicated architectural support that can be added to a processor.
  • In one aspect this may include, but it is not limited to, techniques that leverage statically managed energy-efficient hardware. Next, we present a number of such mechanisms. The framework is however not limited to only those that are described here. The compiler support can be implemented either through source-level or with executable-level re-compilation. The approach is not limited to using executable compilation.
  • On-Demand Static Issue (OSI) Processing and its Control
  • In one embodiment, energy consumption may be reduced by determining at compile time which instructions can be executed in parallel, without requiring special hardware disambiguation techniques, and adding at compile-time control information into the instruction stream ahead of their execution. In one aspect, such an approach can be integrated with other energy optimizations, resulting in the control overhead being amortized across many different, for example energy-related, optimizations in a processor.
  • In a superscalar processor design, parallelism extraction and scheduling is performed with hardware techniques; while superscalars can provide good improvement in performance, such designs are energy inefficient due to the runtime hardware support required to find and control parallel execution. Such hardware support is required, for example, to extract parallelism from instructions, hardware renaming, and reordering of instructions. Embedded processor manufacturers are reluctant to add parallelism via such an approach to their designs. This is because the increased complexity of the added hardware offsets the benefits of improved performance, due to the increase in load capacitances that increase power consumption.
  • By contrast, the parallelism method and processing system that is provided in this invention is on-demand and controlled fully statically. It is referred to as on-demand static issue (OSI) parallelism in the remaining text.
  • In comparison with compiler-managed techniques such as VLIW (Very Large Instruction Word) architectures, the OSI technique could be used selectively in code sequences where there is significant instruction-level parallelism and where the overall energy efficiency is estimated to improve, and not applied in codes where there is little parallelism and thus no energy benefit at runtime. As the parallelism is encoded for several instructions ahead of their execution, when parallelism is not exploited, the corresponding execution units can be put instead on standby. A key reason OSI is highly energy-efficient is because it has a minimal impact on the hardware. Moreover, when there is no parallelism in the program, the approach does not impact on the processors energy efficiency. The OSI method is selectively used to achieve as much energy reduction as possible.
  • The OSI solution does not affect significantly load capacitances in processor pipelines, as most of the support required is in the compiler where no runtime-related energy is consumed. The required hardware support could include added read and write ports on the register file and the ability to decode and fetch multiple instructions per cycle.
  • OSI does not require a fixed multi-issue instruction format similar to a VLIW design. In fact, a processor that supports OSI is backward compatible with codes that do not expose OSI parallelism: another key practical benefit.
  • The control bits required for OSI depend on the level of parallelism targeted, but could be as few as one bit per group of instructions specified to be issued in parallel. In a 2-way OSI embodiment it would be sufficient to add one bit per group, or three bits in a six-instruction long basic block. Other types of encodings are however also possible.
  • In a preferred embodiment of the invention, the control bits required by OSI could be combined with control bits required for other optimizations.
  • The control can be encapsulated for an instruction sequence such as a basic block or super block. This way, static control overhead due to the code dilution is optimized across many other, for example energy related, beneficial optimizations.
  • The OSI parallelism approach would also be applicable to existing processor designs as it can be an add-on component. A processor that would be equipped with such a feature would be backward compatible with compilers that do not expose parallelism at compile time; that is, previously compiled executables could also be run unmodified on such a processor. This feature makes OSI an easy upgrade on simple embedded designs where backward compatibility is often required to be preserved due to market constraints.
  • In one possible embodiment that we present next, the OSI-related compile-time parallelism analysis is broken up into three different schemes. The first scheme finds the parallelism that is already present in a basic block. The second global scheme reschedules the instructions in several basic blocks globally, to bring out more parallelism. A third approach, is based on a basic block and hyperblock-level software-pipelining technique to expose more parallelism in critical loops. Codes that have extensive control-flow and complicated do-across loop-structure, such as having early exit points and loop-carried dependencies, can also be handled.
  • The first, simplest, parallelism scheme traverses the program, performing the analysis on each block that has already been annotated as a critical block. Once a critical block is found, the analysis starts with the first two instructions, in a 2-way OSI embodiment. The two instructions are first checked to see if they could possibly run in parallel given the restrictions of the second OSI pipeline. The types of operations supported in the second pipeline are implementation or embodiment specific.
  • For simplicity of describing the techniques we assume 2-way OSI pipelines, however, this is not a limitation—any number of additional execution units and with various capabilities can be added, depending on application and vertical markets targeted.
  • The checks that are made for the second pipeline in a possible embodiment are as follows. In one of its aspects, instructions cannot be run in parallel only if: the first instruction is not conditional and the second instruction is (the status bits could be affected); either of the instructions contain the Program Counter; either of the instructions are branch instructions; neither of the instructions is of type Data Processing; both instructions are multiply instructions; one instruction is a multiply and the other is not a data processing instruction.
  • These checks reflect a design where the second OSI pipeline only has limited capabilities to execute certain type of arithmetic a logical instructions. This is not a limitation: it is the choice of the designer to decide what capabilities to have in each pipeline, or how many pipelines to add.
  • There are also special instructions in different architectures that might not be run in parallel (e.g., saturated add/sub in ARM (QADD,QSUB), state changing instructions in ARM (MSR, MRS)).
  • If the instructions can be run in parallel, given the hardware constraints, they are then checked for inter-instruction dependencies. This dependency analysis starts by checking the second instruction for dependencies on the first instruction. Read-After-Write (RAW) hazards as well as Write-After-Write (WAW or output) and Write-After-Read (WAR or false) hazards are dependencies that typically prevent the instructions from being run in parallel. Software register-renaming techniques in the compiler can be used to eliminate both inter- and intra-iterations-based output and false dependencies.
  • If the pair of instructions passes both the pipeline restrictions and the dependency tests, there is one final check that can be made. This is another dependency check, only this time, the next instruction in the basic block, i.e., the 3rd instruction in this example, is checked for dependencies with the first. This check is made because if there is a dependency between the first and the third, there might not always be a speedup if the first and second were run in parallel. If all checks are passed, the first and second instructions are annotated to be run in parallel and at code generation, the necessary control bits are inserted into the control instructions.
  • This process is repeated until all the instructions in the basic block have been analyzed with their following instruction.
  • A second scheme for OSI parallelism, instead of taking the instructions in the order the original performance compiler put them, it reschedules the instructions in a manner to bring out more parallelism. This scheme can be complemented with a third approach based on a software pipelining, to expose more parallelism in loops. There are many other ways parallelism can be exposed and the embodiment described here is not intended to be limiting.
  • The OSI instruction rescheduling pass builds a dependency graph for the instructions in the basic block. Along with this dependency graph, each instruction is checked against all of the following instructions and noted whether or not it could be run in parallel with them. Once this is complete, a modified scheduling algorithm is used to reschedule the instructions.
  • The rescheduling algorithm used starts with the instructions that have no incoming edges (instructions that don't depend on any other instructions). If there is more than one instruction in this group of candidates, the instruction with the earliest original place in the basic block is chosen to be scheduled. After an instruction is scheduled, all of the outgoing edges (instructions that depend on the instruction that was scheduled last) are possible candidates. These possible candidates are only deemed candidates if all of their incoming edges have already been scheduled.
  • If there is more than one instruction that could be run in parallel with the previously scheduled instruction, the instruction with the earliest original placement is selected.
  • There is an additional step that may be necessary in instruction sets that support conditional execution. To ensure correctness, the instruction that alters the status bits, which the conditionally executed instructions depend on, is always scheduled as late as possible. This ensures that the conditionally executed instructions that follow will have the correct status bits set. This ensures that the conditionally executed instructions that follow will have the correct status bits set.
  • Compiler-Inserted Control to Reduce Energy in the Instruction Memory
  • This part of the invention relates to compiler-architecture interaction based approach to reduce energy consumption in the instruction memory system.
  • An optimization may target reduction of energy in the instruction memory by directing instruction memory accesses to other more energy-efficient memory structures than the conventional memory structures.
  • This control can be incorporated by adding one or more static control bits per controlled sequences of instructions. In fact, a scheme that uses one bit per controlled sequence is possible.
  • In one embodiment, shown in FIG. 4, there are two memory structures used in the memory architecture—both are compiler controlled. A first structure is a small cache or an SRAM memory or a partition of the first level cache, called the Hotblock 82; a second structure is equivalent to a conventional first level cache 98, and requires either a conventional lookup 74 or could avoid tag-lookup 74 if it is accessing data in the same cache line as in the previous access, shown as mechanism 80 and 96. In a different embodiment the first level cache could be a Ram-Tag based cache instead of the CAM-tag based shown in the figure. A key difference between the two cache types is that in a CAM-based design the tag-check is performed with a Content Addressable Memory (CAM) structure where tags in each way in a set are compared within the CAM after which the correct word-line is selected if the operation results in a cache hit. By contrast, the Ram-based tag structure would require indexing that is performed after word-line decoding from the input address bits. This indexing is performed typically in parallel for the data-array and tag-array.
  • Another embodiment may have multiple levels of caches and the addressing of the caches may be physical or virtual.
  • In one aspect, the compiler selects to map sequences of instructions, such as a basic block, to either of these structures. When a compiler maps sequences of instructions to the smaller Hotblock structure 82, enabling signal 90, instruction memory related energy consumption can be significantly reduced due to the reduction of access energy. This reduction is achieved because the Hotblock cache has a much smaller access energy compared to the first level cache. Clearly, the more accesses are mapped to the Hotblock cache correctly, that is, without causing a Hotblock cache miss, the greater the improvement in energy efficiency.
  • Moreover, cell and bitline related leakage energy could be reduced in the first level instruction cache during a Hotblock access by providing support for putting L1 cache lines that are mapped to the Hotblock cache into low-leakage modes.
  • The benefit of a compiler-driven strategy for leakage reduction is that it would allow controlling tradeoffs between awakening energy/delay, performance degradation, and leakage power reduction, at a fine granularity and without impacting hardware complexity significantly.
  • Inactivity periods are program dependent, as resource demands change as execution proceeds. When inactivity periods are longer and highly predictable at compile-time, we could select to put the circuit blocks in lowest possible leakage power modes. When the inactivity periods are unknown or speculative, we could instead select to use state-preserving approaches (or no leakage control) that, while saving less energy, have lower awakening costs in case of (inactivity period) mispredictions.
  • Low leakage modes can be based on gating the power supply 94 on cache lines and/or reduced power supply on cache lines, also called drowsy lines, controlled in block 94. Other schemes are also possible; the compiler control can be adapted to various circuit-level implementations to address leakage in SRAM cells, as well as control precharging to reduce leakage in the bitlines. Precharging-related leakage energy can be avoided by precharging only the first level cache bank that contains the memory access, instead of all the banks.
  • The actual leakage power savings depend on the fraction of drowsy cells compared to gated cells in the L1 data array and other factors such as the time periods during which we can maintain low leakage states in L1 cache lines. The leakage power in the Hotblock cache is small given its small size, as leakage power is at first order proportional to the size of the circuit. Another mechanism used, controls cell and bitline leakage during L1 accesses.
  • Bitline leakage is reduced by precharging only the right cache bank whenever the compiler (or the last cache line tag buffer 80) guarantees intra-line cache accesses. Furthermore, instructions that are placed into low leakage modes during previous Hotblock accesses, would remain in low leakage modes until accessed again.
  • With careful compiler orchestration of only mapping the energy critical sequences to the Hotblock structure and reusing the Hotblock across critical loops, a very small cache size can be used. In this embodiment, a cache of 1 Kbyte size provided a sufficient storage for optimizing a wide range of applications studied.
  • Independent of the Hotblock cache size, the compiler can restrict accesses to achieve a very high Hotblock hit rate.
  • If the Hotblock cache integrates protection related to virtual memory, then address translation from virtual to physical, can be avoided by enabling signal 76.
  • The method in this invention can keep the Hotblock miss rate 92 very low by mapping selectively critical sequences of instructions, estimating the required memory footprint, and managing it at fine granularity with control bits inserted into the instruction stream at fine granularities.
  • Furthermore, the control can be integrated with other energy optimizations based similarly on compiler-architecture interaction: any overhead from static control could be therefore amortized across several energy optimization. The negative effects of the control, if any, are more than compensated for by the energy reductions obtained in several critical processor components.
  • In the embodiment evaluated we have found that the compiler could limit the miss rate in such a Hotblock structure to below 1%. In one embodiment, this has been demonstrated for a structure as small as 1 KByte size and for a wide range of applications, including SPEC2000, Media, and Mibench benchmarks. These benchmarks represent a cross-section of typical embedded applications from many industries including telecom, security, media, and automotive.
  • This can be attributed to selecting at compile time only the very critical blocks and by guaranteeing at compile time that thrashing in the Hotblock structure during critical program sequences such as critical loop iterations do not occur.
  • The architecture used can be fully flexible in the way the various structures are ordered. In one preferred embodiment the first level cache 98 can also be accessed directly, depending on compiler information, and it can also be accessed on a miss 94 in the Hotblock structure.
  • The compiler would map selected critical blocks, at a fine granularity, to the Hotblock structure and less critical blocks directly to the first level cache.
  • In this embodiment, a Hotblock miss is looked up in the first level cache. If the entry is found in the first level cache the corresponding entry in the Hotblock structure is updated.
  • A hotblock miss results in a one-cycle penalty. However, with compiler control, the miss rate can be kept very low. Non-critical instructions are directly fetched from the first-level cache avoiding Hotblock misses. The Hotblock cache is reused across instruction sequences such as different loop structures.
  • In general, compiler control decides which one of the memory structures is accessed and for which selected instruction sequences, such that overall energy consumption is optimized. The compiler analysis ranks all basic blocks, or larger blocks, in terms of their estimated contribution to the processor's total energy consumption, to determine the memory structure used.
  • Referring to FIG. 5, key steps of an instruction analysis 100 are shown on a procedure called Proc 57. Flowchart 112 denotes a CFG with basic blocks including flowchart 114 that denotes Proc 57. The next flowchart 116 shows basic blocks with detected loop structures including outer-loop 102 and inner-loop 104 and loop-footer 108 for inner-loop. The outer-loop is also shown in flowchart 120 as 118. As shown, the outer-loop encapsulates the inner-loop. During analysis in flowchart 120, weight and loop-related criticality is calculated for each basic block. Weight is recalculated after each branch. Depending on embodiment, a weight is attributed depending on the position of the block in the CFG. Criticality in the procedure is added based on loop nest information extracted during analysis on Flowchart 116. Flowchart 122 shows all blocks updated with weight and criticality by also taking into consideration incoming procedure criticalities such as due to procedure 126 that has an incoming edge to procedure 57. After this global criticality analysis, the most critical basic blocks 110 are determined as shown in flowchart 124. These are the blocks that are ultimately mapped to the Hotblock cache. If their footprint exceeds the available space, for example due to fragmentation in the cache, the blocks are mapped in order of their criticality. Fragmentation and other aspects such as cache line size and cache associativity can be taken into consideration during the mapping to avoid overflowing the available space in the Hotblock cache and causing unwanted cache misses. This analysis shows an example with one Hotblock cache. Other embodiments can be based on several Hotblock caches and of different sizes. In such cases, the analysis would map the most critical blocks starting from the smallest Hotblock cache and so on. This organization is not intended to be limiting. Any hierarchical organization of memory structures can be mapped to blocks in the same fashion based on a compiler-selected criticality (or optimization) criterion.
  • Other Compiler-Inserted Control for Energy Reduction
  • Furthermore, data memory accesses could be directed similarly to more energy efficient access mechanisms to avoid tag-lookups and associative data-array accesses, or to access more energy-efficient memory structures such as a smaller cache or a small cache partition. This may include determining the memory access strides or the criticality of an instruction in an instruction stream. Control information could be added, encoding such sequences of instructions, to enable streamlining a data memory access.
  • Unnecessary register file accesses can be avoided by exposing the register access to the compiler and by avoiding register access for registers that are short-lived by accessing the value directly from added buffers in a design, such as accumulators and bypass latches.
  • In one aspect, the approach enables replacing dynamic bypass networks in processors, with compiler controlled explicit bypassing.
  • In general, in one aspect, dynamic branch prediction techniques could be complemented or replaced by energy-focused static branch prediction. Additionally, compiler-managed prefetching or prefetching hints could be incorporated to reduce cache related energy consumption in designs that otherwise aggressively use prefetching.
  • Encapsulating Compiler Inserted Control for Several Optimizations
  • All these mentioned optimizations and others not described in this embodiment could be integrated into a processor-wide solution and controlled with one or more control instructions per sequence of instructions. This would reduce the control overhead as the code-dilution overhead would be amortized across many different energy optimizations.
  • In one aspect, the control bits could be added as data to an executable. In one aspect, this data can be accessed through a small dedicated hardware mechanism that would associate branch targets to addresses where control bits are located in the data memory, for example through a hashing mechanism, to fetch the corresponding control bits. A static decode unit would decode these bits and generate the control signals for the associated sequence of instructions.
  • During execution, a sequencing mechanism would control both processor resources and select appropriate energy efficient access mechanisms corresponding to the encodings decoded from the compiler-generated control bits.
  • The control information can also be incorporated as regular extensions to the instruction set or as co-processor instructions.
  • Minimal added pre-decoding logic could be used to remove the control instructions before entering processor pipelines.
  • Transformations to the Binary and Relocation of Executable
  • Modifications performed on the executable may require relocation of procedure call addresses and memory operations as well as code and other sequences in an executable.
  • A method in this invention provides such a relocation in a performance-efficient way in case ambiguous branches or memory accesses exist in the executable. Ambiguous branches or memory accesses may refer to situations when addresses are not known at compile time.
  • The challenge is that ambiguous call-points may refer to any procedure in the program; thus if the start point of a procedure is changed in the executable the ambiguous call point may execute incorrectly after relocation is performed.
  • In one embodiment, a solution is provided based on the observation that if the original program addresses in the executable of these ambiguous instructions are kept unmodified and all procedures entry points are kept unmodified after relocation, the relocation can be easily accomplished. This can be achieved easily by moving some portion of a procedure to the end of the executable.
  • A sample implementation, including the optimizations outlined and performed at executable-level, achieves energy reduction of 26% to 68% when implemented to extend a leading embedded low-power processor.
  • OTHER EMBODIMENTS
  • The invention is not limited to the specific embodiments described herein. The invention is not limited to reducing energy consumption. It could also be used, but is not limited to, to improve performance or improve security.
  • Other types of compiler analyses and/or architecture support may be used. The invention may be applied to control any appropriate component of a processor. The optimizations and/or analyses may be performed in a different order and combined with other techniques, in other embodiments. There are different forms of energy consumption, for example such as dynamic or leakage power. The invention is not limited to one source of energy consumption; compiler control for both leakage and dynamic energy can be accomplished as described.
  • Other embodiments not described herein are also within the scope of the following claims.

Claims (22)

  1. 1. A method, for use in a processor context, comprising of:
    analyzing a program executable at compile time;
    creating an intermediate program representation of the executable;
    analyzing the intermediate representation;
    performing a transformation on the intermediate representation such that a design objective is optimized;
    generating optimized program executable from the intermediate representation;
  2. 2. The method of claim 1, further comprising of transforming an executable to reduce energy consumption in a processor.
  3. 3. The method of claim 1, further comprising of transforming an executable to improve performance in a processor.
  4. 4. The method of claim 1, further comprising of incorporating information related to energy consumption into an intermediate program representation of an executable.
  5. 5. The method of claim 2, wherein an instruction sequence of one or more instructions is replaced with another instruction sequence of one or more instructions to reduce energy.
  6. 6. A method, for use in an application or processor context, comprising of:
    analyzing a program executable at compile time;
    creating an intermediate program representation of the executable;
    analyzing the intermediate representation;
    estimating energy consumption in a processor for an instruction sequence of one or more instructions in an application.
  7. 7. The method of claim 6, further comprising of generating an output to visualize energy consumption in an application component.
  8. 8. The method of claim 6, further comprising of identifying an instruction sequence of one or more instructions most likely to contribute significantly to energy consumption.
  9. 9. The method of claim 6, further comprising of:
    obtaining runtime statistics about an application and its activity in a processor through simulation;
    combining simulation information and compile-time information to obtain energy estimations of one or more instructions.
  10. 10. A method wherein:
    control information is added at compile time related to execution of a sequence of instructions, of one or more instructions, and controlling plural architectural components during execution;
    control information related to a sequence of instructions, of one or more instructions, encoded into a processor instruction.
  11. 11. The method of claim 10 wherein a control information is inserted targeting energy reduction in a processor.
  12. 12. The method of claim 10 wherein control information is encoded into an instruction part of an instruction set architecture.
  13. 13. The method of claim 10 wherein control information is encoded into a coprocessor instruction.
  14. 14. A processor framework of claim 10 wherein control instructions are inserted for selected instruction sequences and removed at runtime before entering a processor pipeline.
  15. 15. The method of claim 10 wherein control information is inserted as program data.
  16. 16. A method wherein control information inserted at compile time comprises of:
    which instructions in an instruction sequence are to be issued in parallel at runtime;
    additional information related to one or more of the following aspects:
    which instruction memory structure an instruction sequence should be fetched from,
    length of the instruction sequence,
    branch prediction mechanism, and
    data memory access mechanism.
  17. 17. A processor framework of claim 10 comprising of a compiler-encoded instruction-level parallelism approach wherein instructions in a sequence of instructions are issued in parallel at runtime on compile-time selected blocks of instructions.
  18. 18. A method of claim 16 wherein coprocessor instructions encode instruction level parallelism.
  19. 19. A method, wherein control information is inserted at compile time to determine explicitly which instruction memory structure an instruction sequence should be fetched from.
  20. 20. The processor framework of claim 19 comprised of:
    one or more Hotblock instruction memory structures exposed to the compiler;
    a first level memory structure exposed and controlled by a compiler;
  21. 21. An electronics system that implements claim 20.
  22. 22. A processor framework of claim 20 where leakage energy reduction is optimized in a memory structure during a time a Hotblock structure is active.
US10967989 2003-10-29 2004-10-18 Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control Abandoned US20050114850A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US51526003 true 2003-10-29 2003-10-29
US10967989 US20050114850A1 (en) 2003-10-29 2004-10-18 Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10967989 US20050114850A1 (en) 2003-10-29 2004-10-18 Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control
US14212737 US9569186B2 (en) 2003-10-29 2014-03-14 Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control
US15410567 US20170131986A1 (en) 2003-10-29 2017-01-19 Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US14212737 Continuation US9569186B2 (en) 2003-10-29 2014-03-14 Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control

Publications (1)

Publication Number Publication Date
US20050114850A1 true true US20050114850A1 (en) 2005-05-26

Family

ID=34594822

Family Applications (3)

Application Number Title Priority Date Filing Date
US10967989 Abandoned US20050114850A1 (en) 2003-10-29 2004-10-18 Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control
US14212737 Active 2026-01-07 US9569186B2 (en) 2003-10-29 2014-03-14 Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control
US15410567 Pending US20170131986A1 (en) 2003-10-29 2017-01-19 Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control

Family Applications After (2)

Application Number Title Priority Date Filing Date
US14212737 Active 2026-01-07 US9569186B2 (en) 2003-10-29 2014-03-14 Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control
US15410567 Pending US20170131986A1 (en) 2003-10-29 2017-01-19 Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control

Country Status (1)

Country Link
US (3) US20050114850A1 (en)

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040010782A1 (en) * 2002-07-09 2004-01-15 Moritz Csaba Andras Statically speculative compilation and execution
US20050108507A1 (en) * 2003-11-17 2005-05-19 Saurabh Chheda Security of program executables and microprocessors based on compiler-arcitecture interaction
US20050132238A1 (en) * 2003-12-16 2005-06-16 Murthi Nanja Performance monitoring based dynamic voltage and frequency scaling
US20050172277A1 (en) * 2004-02-04 2005-08-04 Saurabh Chheda Energy-focused compiler-assisted branch prediction
US20050229149A1 (en) * 2004-03-17 2005-10-13 Munter Joel D Power and/or energy optimized compile/execution
US20050283351A1 (en) * 2004-06-18 2005-12-22 Virtutech Ab Method and system for partial evaluation of virtual address translations in a simulator
US20060170675A1 (en) * 2005-02-01 2006-08-03 Samsung Electronics Co., Ltd. Method and apparatus for rendering 3D graphics data
US20070136720A1 (en) * 2005-12-12 2007-06-14 Freescale Semiconductor, Inc. Method for estimating processor energy usage
US20070157044A1 (en) * 2005-12-29 2007-07-05 Industrial Technology Research Institute Power-gating instruction scheduling for power leakage reduction
US20070294181A1 (en) * 2006-05-22 2007-12-20 Saurabh Chheda Flexible digital rights management with secure snippets
US20080126766A1 (en) * 2006-11-03 2008-05-29 Saurabh Chheda Securing microprocessors against information leakage and physical tampering
US20080177993A1 (en) * 2006-08-08 2008-07-24 International Business Machines Corporation System, method and program product for control of sequencing of data processing by different programs
US20100299662A1 (en) * 2009-05-20 2010-11-25 Microsoft Corporation Resource aware programming
US7853812B2 (en) 2007-02-07 2010-12-14 International Business Machines Corporation Reducing power usage in a software application
US20110078655A1 (en) * 2009-09-30 2011-03-31 International Business Machines Corporation Creating functional equivalent code segments of a computer software program with lower energy footprints
US20120017201A1 (en) * 2010-07-14 2012-01-19 Rajan Sreeranga P System and Method for Comparing Software Frameworks
US20130111032A1 (en) * 2011-10-28 2013-05-02 International Business Machines Corporation Cloud optimization using workload analysis
US20130117544A1 (en) * 2007-05-16 2013-05-09 International Business Machines Corporation Method and apparatus for run-time statistics dependent program execution using source-coding principles
US20140173206A1 (en) * 2012-12-14 2014-06-19 Ren Wang Power Gating A Portion Of A Cache Memory
US20150074636A1 (en) * 2013-09-06 2015-03-12 Texas Instruments Deutschland Gmbh System and method for energy aware program development
US9411964B1 (en) * 2014-11-24 2016-08-09 Bluerisc, Inc. Characterizing, detecting and healing vulnerabilities in computer code
US9569186B2 (en) 2003-10-29 2017-02-14 Iii Holdings 2, Llc Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control
US9754112B1 (en) 2014-11-24 2017-09-05 Bluerisc, Inc. Detection and healing of vulnerabilities in computer code

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150309779A1 (en) * 2014-04-29 2015-10-29 Reservoir Labs, Inc. Systems and methods for power optimization of processors

Citations (97)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4003033A (en) * 1975-12-22 1977-01-11 Honeywell Information Systems, Inc. Architecture for a microprogrammed device controller
US4067059A (en) * 1976-01-29 1978-01-03 Sperry Rand Corporation Shared direct memory access controller
US4079455A (en) * 1976-12-13 1978-03-14 Rca Corporation Microprocessor architecture
US4138720A (en) * 1977-04-04 1979-02-06 Burroughs Corporation Time-shared, multi-phase memory accessing system
US4181942A (en) * 1978-03-31 1980-01-01 International Business Machines Corporation Program branching method and apparatus
US4255785A (en) * 1978-09-25 1981-03-10 Motorola, Inc. Microprocessor having instruction fetch and execution overlap
US4376977A (en) * 1979-08-27 1983-03-15 U.S. Philips Corporation Computer system with scannable program memory
US4382279A (en) * 1978-04-25 1983-05-03 Compagnie Internationale Pour L'informatique Cii-Honeywell Bull (Societe Anonyme) Single chip microprocessor with on-chip modifiable memory
US4434461A (en) * 1980-09-15 1984-02-28 Motorola, Inc. Microprocessor with duplicate registers for processing interrupts
US4435758A (en) * 1980-03-10 1984-03-06 International Business Machines Corporation Method for conditional branch execution in SIMD vector processors
US4450519A (en) * 1980-11-24 1984-05-22 Texas Instruments Incorporated Psuedo-microprogramming in microprocessor in single-chip microprocessor with alternate IR loading from internal or external program memories
US4577282A (en) * 1982-02-22 1986-03-18 Texas Instruments Incorporated Microcomputer system for digital signal processing
US4592013A (en) * 1981-08-21 1986-05-27 International Business Machines Corp. Method and device for addressing a memory
US4649471A (en) * 1983-03-01 1987-03-10 Thomson Components-Mostek Corporation Address-controlled automatic bus arbitration and address modification
US4665495A (en) * 1984-07-23 1987-05-12 Texas Instruments Incorporated Single chip dram controller and CRT controller
US4720812A (en) * 1984-05-30 1988-01-19 Racal-Milgo, Inc. High speed program store with bootstrap
US4803621A (en) * 1986-07-24 1989-02-07 Sun Microsystems, Inc. Memory access system
US4931986A (en) * 1989-03-03 1990-06-05 Ncr Corporation Computer system clock generator for generating tuned multiple clock signals
US4992933A (en) * 1986-10-27 1991-02-12 International Business Machines Corporation SIMD array processor with global instruction control and reprogrammable instruction decoders
US5021993A (en) * 1987-03-31 1991-06-04 Kabushiki Kaisha Toshiba Device for saving and restoring register information
US5111389A (en) * 1987-10-29 1992-05-05 International Business Machines Corporation Aperiodic mapping system using power-of-two stride access to interleaved devices
US5121498A (en) * 1988-05-11 1992-06-09 Massachusetts Institute Of Technology Translator for translating source code for selective unrolling of loops in the source code
US5127091A (en) * 1989-01-13 1992-06-30 International Business Machines Corporation System for reducing delay in instruction execution by executing branch instructions in separate processor while dispatching subsequent instructions to primary processor
US5193202A (en) * 1990-05-29 1993-03-09 Wavetracer, Inc. Processor array with relocated operand physical address generator capable of data transfer to distant physical processor for each virtual processor while simulating dimensionally larger array processor
US5224214A (en) * 1990-04-12 1993-06-29 Digital Equipment Corp. BuIffet for gathering write requests and resolving read conflicts by matching read and write requests
US5276895A (en) * 1986-09-18 1994-01-04 Digital Equipment Corporation Massively parallel array processing system
US5410669A (en) * 1993-04-05 1995-04-25 Motorola, Inc. Data processor having a cache memory capable of being used as a linear ram bank
US5481684A (en) * 1994-01-11 1996-01-02 Exponential Technology, Inc. Emulating operating system calls in an alternate instruction set using a modified code segment descriptor
US5481693A (en) * 1994-07-20 1996-01-02 Exponential Technology, Inc. Shared register architecture for a dual-instruction-set CPU
US5497478A (en) * 1991-03-20 1996-03-05 Hewlett-Packard Company Memory access system and method modifying a memory interleaving scheme so that data can be read in any sequence without inserting wait cycles
US5524223A (en) * 1994-01-31 1996-06-04 Motorola, Inc. Instruction accelerator for processing loop instructions with address generator using multiple stored increment values
US5598546A (en) * 1994-08-31 1997-01-28 Exponential Technology, Inc. Dual-architecture super-scalar pipeline
US5604913A (en) * 1993-08-10 1997-02-18 Fujitsu Limited Vector processor having a mask register used for performing nested conditional instructions
US5608886A (en) * 1994-08-31 1997-03-04 Exponential Technology, Inc. Block-based branch prediction using a target finder array storing target sub-addresses
US5630143A (en) * 1992-03-27 1997-05-13 Cyrix Corporation Microprocessor with externally controllable power management
US5637932A (en) * 1990-11-27 1997-06-10 Hitachi, Ltd. Power consumption control system
US5638525A (en) * 1995-02-10 1997-06-10 Intel Corporation Processor capable of executing programs that contain RISC and CISC instructions
US5638533A (en) * 1995-10-12 1997-06-10 Lsi Logic Corporation Method and apparatus for providing data to a parallel processing array
US5721893A (en) * 1996-05-14 1998-02-24 Hewlett-Packard Company Exploiting untagged branch prediction cache by relocating branches
US5727229A (en) * 1996-02-05 1998-03-10 Motorola, Inc. Method and apparatus for moving data in a parallel processor
US5737749A (en) * 1996-05-20 1998-04-07 International Business Machines Corporation Method and system for dynamically sharing cache capacity in a microprocessor
US5737572A (en) * 1995-06-06 1998-04-07 Apple Computer, Inc. Bank selection logic for memory controllers
US5742804A (en) * 1996-07-24 1998-04-21 Institute For The Development Of Emerging Architectures, L.L.C. Instruction prefetch mechanism utilizing a branch predict instruction
US5752068A (en) * 1994-08-23 1998-05-12 Massachusetts Institute Of Technology Mesh parallel computer architecture apparatus and associated methods
US5758112A (en) * 1994-10-14 1998-05-26 Silicon Graphics, Inc. Pipeline processor with enhanced method and apparatus for restoring register-renaming information in the event of a branch misprediction
US5758176A (en) * 1994-09-28 1998-05-26 International Business Machines Corporation Method and system for providing a single-instruction, multiple-data execution unit for performing single-instruction, multiple-data operations within a superscalar data processing system
US5857104A (en) * 1996-11-26 1999-01-05 Hewlett-Packard Company Synthetic dynamic branch prediction
US5864697A (en) * 1996-06-28 1999-01-26 Texas Instruments Incorporated Microprocessor using combined actual and speculative branch history prediction
US5864707A (en) * 1995-12-11 1999-01-26 Advanced Micro Devices, Inc. Superscalar microprocessor configured to predict return addresses from a return stack storage
US5870581A (en) * 1996-12-20 1999-02-09 Oak Technology, Inc. Method and apparatus for performing concurrent write operations to a single-write-input register file and an accumulator register
US5872987A (en) * 1992-08-07 1999-02-16 Thinking Machines Corporation Massively parallel computer including auxiliary vector processor
US5875324A (en) * 1995-06-07 1999-02-23 Advanced Micro Devices, Inc. Superscalar microprocessor which delays update of branch prediction information in response to branch misprediction until a subsequent idle clock
US5875464A (en) * 1991-12-10 1999-02-23 International Business Machines Corporation Computer system with private and shared partitions in cache
US5884057A (en) * 1994-01-11 1999-03-16 Exponential Technology, Inc. Temporal re-alignment of a floating point pipeline to an integer pipeline for emulation of a load-operate architecture on a load/store processor
US5887166A (en) * 1996-12-16 1999-03-23 International Business Machines Corporation Method and system for constructing a program including a navigation instruction
US5903750A (en) * 1996-11-20 1999-05-11 Institute For The Development Of Emerging Architectures, L.L.P. Dynamic branch prediction for branch instructions with multiple targets
US6021484A (en) * 1997-11-14 2000-02-01 Samsung Electronics Co., Ltd. Dual instruction set architecture
US6044469A (en) * 1997-08-29 2000-03-28 Preview Software Software publisher or distributor configurable software security mechanism
US6049330A (en) * 1997-08-28 2000-04-11 Oak Technology, Inc. Method and apparatus for optimizing storage of compressed images in memory
US6052703A (en) * 1998-05-12 2000-04-18 Oak Technology, Inc. Method and apparatus for determining discrete cosine transforms using matrix multiplication and modified booth encoding
US6058469A (en) * 1995-04-17 2000-05-02 Ricoh Corporation System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization
US6067609A (en) * 1998-04-09 2000-05-23 Teranex, Inc. Pattern generation and shift plane operations for a mesh connected computer
US6067622A (en) * 1996-01-02 2000-05-23 Moore; Steven Jerome Software security system using remove function to restrict unauthorized duplicating and installation of an application program
US6175892B1 (en) * 1998-06-19 2001-01-16 Hitachi America. Ltd. Registers and methods for accessing registers for use in a single instruction multiple data system
US6178498B1 (en) * 1997-12-18 2001-01-23 Idea Corporation Storing predicted branch target address in different storage according to importance hint in branch prediction instruction
US6212542B1 (en) * 1996-12-16 2001-04-03 International Business Machines Corporation Method and system for executing a program within a multiscalar processor by processing linked thread descriptors
US6216223B1 (en) * 1998-01-12 2001-04-10 Billions Of Operations Per Second, Inc. Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor
US6219796B1 (en) * 1997-12-23 2001-04-17 Texas Instruments Incorporated Power reduction for processors by software control of functional units
US6341371B1 (en) * 1999-02-23 2002-01-22 International Business Machines Corporation System and method for optimizing program execution in a computer system
US6381668B1 (en) * 1997-03-21 2002-04-30 International Business Machines Corporation Address mapping for system memory
US6385720B1 (en) * 1997-07-14 2002-05-07 Matsushita Electric Industrial Co., Ltd. Branch prediction method and processor using origin information, relative position information and history information
US6393520B2 (en) * 1997-04-17 2002-05-21 Matsushita Electric Industrial Co., Ltd. Data processor and data processing system with internal memories
US20030014742A1 (en) * 2001-07-09 2003-01-16 Sasken Communication Technologies Limited Technique for compiling computer code to reduce energy consumption while executing the code
US20030041230A1 (en) * 1998-12-30 2003-02-27 Lihu Rappoport Method and system for branch target prediction using path information
US6529943B1 (en) * 1998-04-24 2003-03-04 Canon Kabushiki Kaisha Server, client, client server system, method for controlling them and storage medium therefor
US6539543B1 (en) * 1999-11-29 2003-03-25 Adelante Technologies, Nv Method and apparatus for compiling source code by flattening hierarchies
US20030066061A1 (en) * 2001-09-29 2003-04-03 Youfeng Wu Method and apparatus for performing compiler transformation of software code using fastforward regions and value specialization
US6550004B1 (en) * 1999-11-05 2003-04-15 Ip-First, Llc Hybrid branch predictor with improved selector table update mechanism
US6560776B1 (en) * 2000-02-18 2003-05-06 Avaya Technology Corp. Software installation verification tool
US6571331B2 (en) * 1999-03-18 2003-05-27 Ip-First, Llc Static branch prediction mechanism for conditional branch instructions
US6675305B1 (en) * 2000-08-04 2004-01-06 Synopsys, Inc. Power saving in a USB peripheral by providing gated clock signal to CSR block in response to a local interrupt generated when an operation is to be performed
US20040010782A1 (en) * 2002-07-09 2004-01-15 Moritz Csaba Andras Statically speculative compilation and execution
US20040010679A1 (en) * 2002-07-09 2004-01-15 Moritz Csaba Andras Reducing processor energy consumption by controlling processor resources
US20040010783A1 (en) * 2002-07-09 2004-01-15 Moritz Csaba Andras Reducing processor energy consumption using compile-time information
US20040015923A1 (en) * 2001-02-16 2004-01-22 Craig Hemsing Apparatus and method to reduce memory footprints in processor architectures
US6687838B2 (en) * 2000-12-07 2004-02-03 Intel Corporation Low-power processor hint, such as from a PAUSE instruction
US6732253B1 (en) * 2000-11-13 2004-05-04 Chipwrights Design, Inc. Loop handling for single instruction multiple datapath processor architectures
US20050066153A1 (en) * 1998-10-12 2005-03-24 Harshvardhan Sharangpani Method for processing branch operations
US20050108507A1 (en) * 2003-11-17 2005-05-19 Saurabh Chheda Security of program executables and microprocessors based on compiler-arcitecture interaction
US6988183B1 (en) * 1998-06-26 2006-01-17 Derek Chi-Lan Wong Methods for increasing instruction-level parallelism in microprocessors and digital system
US7024393B1 (en) * 1999-03-27 2006-04-04 Microsoft Corporation Structural of digital rights management (DRM) system
US7036118B1 (en) * 2001-12-20 2006-04-25 Mindspeed Technologies, Inc. System for executing computer programs on a limited-memory computing machine
US7076638B2 (en) * 2001-09-20 2006-07-11 Matsushita Electric Industrial Co., Ltd. Processor, compiler and compilation method
US7162617B2 (en) * 2003-02-14 2007-01-09 Fine Arc Incorporated Data processor with changeable architecture
US7185215B2 (en) * 2003-02-24 2007-02-27 International Business Machines Corporation Machine code builder derived power consumption reduction
US20080126766A1 (en) * 2006-11-03 2008-05-29 Saurabh Chheda Securing microprocessors against information leakage and physical tampering
US7487340B2 (en) * 2006-06-08 2009-02-03 International Business Machines Corporation Local and global branch prediction information storage

Family Cites Families (156)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3603934A (en) 1968-07-15 1971-09-07 Ibm Data processing system capable of operation despite a malfunction
US4050058A (en) 1973-12-26 1977-09-20 Xerox Corporation Microprocessor with parallel operation
US4042972A (en) 1974-09-25 1977-08-16 Data General Corporation Microprogram data processing technique and apparatus
US4037090A (en) 1974-11-19 1977-07-19 Texas Instruments Incorporated Multiphase clocking for MOS
CA1059639A (en) 1975-03-26 1979-07-31 Garvin W. Patterson Instruction look ahead having prefetch concurrency and pipe line features
US4090247A (en) 1975-08-11 1978-05-16 Arthur D. Little, Inc. Portable data entry device
US4101960A (en) 1977-03-29 1978-07-18 Burroughs Corporation Scientific processor
US4128873A (en) 1977-09-20 1978-12-05 Burroughs Corporation Structure for an easily testable single chip calculator/controller
JPS5616248A (en) 1979-07-17 1981-02-17 Matsushita Electric Ind Co Ltd Processing system for interruption
US4354228A (en) 1979-12-20 1982-10-12 International Business Machines Corporation Flexible processor on a single semiconductor substrate using a plurality of arrays
US4463421A (en) 1980-11-24 1984-07-31 Texas Instruments Incorporated Serial/parallel input/output bus for microprocessor system
US4403303A (en) 1981-05-15 1983-09-06 Beehive International Terminal configuration manager
US4541045A (en) 1981-09-21 1985-09-10 Racal-Milgo, Inc. Microprocessor architecture employing efficient operand and instruction addressing
US4538239A (en) 1982-02-11 1985-08-27 Texas Instruments Incorporated High-speed multiplier for microcomputer used in digital signal processing system
US4607332A (en) 1983-01-14 1986-08-19 At&T Bell Laboratories Dynamic alteration of firmware programs in Read-Only Memory based systems
US4626988A (en) 1983-03-07 1986-12-02 International Business Machines Corporation Instruction fetch look-aside buffer with loop mode control
US4604695A (en) 1983-09-30 1986-08-05 Honeywell Information Systems Inc. Nibble and word addressable memory arrangement
EP0148478B1 (en) 1983-12-23 1989-08-09 Hitachi, Ltd. A data processor with control of the significant bit lenghts of general purpose registers
US4777591A (en) 1984-01-03 1988-10-11 Texas Instruments Incorporated Microprocessor with integrated CPU, RAM, timer, and bus arbiter for data communications systems
US4562537A (en) 1984-04-13 1985-12-31 Texas Instruments Incorporated High speed processor
US4709329A (en) 1984-06-25 1987-11-24 Data General Corporation Input/output device controller for a data processing system
EP0185215B1 (en) 1984-11-21 1993-09-22 Harris Corporation Forth-like language microprocessor
JPS61175845A (en) 1985-01-31 1986-08-07 Toshiba Corp Microprocessor system
US4713749A (en) 1985-02-12 1987-12-15 Texas Instruments Incorporated Microprocessor with repeat instruction
US4714994A (en) 1985-04-30 1987-12-22 International Business Machines Corp. Instruction prefetch buffer control
US5045995A (en) 1985-06-24 1991-09-03 Vicom Systems, Inc. Selective operation of processing elements in a single instruction multiple data stream (SIMD) computer system
GB2177526B (en) 1985-06-24 1990-02-14 Pixar Selective operation of processing elements in a single instruction, multiple data stream (simd)computer system
US4896258A (en) 1985-07-04 1990-01-23 Hitachi, Ltd. Data processor provided with instructions which refer to both tagged and tagless data
JPH0543151B2 (en) 1985-08-21 1993-06-30 Nippon Electric Co
US4773038A (en) 1986-02-24 1988-09-20 Thinking Machines Corporation Method of simulating additional processors in a SIMD parallel processor array
US4870562A (en) 1986-03-20 1989-09-26 Nec Corporation Microcomputer capable of accessing internal memory at a desired variable access time
US4787032A (en) 1986-09-08 1988-11-22 Compaq Computer Corporation Priority arbitration circuit for processor access
US5230079A (en) 1986-09-18 1993-07-20 Digital Equipment Corporation Massively parallel array processing system with processors selectively accessing memory module locations using address in microword or in address register
US4873626A (en) 1986-12-17 1989-10-10 Massachusetts Institute Of Technology Parallel processing system with processor array having memory system included in system memory
GB2201015B (en) 1987-02-10 1990-10-10 Univ Southampton Parallel processor array and array element
US5038282A (en) 1988-05-11 1991-08-06 Massachusetts Institute Of Technology Synchronous processor with simultaneous instruction processing and data transfer
JP2595314B2 (en) 1988-06-30 1997-04-02 三菱電機株式会社 ic mosquitoes with an erroneous write preventing function - de
US5136697A (en) 1989-06-06 1992-08-04 Advanced Micro Devices, Inc. System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache
US5157785A (en) 1990-05-29 1992-10-20 Wavetracer, Inc. Process cell for an n-dimensional processor array having a single input element with 2n data inputs, memory, and full function arithmetic logic unit
CA2045790A1 (en) 1990-06-29 1991-12-30 Richard Lee Sites Branch prediction in high-performance processor
US5361363A (en) 1990-10-03 1994-11-01 Thinking Machines Corporation Input/output system for parallel computer for performing parallel file transfers between selected number of input/output devices and another selected number of processing nodes
JPH06500655A (en) 1990-10-03 1994-01-20
US5361367A (en) 1991-06-10 1994-11-01 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Highly parallel reconfigurable computer architecture for robotic computation having plural processor cells each having right and left ensembles of plural processors
US5132575A (en) * 1991-08-23 1992-07-21 Micron Technology, Inc. Method for providing multi-level potentials at a sense node
WO1993008525A3 (en) 1991-10-24 1993-06-24 Intel Corp Data processing system
US5659778A (en) 1992-02-03 1997-08-19 Tm Patents, L.P. System and method of mapping an array to processing elements
US5551039A (en) 1992-02-03 1996-08-27 Thinking Machines Corporation Compiling a source code vector instruction by generating a subgrid loop for iteratively processing array elements by plural processing elements
US5452401A (en) 1992-03-31 1995-09-19 Seiko Epson Corporation Selective power-down for high performance CPU/system
JP2642039B2 (en) 1992-05-22 1997-08-20 インターナショナル・ビジネス・マシーンズ・コーポレイション Array processor
US5479624A (en) 1992-10-14 1995-12-26 Lee Research, Inc. High-performance interleaved memory system comprising a prime number of memory modules
US5542074A (en) 1992-10-22 1996-07-30 Maspar Computer Corporation Parallel processor system with highly flexible local control capability, including selective inversion of instruction signal and control of bit shift amount
JPH06162228A (en) 1992-11-26 1994-06-10 Sharp Corp Data flow processor device
GB9325170D0 (en) 1992-12-11 1994-02-09 Hughes Aircraft Co Multiple masks for array processors
US5696958A (en) 1993-01-11 1997-12-09 Silicon Graphics, Inc. Method and apparatus for reducing delays following the execution of a branch instruction in an instruction pipeline
CA2116985C (en) 1993-03-11 1999-09-21 Cynthia J. Burns Memory system
US5454117A (en) 1993-08-25 1995-09-26 Nexgen, Inc. Configurable branch prediction for a processor performing speculative execution
EP1338957A3 (en) 1993-11-05 2003-10-29 Intergraph Corporation Software scheduled superscalar computer architecture
JP3415693B2 (en) 1993-12-23 2003-06-09 ノキア モービル フォーンズ リミテッド Interleaving process
US5542059A (en) 1994-01-11 1996-07-30 Exponential Technology, Inc. Dual instruction set processor having a pipeline with a pipestage functional unit that is relocatable in time and sequence order
US5781750A (en) 1994-01-11 1998-07-14 Exponential Technology, Inc. Dual-instruction-set architecture CPU with hidden software emulation mode
EP0671685B1 (en) 1994-03-08 1998-11-04 Digital Equipment Corporation Method and apparatus for detecting and executing cross-domain calls in a computer system
US5590352A (en) 1994-04-26 1996-12-31 Advanced Micro Devices, Inc. Dependency checking and forwarding of variable width operands
US5659722A (en) 1994-04-28 1997-08-19 International Business Machines Corporation Multiple condition code branching system in a multi-processor environment
EP0681236B1 (en) 1994-05-05 2000-11-22 Conexant Systems, Inc. Space vector data path
US5579520A (en) 1994-05-13 1996-11-26 Borland International, Inc. System and methods for optimizing compiled code according to code object participation in program activities
US5812811A (en) * 1995-02-03 1998-09-22 International Business Machines Corporation Executing speculative parallel instructions threads with forking and inter-thread communication
US5933860A (en) 1995-02-10 1999-08-03 Digital Equipment Corporation Multiprobe instruction cache with instruction-based probe hint generation and training whereby the cache bank or way to be accessed next is predicted
JPH08249306A (en) 1995-03-09 1996-09-27 Sharp Corp Data driven type information processor
US5655122A (en) 1995-04-05 1997-08-05 Sequent Computer Systems, Inc. Optimizing compiler with static prediction of branch probability, branch frequency and function frequency
US5774685A (en) 1995-04-21 1998-06-30 International Business Machines Corporation Method and apparatus for biasing cache LRU for prefetched instructions/data based upon evaluation of speculative conditions
US5704053A (en) 1995-05-18 1997-12-30 Hewlett-Packard Company Efficient explicit data prefetching analysis and code generation in a low-level optimizer for inserting prefetch instructions into loops of applications
US5774686A (en) 1995-06-07 1998-06-30 Intel Corporation Method and apparatus for providing two system architectures in a processor
JP3520611B2 (en) * 1995-07-06 2004-04-19 株式会社日立製作所 Method of controlling the processor
US6006328A (en) 1995-07-14 1999-12-21 Christopher N. Drake Computer software authentication, protection, and security system
US5652894A (en) 1995-09-29 1997-07-29 Intel Corporation Method and apparatus for providing power saving modes to a pipelined processor
US6292879B1 (en) 1995-10-25 2001-09-18 Anthony S. Fong Method and apparatus to specify access control list and cache enabling and cache coherency requirement enabling on individual operands of an instruction of a computer
US5930490A (en) 1996-01-02 1999-07-27 Advanced Micro Devices, Inc. Microprocessor configured to switch instruction sets upon detection of a plurality of consecutive instructions
US5822606A (en) 1996-01-11 1998-10-13 Morton; Steven G. DSP having a plurality of like processors controlled in parallel by an instruction word, and a control processor also controlled by the instruction word
US5930509A (en) 1996-01-29 1999-07-27 Digital Equipment Corporation Method and apparatus for performing binary translation
US5664950A (en) 1996-02-13 1997-09-09 Lawrence; Richard J. Hardware mechanism for computer software security
US5835968A (en) 1996-04-17 1998-11-10 Advanced Micro Devices, Inc. Apparatus for providing memory and register operands concurrently to functional units
US5949995A (en) 1996-08-02 1999-09-07 Freeman; Jackie Andrew Programmable branch prediction system and method for inserting prediction operation which is independent of execution of program code
US5854934A (en) * 1996-08-23 1998-12-29 Hewlett-Packard Company Optimizing compiler having data cache prefetch spreading
US6089460A (en) 1996-09-13 2000-07-18 Nippon Steel Corporation Semiconductor device with security protection function, ciphering and deciphering method thereof, and storage medium for storing software therefor
US5991884A (en) * 1996-09-30 1999-11-23 Intel Corporation Method for reducing peak power in dispatching instructions to multiple execution units
US5805907A (en) 1996-10-04 1998-09-08 International Business Machines Corporation System and method for reducing power consumption in an electronic circuit
US5966544A (en) 1996-11-13 1999-10-12 Intel Corporation Data speculatable processor having reply architecture
US5946222A (en) 1996-12-20 1999-08-31 Oak Technology, Inc. Method and apparatus for performing a masked byte addition operation
US6108775A (en) 1996-12-30 2000-08-22 Texas Instruments Incorporated Dynamically loadable pattern history tables in a multi-task microprocessor
JPH10254839A (en) 1997-03-11 1998-09-25 Sony Corp Simd controlling parallel processor and arithmetic method
US6286135B1 (en) 1997-03-26 2001-09-04 Hewlett-Packard Company Cost-sensitive SSA-based strength reduction algorithm for a machine with predication support and segmented addresses
DE69804708T2 (en) 1997-03-29 2002-11-14 Imec Vzw Method and apparatus for size optimization of memory units
JPH10289305A (en) 1997-04-11 1998-10-27 Mitsubishi Electric Corp Image processing device and its method
US5996061A (en) 1997-06-25 1999-11-30 Sun Microsystems, Inc. Method for invalidating data identified by software compiler
WO1999014685A1 (en) 1997-09-16 1999-03-25 Hitachi, Ltd. Data processor and data processing system
US5933650A (en) 1997-10-09 1999-08-03 Mips Technologies, Inc. Alignment and ordering of vector elements for single instruction multiple data processing
US6289505B1 (en) 1997-11-18 2001-09-11 Sun Microsystems, Inc. Method, apparatus and computer programmed product for binary re-optimization using a high level language compiler
US6119205A (en) 1997-12-22 2000-09-12 Sun Microsystems, Inc. Speculative cache line write backs to avoid hotspots
US6412105B1 (en) 1997-12-31 2002-06-25 Elbrus International Limited Computer method and apparatus for compilation of multi-way decisions
US6272676B1 (en) 1998-01-13 2001-08-07 Intel Corporation Method and apparatus for finding loop— lever parallelism in a pointer based application
US6374349B2 (en) 1998-03-19 2002-04-16 Mcfarling Scott Branch predictor with serially connected predictor stages for improving branch prediction accuracy
JPH11272546A (en) 1998-03-23 1999-10-08 Nec Corp Variable length register device
US6121905A (en) 1998-05-11 2000-09-19 Oak Technology, Inc. Method and apparatus for decoding JPEG symbols
US6130631A (en) 1998-05-11 2000-10-10 Oak Technology, Inc. Method and apparatus utilizing a simplified content-addressable memory for JPEG decoding
US6105139A (en) 1998-06-03 2000-08-15 Nec Usa, Inc. Controller-based power management for low-power sequential circuits
EP2280502B1 (en) 1998-06-03 2018-05-02 Cryptography Research, Inc. Using unpredictable information to Resist Discovery of Secrets by External Monitoring
US6334175B1 (en) 1998-07-22 2001-12-25 Ati Technologies, Inc. Switchable memory system and memory allocation method
US6301705B1 (en) 1998-10-01 2001-10-09 Institute For The Development Of Emerging Architectures, L.L.C. System and method for deferring exceptions generated during speculative execution
EP0992916A1 (en) 1998-10-06 2000-04-12 Texas Instruments France Digital signal processor
US6272512B1 (en) 1998-10-12 2001-08-07 Intel Corporation Data manipulation instruction for enhancing value and efficiency of complex arithmetic
GB9825102D0 (en) 1998-11-16 1999-01-13 Insignia Solutions Plc Computer system
JP3297389B2 (en) 1998-12-07 2002-07-02 インターナショナル・ビジネス・マシーンズ・コーポレーション Power control method and electrical equipment
US6430674B1 (en) 1998-12-30 2002-08-06 Intel Corporation Processor executing plural instruction sets (ISA's) with ability to have plural ISA's in different pipeline stages at same time
US6487640B1 (en) 1999-01-19 2002-11-26 International Business Machines Corporation Memory access request reordering to reduce memory access latency
US6282628B1 (en) 1999-02-24 2001-08-28 International Business Machines Corporation Method and system for a result code for a single-instruction multiple-data predicate compare operation
US7430670B1 (en) 1999-07-29 2008-09-30 Intertrust Technologies Corp. Software self-defense systems and methods
JP2001080198A (en) 1999-09-17 2001-03-27 Riso Kagaku Corp Stencil printer
US6446197B1 (en) 1999-10-01 2002-09-03 Hitachi, Ltd. Two modes for executing branch instructions of different lengths and use of branch control instruction and register set loaded with target instructions
WO2001046777A3 (en) 1999-10-26 2008-09-25 Pyxsys Corp Mimd arrangement of simd machines
US6502188B1 (en) 1999-11-16 2002-12-31 Advanced Micro Devices, Inc. Dynamic classification of conditional branches in global history branch prediction
EP1107123B1 (en) 1999-12-06 2007-11-21 Texas Instruments France Smart cache
US6625740B1 (en) 2000-01-13 2003-09-23 Cirrus Logic, Inc. Dynamically activating and deactivating selected circuit blocks of a data processing integrated circuit during execution of instructions according to power code bits appended to selected instructions
US7124286B2 (en) 2000-01-14 2006-10-17 Advanced Micro Devices, Inc. Establishing an operating mode in a processor
US6452864B1 (en) 2000-01-31 2002-09-17 Stmicroelectonics S.R.L. Interleaved memory device for sequential access synchronous reading with simplified address counters
US6282623B1 (en) 2000-02-04 2001-08-28 Motorola Inc. Method for digital signal processing, DSP, mobile communication and audi o-device
EP1130517B1 (en) 2000-03-02 2004-05-26 STMicroelectronics S.r.l. Redundancy architecture for an interleaved memory
WO2001065366A1 (en) 2000-03-02 2001-09-07 Alarity Corporation System and method for process protection
US6446181B1 (en) 2000-03-31 2002-09-03 Intel Corporation System having a configurable cache/SRAM memory
JP2002007359A (en) 2000-06-21 2002-01-11 Sony Corp Method and device for parallel processing simd control
WO2002039272A9 (en) 2000-11-10 2003-09-04 Chipwrights Design Inc Method and apparatus for reducing branch latency
US6931518B1 (en) 2000-11-28 2005-08-16 Chipwrights Design, Inc. Branching around conditional processing if states of all single instruction multiple datapaths are disabled and the computer program is non-deterministic
CN1486465A (en) 2000-11-28 2004-03-31 奇普赖茨设计公司 Handling conditional processing in a single instruction multiple datapath processor architecture
US20020073301A1 (en) 2000-12-07 2002-06-13 International Business Machines Corporation Hardware for use with compiler generated branch information
CA2327911A1 (en) 2000-12-08 2002-06-08 Cloakware Corporation Obscuring functions in computer software
US6813693B2 (en) 2000-12-11 2004-11-02 Microsoft Corporation System and method for the discovery and use of repetitively accessed data
JP3681647B2 (en) 2001-02-21 2005-08-10 株式会社半導体理工学研究センター Cache memory system unit
US6643739B2 (en) 2001-03-13 2003-11-04 Koninklijke Philips Electronics N.V. Cache way prediction based on instruction base register
US20040205740A1 (en) 2001-03-29 2004-10-14 Lavery Daniel M. Method for collection of memory reference information and memory disambiguation
US6795781B2 (en) 2002-06-27 2004-09-21 Intel Corporation Method and apparatus for compiler assisted power management
US7467377B2 (en) 2002-10-22 2008-12-16 Intel Corporation Methods and apparatus for compiler managed first cache bypassing
US7500126B2 (en) 2002-12-04 2009-03-03 Nxp B.V. Arrangement and method for controlling power modes of hardware resources
US20040154010A1 (en) * 2003-01-31 2004-08-05 Pedro Marcuello Control-quasi-independent-points guided speculative multithreading
US7076769B2 (en) * 2003-03-28 2006-07-11 Intel Corporation Apparatus and method for reproduction of a source ISA application state corresponding to a target ISA application state at an execution stop point
US7299500B1 (en) 2003-07-17 2007-11-20 Copyright Clearance Center, Inc. Method and apparatus for secure delivery and rights management of digital content at an unsecure site
US7089594B2 (en) 2003-07-21 2006-08-08 July Systems, Inc. Application rights management in a mobile environment
JP2005078178A (en) 2003-08-28 2005-03-24 Toshiba Corp Computer system and software management method
US20050114850A1 (en) 2003-10-29 2005-05-26 Saurabh Chheda Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control
US7293164B2 (en) 2004-01-14 2007-11-06 International Business Machines Corporation Autonomic method and apparatus for counting branch instructions to generate branch statistics meant to improve branch predictions
US8607209B2 (en) 2004-02-04 2013-12-10 Bluerisc Inc. Energy-focused compiler-assisted branch prediction
KR101254209B1 (en) 2004-03-22 2013-04-23 삼성전자주식회사 Apparatus and method for moving and copying right objects between device and portable storage device
US7664109B2 (en) 2004-09-03 2010-02-16 Microsoft Corporation System and method for distributed streaming of scalable media
US7676661B1 (en) 2004-10-05 2010-03-09 Xilinx, Inc. Method and system for function acceleration using custom instructions
EP1842203A4 (en) 2004-11-12 2011-03-23 Verayo Inc Volatile device keys and applications thereof
US7600265B2 (en) 2005-03-09 2009-10-06 Nokia Corporation System and method for applying an OMA DRM permission model to JAVA MIDP applications
US7613921B2 (en) 2005-05-13 2009-11-03 Intel Corporation Method and apparatus for remotely provisioning software-based security coprocessors
US20070294181A1 (en) 2006-05-22 2007-12-20 Saurabh Chheda Flexible digital rights management with secure snippets

Patent Citations (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4003033A (en) * 1975-12-22 1977-01-11 Honeywell Information Systems, Inc. Architecture for a microprogrammed device controller
US4067059A (en) * 1976-01-29 1978-01-03 Sperry Rand Corporation Shared direct memory access controller
US4079455A (en) * 1976-12-13 1978-03-14 Rca Corporation Microprocessor architecture
US4138720A (en) * 1977-04-04 1979-02-06 Burroughs Corporation Time-shared, multi-phase memory accessing system
US4181942A (en) * 1978-03-31 1980-01-01 International Business Machines Corporation Program branching method and apparatus
US4382279A (en) * 1978-04-25 1983-05-03 Compagnie Internationale Pour L'informatique Cii-Honeywell Bull (Societe Anonyme) Single chip microprocessor with on-chip modifiable memory
US4255785A (en) * 1978-09-25 1981-03-10 Motorola, Inc. Microprocessor having instruction fetch and execution overlap
US4376977A (en) * 1979-08-27 1983-03-15 U.S. Philips Corporation Computer system with scannable program memory
US4435758A (en) * 1980-03-10 1984-03-06 International Business Machines Corporation Method for conditional branch execution in SIMD vector processors
US4434461A (en) * 1980-09-15 1984-02-28 Motorola, Inc. Microprocessor with duplicate registers for processing interrupts
US4450519A (en) * 1980-11-24 1984-05-22 Texas Instruments Incorporated Psuedo-microprogramming in microprocessor in single-chip microprocessor with alternate IR loading from internal or external program memories
US4592013A (en) * 1981-08-21 1986-05-27 International Business Machines Corp. Method and device for addressing a memory
US4577282A (en) * 1982-02-22 1986-03-18 Texas Instruments Incorporated Microcomputer system for digital signal processing
US4649471A (en) * 1983-03-01 1987-03-10 Thomson Components-Mostek Corporation Address-controlled automatic bus arbitration and address modification
US4720812A (en) * 1984-05-30 1988-01-19 Racal-Milgo, Inc. High speed program store with bootstrap
US4665495A (en) * 1984-07-23 1987-05-12 Texas Instruments Incorporated Single chip dram controller and CRT controller
US4803621A (en) * 1986-07-24 1989-02-07 Sun Microsystems, Inc. Memory access system
US5276895A (en) * 1986-09-18 1994-01-04 Digital Equipment Corporation Massively parallel array processing system
US4992933A (en) * 1986-10-27 1991-02-12 International Business Machines Corporation SIMD array processor with global instruction control and reprogrammable instruction decoders
US5021993A (en) * 1987-03-31 1991-06-04 Kabushiki Kaisha Toshiba Device for saving and restoring register information
US5111389A (en) * 1987-10-29 1992-05-05 International Business Machines Corporation Aperiodic mapping system using power-of-two stride access to interleaved devices
US5121498A (en) * 1988-05-11 1992-06-09 Massachusetts Institute Of Technology Translator for translating source code for selective unrolling of loops in the source code
US5127091A (en) * 1989-01-13 1992-06-30 International Business Machines Corporation System for reducing delay in instruction execution by executing branch instructions in separate processor while dispatching subsequent instructions to primary processor
US4931986A (en) * 1989-03-03 1990-06-05 Ncr Corporation Computer system clock generator for generating tuned multiple clock signals
US5224214A (en) * 1990-04-12 1993-06-29 Digital Equipment Corp. BuIffet for gathering write requests and resolving read conflicts by matching read and write requests
US5193202A (en) * 1990-05-29 1993-03-09 Wavetracer, Inc. Processor array with relocated operand physical address generator capable of data transfer to distant physical processor for each virtual processor while simulating dimensionally larger array processor
US5637932A (en) * 1990-11-27 1997-06-10 Hitachi, Ltd. Power consumption control system
US5497478A (en) * 1991-03-20 1996-03-05 Hewlett-Packard Company Memory access system and method modifying a memory interleaving scheme so that data can be read in any sequence without inserting wait cycles
US5875464A (en) * 1991-12-10 1999-02-23 International Business Machines Corporation Computer system with private and shared partitions in cache
US5630143A (en) * 1992-03-27 1997-05-13 Cyrix Corporation Microprocessor with externally controllable power management
US5872987A (en) * 1992-08-07 1999-02-16 Thinking Machines Corporation Massively parallel computer including auxiliary vector processor
US5410669A (en) * 1993-04-05 1995-04-25 Motorola, Inc. Data processor having a cache memory capable of being used as a linear ram bank
US5604913A (en) * 1993-08-10 1997-02-18 Fujitsu Limited Vector processor having a mask register used for performing nested conditional instructions
US5884057A (en) * 1994-01-11 1999-03-16 Exponential Technology, Inc. Temporal re-alignment of a floating point pipeline to an integer pipeline for emulation of a load-operate architecture on a load/store processor
US5481684A (en) * 1994-01-11 1996-01-02 Exponential Technology, Inc. Emulating operating system calls in an alternate instruction set using a modified code segment descriptor
US5524223A (en) * 1994-01-31 1996-06-04 Motorola, Inc. Instruction accelerator for processing loop instructions with address generator using multiple stored increment values
US5481693A (en) * 1994-07-20 1996-01-02 Exponential Technology, Inc. Shared register architecture for a dual-instruction-set CPU
US5752068A (en) * 1994-08-23 1998-05-12 Massachusetts Institute Of Technology Mesh parallel computer architecture apparatus and associated methods
US5598546A (en) * 1994-08-31 1997-01-28 Exponential Technology, Inc. Dual-architecture super-scalar pipeline
US5608886A (en) * 1994-08-31 1997-03-04 Exponential Technology, Inc. Block-based branch prediction using a target finder array storing target sub-addresses
US5758176A (en) * 1994-09-28 1998-05-26 International Business Machines Corporation Method and system for providing a single-instruction, multiple-data execution unit for performing single-instruction, multiple-data operations within a superscalar data processing system
US5758112A (en) * 1994-10-14 1998-05-26 Silicon Graphics, Inc. Pipeline processor with enhanced method and apparatus for restoring register-renaming information in the event of a branch misprediction
US5638525A (en) * 1995-02-10 1997-06-10 Intel Corporation Processor capable of executing programs that contain RISC and CISC instructions
US6058469A (en) * 1995-04-17 2000-05-02 Ricoh Corporation System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization
US5737572A (en) * 1995-06-06 1998-04-07 Apple Computer, Inc. Bank selection logic for memory controllers
US5875324A (en) * 1995-06-07 1999-02-23 Advanced Micro Devices, Inc. Superscalar microprocessor which delays update of branch prediction information in response to branch misprediction until a subsequent idle clock
US5638533A (en) * 1995-10-12 1997-06-10 Lsi Logic Corporation Method and apparatus for providing data to a parallel processing array
US5864707A (en) * 1995-12-11 1999-01-26 Advanced Micro Devices, Inc. Superscalar microprocessor configured to predict return addresses from a return stack storage
US6067622A (en) * 1996-01-02 2000-05-23 Moore; Steven Jerome Software security system using remove function to restrict unauthorized duplicating and installation of an application program
US5727229A (en) * 1996-02-05 1998-03-10 Motorola, Inc. Method and apparatus for moving data in a parallel processor
US5721893A (en) * 1996-05-14 1998-02-24 Hewlett-Packard Company Exploiting untagged branch prediction cache by relocating branches
US5737749A (en) * 1996-05-20 1998-04-07 International Business Machines Corporation Method and system for dynamically sharing cache capacity in a microprocessor
US5864697A (en) * 1996-06-28 1999-01-26 Texas Instruments Incorporated Microprocessor using combined actual and speculative branch history prediction
US5742804A (en) * 1996-07-24 1998-04-21 Institute For The Development Of Emerging Architectures, L.L.C. Instruction prefetch mechanism utilizing a branch predict instruction
US5903750A (en) * 1996-11-20 1999-05-11 Institute For The Development Of Emerging Architectures, L.L.P. Dynamic branch prediction for branch instructions with multiple targets
US5857104A (en) * 1996-11-26 1999-01-05 Hewlett-Packard Company Synthetic dynamic branch prediction
US5887166A (en) * 1996-12-16 1999-03-23 International Business Machines Corporation Method and system for constructing a program including a navigation instruction
US6212542B1 (en) * 1996-12-16 2001-04-03 International Business Machines Corporation Method and system for executing a program within a multiscalar processor by processing linked thread descriptors
US5870581A (en) * 1996-12-20 1999-02-09 Oak Technology, Inc. Method and apparatus for performing concurrent write operations to a single-write-input register file and an accumulator register
US6381668B1 (en) * 1997-03-21 2002-04-30 International Business Machines Corporation Address mapping for system memory
US6393520B2 (en) * 1997-04-17 2002-05-21 Matsushita Electric Industrial Co., Ltd. Data processor and data processing system with internal memories
US6385720B1 (en) * 1997-07-14 2002-05-07 Matsushita Electric Industrial Co., Ltd. Branch prediction method and processor using origin information, relative position information and history information
US6049330A (en) * 1997-08-28 2000-04-11 Oak Technology, Inc. Method and apparatus for optimizing storage of compressed images in memory
US6211864B1 (en) * 1997-08-28 2001-04-03 Oak Technology, Inc. Method and apparatus for optimizing storage of compressed images in memory
US6044469A (en) * 1997-08-29 2000-03-28 Preview Software Software publisher or distributor configurable software security mechanism
US6021484A (en) * 1997-11-14 2000-02-01 Samsung Electronics Co., Ltd. Dual instruction set architecture
US6178498B1 (en) * 1997-12-18 2001-01-23 Idea Corporation Storing predicted branch target address in different storage according to importance hint in branch prediction instruction
US6219796B1 (en) * 1997-12-23 2001-04-17 Texas Instruments Incorporated Power reduction for processors by software control of functional units
US6216223B1 (en) * 1998-01-12 2001-04-10 Billions Of Operations Per Second, Inc. Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor
US6067609A (en) * 1998-04-09 2000-05-23 Teranex, Inc. Pattern generation and shift plane operations for a mesh connected computer
US6529943B1 (en) * 1998-04-24 2003-03-04 Canon Kabushiki Kaisha Server, client, client server system, method for controlling them and storage medium therefor
US6052703A (en) * 1998-05-12 2000-04-18 Oak Technology, Inc. Method and apparatus for determining discrete cosine transforms using matrix multiplication and modified booth encoding
US6175892B1 (en) * 1998-06-19 2001-01-16 Hitachi America. Ltd. Registers and methods for accessing registers for use in a single instruction multiple data system
US6988183B1 (en) * 1998-06-26 2006-01-17 Derek Chi-Lan Wong Methods for increasing instruction-level parallelism in microprocessors and digital system
US20050066153A1 (en) * 1998-10-12 2005-03-24 Harshvardhan Sharangpani Method for processing branch operations
US20030041230A1 (en) * 1998-12-30 2003-02-27 Lihu Rappoport Method and system for branch target prediction using path information
US6341371B1 (en) * 1999-02-23 2002-01-22 International Business Machines Corporation System and method for optimizing program execution in a computer system
US6571331B2 (en) * 1999-03-18 2003-05-27 Ip-First, Llc Static branch prediction mechanism for conditional branch instructions
US7024393B1 (en) * 1999-03-27 2006-04-04 Microsoft Corporation Structural of digital rights management (DRM) system
US6550004B1 (en) * 1999-11-05 2003-04-15 Ip-First, Llc Hybrid branch predictor with improved selector table update mechanism
US6539543B1 (en) * 1999-11-29 2003-03-25 Adelante Technologies, Nv Method and apparatus for compiling source code by flattening hierarchies
US6560776B1 (en) * 2000-02-18 2003-05-06 Avaya Technology Corp. Software installation verification tool
US6675305B1 (en) * 2000-08-04 2004-01-06 Synopsys, Inc. Power saving in a USB peripheral by providing gated clock signal to CSR block in response to a local interrupt generated when an operation is to be performed
US6732253B1 (en) * 2000-11-13 2004-05-04 Chipwrights Design, Inc. Loop handling for single instruction multiple datapath processor architectures
US6687838B2 (en) * 2000-12-07 2004-02-03 Intel Corporation Low-power processor hint, such as from a PAUSE instruction
US20040015923A1 (en) * 2001-02-16 2004-01-22 Craig Hemsing Apparatus and method to reduce memory footprints in processor architectures
US20030014742A1 (en) * 2001-07-09 2003-01-16 Sasken Communication Technologies Limited Technique for compiling computer code to reduce energy consumption while executing the code
US7076638B2 (en) * 2001-09-20 2006-07-11 Matsushita Electric Industrial Co., Ltd. Processor, compiler and compilation method
US20030066061A1 (en) * 2001-09-29 2003-04-03 Youfeng Wu Method and apparatus for performing compiler transformation of software code using fastforward regions and value specialization
US7036118B1 (en) * 2001-12-20 2006-04-25 Mindspeed Technologies, Inc. System for executing computer programs on a limited-memory computing machine
US20040010679A1 (en) * 2002-07-09 2004-01-15 Moritz Csaba Andras Reducing processor energy consumption by controlling processor resources
US20040010783A1 (en) * 2002-07-09 2004-01-15 Moritz Csaba Andras Reducing processor energy consumption using compile-time information
US7493607B2 (en) * 2002-07-09 2009-02-17 Bluerisc Inc. Statically speculative compilation and execution
US20040010782A1 (en) * 2002-07-09 2004-01-15 Moritz Csaba Andras Statically speculative compilation and execution
US7162617B2 (en) * 2003-02-14 2007-01-09 Fine Arc Incorporated Data processor with changeable architecture
US7185215B2 (en) * 2003-02-24 2007-02-27 International Business Machines Corporation Machine code builder derived power consumption reduction
US20050108507A1 (en) * 2003-11-17 2005-05-19 Saurabh Chheda Security of program executables and microprocessors based on compiler-arcitecture interaction
US7487340B2 (en) * 2006-06-08 2009-02-03 International Business Machines Corporation Local and global branch prediction information storage
US20080126766A1 (en) * 2006-11-03 2008-05-29 Saurabh Chheda Securing microprocessors against information leakage and physical tampering

Cited By (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040010782A1 (en) * 2002-07-09 2004-01-15 Moritz Csaba Andras Statically speculative compilation and execution
US9235393B2 (en) 2002-07-09 2016-01-12 Iii Holdings 2, Llc Statically speculative compilation and execution
US7493607B2 (en) 2002-07-09 2009-02-17 Bluerisc Inc. Statically speculative compilation and execution
US20090300590A1 (en) * 2002-07-09 2009-12-03 Bluerisc Inc., A Massachusetts Corporation Statically speculative compilation and execution
US9569186B2 (en) 2003-10-29 2017-02-14 Iii Holdings 2, Llc Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control
US9582650B2 (en) 2003-11-17 2017-02-28 Bluerisc, Inc. Security of program executables and microprocessors based on compiler-architecture interaction
US7996671B2 (en) 2003-11-17 2011-08-09 Bluerisc Inc. Security of program executables and microprocessors based on compiler-architecture interaction
US20050108507A1 (en) * 2003-11-17 2005-05-19 Saurabh Chheda Security of program executables and microprocessors based on compiler-arcitecture interaction
US7770034B2 (en) 2003-12-16 2010-08-03 Intel Corporation Performance monitoring based dynamic voltage and frequency scaling
US20050132238A1 (en) * 2003-12-16 2005-06-16 Murthi Nanja Performance monitoring based dynamic voltage and frequency scaling
US9697000B2 (en) 2004-02-04 2017-07-04 Iii Holdings 2, Llc Energy-focused compiler-assisted branch prediction
US8607209B2 (en) 2004-02-04 2013-12-10 Bluerisc Inc. Energy-focused compiler-assisted branch prediction
US20050172277A1 (en) * 2004-02-04 2005-08-04 Saurabh Chheda Energy-focused compiler-assisted branch prediction
US9244689B2 (en) 2004-02-04 2016-01-26 Iii Holdings 2, Llc Energy-focused compiler-assisted branch prediction
US20050229149A1 (en) * 2004-03-17 2005-10-13 Munter Joel D Power and/or energy optimized compile/execution
US7904893B2 (en) * 2004-03-17 2011-03-08 Marvell International Ltd. Power and/or energy optimized compile/execution
US8621179B2 (en) * 2004-06-18 2013-12-31 Intel Corporation Method and system for partial evaluation of virtual address translations in a simulator
US20050283351A1 (en) * 2004-06-18 2005-12-22 Virtutech Ab Method and system for partial evaluation of virtual address translations in a simulator
US20060170675A1 (en) * 2005-02-01 2006-08-03 Samsung Electronics Co., Ltd. Method and apparatus for rendering 3D graphics data
US8614704B2 (en) * 2005-02-01 2013-12-24 Samsung Electronics Co., Ltd. Method and apparatus for rendering 3D graphics data
US7802241B2 (en) * 2005-12-12 2010-09-21 Freescale Semiconductor, Inc. Method for estimating processor energy usage
US20070136720A1 (en) * 2005-12-12 2007-06-14 Freescale Semiconductor, Inc. Method for estimating processor energy usage
US7539884B2 (en) 2005-12-29 2009-05-26 Industrial Technology Research Institute Power-gating instruction scheduling for power leakage reduction
US20070157044A1 (en) * 2005-12-29 2007-07-05 Industrial Technology Research Institute Power-gating instruction scheduling for power leakage reduction
US20070294181A1 (en) * 2006-05-22 2007-12-20 Saurabh Chheda Flexible digital rights management with secure snippets
US8001540B2 (en) * 2006-08-08 2011-08-16 International Business Machines Corporation System, method and program product for control of sequencing of data processing by different programs
US20080177993A1 (en) * 2006-08-08 2008-07-24 International Business Machines Corporation System, method and program product for control of sequencing of data processing by different programs
US20080126766A1 (en) * 2006-11-03 2008-05-29 Saurabh Chheda Securing microprocessors against information leakage and physical tampering
US9069938B2 (en) 2006-11-03 2015-06-30 Bluerisc, Inc. Securing microprocessors against information leakage and physical tampering
US9940445B2 (en) 2006-11-03 2018-04-10 Bluerisc, Inc. Securing microprocessors against information leakage and physical tampering
US7853812B2 (en) 2007-02-07 2010-12-14 International Business Machines Corporation Reducing power usage in a software application
US8739142B2 (en) * 2007-05-16 2014-05-27 International Business Machines Corporation Method and apparatus for run-time statistics dependent program execution using source-coding principles
US20130117544A1 (en) * 2007-05-16 2013-05-09 International Business Machines Corporation Method and apparatus for run-time statistics dependent program execution using source-coding principles
US20100299662A1 (en) * 2009-05-20 2010-11-25 Microsoft Corporation Resource aware programming
US9329876B2 (en) 2009-05-20 2016-05-03 Microsoft Technology Licensing, Llc Resource aware programming
US20110078655A1 (en) * 2009-09-30 2011-03-31 International Business Machines Corporation Creating functional equivalent code segments of a computer software program with lower energy footprints
US20120017201A1 (en) * 2010-07-14 2012-01-19 Rajan Sreeranga P System and Method for Comparing Software Frameworks
US9477928B2 (en) * 2010-07-14 2016-10-25 Fujitsu Limited System and method for comparing software frameworks
US20130111032A1 (en) * 2011-10-28 2013-05-02 International Business Machines Corporation Cloud optimization using workload analysis
US8914515B2 (en) * 2011-10-28 2014-12-16 International Business Machines Corporation Cloud optimization using workload analysis
US9183144B2 (en) * 2012-12-14 2015-11-10 Intel Corporation Power gating a portion of a cache memory
US9176875B2 (en) * 2012-12-14 2015-11-03 Intel Corporation Power gating a portion of a cache memory
US20140173207A1 (en) * 2012-12-14 2014-06-19 Ren Wang Power Gating A Portion Of A Cache Memory
US20140173206A1 (en) * 2012-12-14 2014-06-19 Ren Wang Power Gating A Portion Of A Cache Memory
US9542179B2 (en) * 2013-09-06 2017-01-10 Texas Instruments Incorporated System and method for energy aware program development
US20150074636A1 (en) * 2013-09-06 2015-03-12 Texas Instruments Deutschland Gmbh System and method for energy aware program development
US9411964B1 (en) * 2014-11-24 2016-08-09 Bluerisc, Inc. Characterizing, detecting and healing vulnerabilities in computer code
US9754112B1 (en) 2014-11-24 2017-09-05 Bluerisc, Inc. Detection and healing of vulnerabilities in computer code

Also Published As

Publication number Publication date Type
US20140372994A1 (en) 2014-12-18 application
US9569186B2 (en) 2017-02-14 grant
US20170131986A1 (en) 2017-05-11 application

Similar Documents

Publication Publication Date Title
Sharangpani et al. Itanium processor microarchitecture
US6988183B1 (en) Methods for increasing instruction-level parallelism in microprocessors and digital system
US6035374A (en) Method of executing coded instructions in a multiprocessor having shared execution resources including active, nap, and sleep states in accordance with cache miss latency
US5799180A (en) Microprocessor circuits, systems, and methods passing intermediate instructions between a short forward conditional branch instruction and target instruction through pipeline, then suppressing results if branch taken
US6349365B1 (en) User-prioritized cache replacement
US7975134B2 (en) Macroscalar processor architecture
US20130080805A1 (en) Dynamic partitioning for heterogeneous cores
US7617496B2 (en) Macroscalar processor architecture
US6151662A (en) Data transaction typing for improved caching and prefetching characteristics
Reinman et al. Predictive techniques for aggressive load speculation
Rychlik et al. Efficacy and performance impact of value prediction
US5996060A (en) System and method for concurrent processing
US20030126408A1 (en) Dependence-chain processor
US20040044880A1 (en) Method and apparatus for transferring control in a computer system with dynamic compilation capability
Krishnaswamy et al. Profile guided selection of ARM and thumb instructions
Wang et al. Guided region prefetching: a cooperative hardware/software approach
US6308261B1 (en) Computer system having an instruction for probing memory latency
US5941983A (en) Out-of-order execution using encoded dependencies between instructions in queues to determine stall values that control issurance of instructions from the queues
US5889985A (en) Array prefetch apparatus and method
Gabbay et al. Speculative execution based on value prediction
US7487340B2 (en) Local and global branch prediction information storage
US20030023959A1 (en) General and efficient method for transforming predicated execution to static speculation
US20040205326A1 (en) Early predicate evaluation to reduce power in very long instruction word processors employing predicate execution
US20040117606A1 (en) Method and apparatus for dynamically conditioning statically produced load speculation and prefetches using runtime information
Corliss et al. DISE: A programmable macro engine for customizing applications

Legal Events

Date Code Title Description
AS Assignment

Owner name: BLUERISC INC, MASSACHUSETTS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHHEDA, SAURABH;ASHOK, RAKSIT;CARVER, KRISTOPHER;REEL/FRAME:016730/0718

Effective date: 20041201

AS Assignment

Owner name: BLUERISC, INC., MASSACHUSETTS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHHEDA, SAURABH;CARVER, KRISTOPHER;ASHOK, RAKSIT;REEL/FRAME:033980/0621

Effective date: 20041201

AS Assignment

Owner name: III HOLDINGS 2, LLC, DELAWARE

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BLUERISC, INC.;REEL/FRAME:034980/0170

Effective date: 20141115