US20080126766A1 - Securing microprocessors against information leakage and physical tampering - Google Patents

Securing microprocessors against information leakage and physical tampering Download PDF

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US20080126766A1
US20080126766A1 US11981178 US98117807A US2008126766A1 US 20080126766 A1 US20080126766 A1 US 20080126766A1 US 11981178 US11981178 US 11981178 US 98117807 A US98117807 A US 98117807A US 2008126766 A1 US2008126766 A1 US 2008126766A1
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instruction
encoding
mutation
processor
instructions
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Saurabh Chheda
Kristopher Carver
Csaba Andras Moritz
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BlueRISC Inc
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BlueRISC Inc
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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
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    • G06F21/12Protecting executable software
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    • G06F21/70Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/75Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
    • G06F21/755Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation with measures against power attack
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
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    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • GPHYSICS
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    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145Instruction analysis, e.g. decoding, instruction word fields
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
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    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017Runtime instruction translation, e.g. macros
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    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
    • G06F9/3842Speculative instruction execution
    • G06F9/3846Speculative instruction execution using static prediction, e.g. branch taken strategy
    • GPHYSICS
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    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3877Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
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    • G06F2221/033Test or assess software
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Abstract

A processor system comprising: performing a compilation process on a computer program; encoding an instruction with a selected encoding; encoding the security mutation information in an instruction set architecture of a processor; and executing a compiled computer program in the processor using an added mutation instruction, wherein executing comprises executing a mutation instruction to enable decoding another instruction. A processor system with a random instruction encoding and randomized execution, providing effective defense against offline and runtime security attacks including software and hardware reverse engineering, invasive microprobing, fault injection, and high-order differential and electromagnetic power analysis.

Description

    RELATED U.S. APPLICATION DATA
  • This application claims the benefits of U.S. Provisional Application No. 60/856,593, filed on Nov. 3, 2006, and Confirmation No 1421, entitled: SAFE ZONES: SECURING A PROCESSOR AGAINST INFORMATION LEAKAGE AND PHYSICAL TAMPERING, the contents of which are hereby incorporated by reference into this application as if set forth herein in full.
  • TECHNICAL FIELD
  • This invention relates generally to providing effective defense against information leakage and tampering in a microprocessor or a system where such a secured microprocessor would be incorporated. More particularly, it relates to a processor framework and methods supporting an execution based on chained sequences of small obfuscated codes called safe zones and associated randomized execution. It relates to mechanisms to make encoding of instructions in each safe zone random and unique for each chip, or compilation, and to ensure that breaking into a safe zone's encoding does not compromise another safe zone's security or does not allow leaking information from the processor outside that safe zone. The invention provides effective mechanisms across compiler, instruction set architecture, and micro-architecture layers to defend against offline and runtime security attacks including software and hardware reverse engineering, invasive microprobing, fault injection, and high-order differential and electromagnetic power analysis. The invention provides the security benefits without significantly impacting performance, power consumption, or energy efficiency during execution.
  • Furthermore, systems that incorporate a microprocessor with above technology can rely on the trust and security provided inside the processor to defend against different kinds of information leakage and tampering attacks including both invasive and non-invasive methods. Additionally, systems that in addition incorporate microprocessors with lesser security that would run applications, could be still effectively defended with the addition of a security microprocessor designed with the proposed invention.
  • BACKGROUND
  • Processing devices are vulnerable to security attacks including software attacks, invasive attacks by removing layers of packaging and different types of non-invasive attacks like fault injection and power analysis, etc. Attacks are also often categorized as in-wire when an attack does not require physical presence of an attacker. An example of such an attack is through the internet or other connection to another system. Non in-wire attackers would need typically to have access to the system.
  • This section mainly focuses on attacks that require considerable resources or Class III such as funded organizations with unlimited resources. Other lesser sophisticated attacks are similarly defended. A list of some of the available defense mechanisms is also described after the attack scenarios.
  • Attack categories: There are several sophisticated attack strategies reported. First, there are non-invasive side-channel attacks based on differential power analysis, electromagnetic analysis, and fault injection. Attacks based on power and electromagnetic analysis utilize the fact that encryption devices leak key data electromagnetically, whether by variation in power consumption or electromagnetic radiation. Differential power analysis (DPA) is very effective against cryptographic designs and password verification techniques. Electromagnetic analysis allows more focused observation of specific parts of a chip. Fault injection attacks typically require precise knowledge of the time instances when faults are injected and aim, e.g., at modifying memory bits to allow extraction of side-channel information. There are several reported successful side-channel attacks, e.g., recovery of password in Freescale MC908AZ60A, AES ASIC implementations, and smart cards.
  • Another attack category is based on invasive methods. Chips can be decapsulated front-side and/or rear-side manually using nitric acid and Acetone, or automatically using concentrated HNO3 and H2SO4. The more advanced approaches for reverse engineering have the capability to gather information about deep-submicron designs using Optical Imaging (OI), or Scanning Electron Microscopy (SEM). SEM yields higher-precision reverse engineering, often with sufficient detail for building gate-level models enabling VHDL simulation. SEM-based Voltage Contrast Microscopy is used to read memory cells.
  • Some attacks are based on recovering data from erased locations (e.g., caused by tamper-detection related zeroization logic) in SRAM and non-volatile memory due to data remanence—see successful attack on PIC16F84A. Other attacks are semi-invasive, e.g., UV or X-rays based, and can be completed without requiring removal of passivation layers.
  • Microprobing attacks would rely on removing the polymer layer from a chip surface, local removing of passivation layers, cutting through metal layers and using Focus Ion Beam (FIB) probes. FIB allows 10-nm precision to create probing points and/or restore security fuses. There are several companies specializing in chip reverse engineering, e.g., Chipworks and Semiconductor Insights at the time of submission of this patent.
  • Because microprocessors are vulnerable they cannot provide defense against sophisticated attackers. When added to systems such as an embedded device, mobile phone, or personal computer, the whole system's security is affected by the lack of a trusted component. In such systems an attacker has several ways to attack including by modifying and tampering with the software, attacking in memory, attacking the operating system, or physically attacking the processor itself. Existing solutions are not adequate whenever high security is necessary. This includes application such as premium content security, access to enterprise resources, devices used in power plats, defense systems, government systems etc.
  • Defenses: State-of-the-art approaches offer limited defense against Class III attacks. Partial defense is provided by techniques including tamper detection with top metal layer sensors, operating voltage as well as temperature sensors, highly doped silicon substrate to defend against a rear-side attack, sophisticated security fuses including those in memory arrays, zeroization logic of security-sensitive state in case of tamper-detection, encryption of memory content with cryptographic accelerators, encryption of buses (typically with simple techniques to not affect latency), VTROM used instead of Mask ROM and Flash memory for non-volatile memory (not visible with static reverse engineering), and various defenses against memory remanence. There has been significant work on securing cryptographic implementations and software protection. These techniques are often software based an vulnerable to even simple attacks based on reverse engineering and running through debuggers. When they are microprocessor-assisted, they are vulnerable as microprocessors today to dot protect against sophisticated attackers.
  • Examples of micro-architectural techniques include memory architectures with protection like ARM Trust-Zone, randomized clock or various asynchronous designs, circuits based on process variation, etc.
  • The ever increasing sophistication of attacks implies that there is a considerable need to enhanced security during processing. Clearly, with a global trade of products and services it will be difficult to address security without establishing trust at the processing layer. No more can one rely on that just because a processing unit is completing a function in hardware it will be able to withstand attacks targeting extracting secret information, getting access to intellectual property, and gaining unauthorized access to system resources.
  • SUMMARY
  • The present invention addresses the foregoing need by providing methods and a processing framework creating an effective defense against the aforementioned security attacks at the digital level. As opposed to many defenses, the approach provides comprehensive security with very low cost and minimal power and performance overhead.
  • At the heart of the invention is a novel processor technology for obfuscated and randomized execution that is based on a security-focused compilation and code generation, associated instruction set architecture paradigm, and security-focused microarchitecture approach for allowing randomized and protected execution internally in the processor.
  • An aspect is the compiler-driven approach for instruction obfuscation and randomization, where the instruction encodings are randomized and tied together. The microarchitecture component of the invention supports this scrambled instruction execution wherein instructions that execute have their meaning decoded at runtime but remain in obfuscated format even internally in a processor. Another aspect is that this processor has its switching activity de-correlated from the operations it executes as the execution is itself random due to the mechanisms and random encoding.
  • Execution in conventional processors is based on a fixed encoding of all instructions. This allows for easy reverse engineering and makes them also vulnerable to a variety of side-channel attacks at runtime. By contrast, the invention proposed here is based on the fact that, with suitable support, the encoding of instructions can be changed at fine granularity and even randomized in chip-unique ways and execution kept obfuscated deep into the processor pipeline.
  • This has significant security benefits such as protecting against side-channel attacks like power and electromagnetic analysis, fault injection that would require precise knowledge of the time instances when faults are injected and data remanence attacks in RAM and non-volatile memory. Reverse engineering of the processor in this invention is not sufficient to reveal critical information due to the layered compiler-hardware approach and chip-unique obfuscated execution technology.
  • Furthermore, the approach hardens against micro-probing attacks by establishing fine-grained secure instruction zones, as small as basic blocks: information extracted from a secure zone is not sufficient to compromise another zone. Instructions in each secure zone are uniquely and randomly encoded. Furthermore, execution can be rendered such that the lifetime of information used to decode an instruction in a secure zone is minimized to the very short durations necessary for the instruction's execution. As soon as decoding of an instruction is completed, the information required for decoding can be discarded.
  • The randomization of encoding and execution can be finalized at runtime to achieve a chip unique random execution. Attacking one chip would not help in extracting information that can be used in another chip.
  • These features provide considerable benefits in defending against sophisticated security attacks.
  • Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Although methods and materials similar or equivalent to those described herein can be used in practice or in the testing of the present invention, suitable methods and materials are described below. In addition, the materials, methods, and examples are illustrative only and are not intended to be limiting.
  • Other features and advantages of the invention will become apparent from the following description, including the claims and drawings.
  • DRAWINGS
  • FIG. 1 is a block diagram comparing a conventional processor framework (left) with a processor framework relying on invention (right). An embodiment of such a processing device is described in embodiment 1.
  • FIG. 2 shows an example microprocessor pipeline diagram implementing embodiment 1.
  • FIG. 3 shows an example security mutation instruction encoding in the ISA.
  • FIG. 4 shows a block level diagram of protecting an AES cryptographic implementation with security approach (detailed in embodiment 2).
  • FIG. 5 shows how a block diagram of how a digital filter can be protected with security approach (detailed in embodiment 3).
  • FIG. 6 shows an example of applying mutation instruction in a basic block of a computer program consisting of instructions and how mutation is applied to each instruction. The figure shows how the information coming in can be used to decode the instruction at runtime. The information encoding allows using randomly selected encodings. In other embodiments, the approach can be used to convert from one fixed ISA to another ISA targeting a flexible hardware implementation as opposed to security.
  • DESCRIPTION Embodiment 1 Security Microprocessor with Randomized Encoding and Execution
  • A security processor in this embodiment is based on a suite of innovative technologies across compiler, instruction set architecture, and micro-architecture layers (see FIG. 1 for a comparison with a conventional processor). A key aspect is the compiler-driven approach 104 for instruction obfuscation, where instruction encodings 106 are randomized. The micro-architecture supports this scrambled instruction execution 105.
  • Execution in conventional processors is based on a fixed encoding of all instructions 103 and a compiler 101 that focuses on generating the sequences of instructions for a computer program. This allows for easy reverse engineering, easily identifiable internal points for microprobing, and a variety of side-channel attacks at runtime like Differential Power Analysis (DPA) in the processor 102. DPA is based on correlating the instructions with operations completed using power measurements and statistical analysis. By contrast, the processor embodiment described here is based on the fact that, with suitable support, the encoding of instructions can be changed at fine granularity and even randomized, and instructions can be executed in this format.
  • The basic idea of the encoding approach is to add security control instructions during compile-time code-generation; these control instructions embed guidance or hints related to how subsequent instructions should be decoded at runtime. The actual encoding of instructions can then be generated randomly: the instructions during execution would be still decodable with the help of the embedded hints in the control instructions. Of course the requirement is that the associated hints are available at runtime at the time a particular instruction is decoded. Each instruction in an executable can be encoded with an encoding scheme described or mutated by such a security control instruction. This is achieved by a security-focused code generation that can be completed at compile time or runtime.
  • The encoding of the control instructions themselves is similarly randomly generated and their decoding is completed with the help of other earlier control instructions. The embedded compile-time structures and built-in code-generation also support a final step of code-generation at runtime. A chip-unique encoding scheme can be created during the first power-on of the chip by randomly modifying the payload of the security/mutation instructions and rewriting the code based on the new mutations. This runtime step is enabled by symbolic information inserted into the binary by the compiler. The root of a runtime chip-unique modification can be based on a scheme leveraging a non-deterministic Random Number Generator and on-chip persistent memory cells. Other schemes can be based on codes derived with a die-specific deterministic circuit or the RTL state created by a randomly generated initialization sequence of instructions stored in persistent memory. This initialization sequence can be created at runtime inside a chip to make the sequence unique across chips.
  • Another aspect is that the code-generation in this embodiment introduces ambiguous control-flow between blocks fundamentally breaking up the code into secure zones: as each zone is uniquely obfuscated, compromising one zone would not make breaking into another zone simple.
  • Security Mutation Instructions and Secure Zones:
  • Before discussing the different types of mutations, FIG. 5 shows an example of using security mutations. In the figure, shown for a basic block 615, there is an incoming instruction encoding template called Mi. This template is randomly generated and possibly mutated randomly prior to this basic block. All instructions following in the BB615 are using the template when they are decoded unless the template is changed in the block.
  • The Mi shown in the figure can be changed with inserted security mutation instructions ssi referred to with 501. The region following the ssi instruction changes the encoding to Mi+1 referred to as area 504.
  • This way, instructions can be having an encoding that is randomly created and encoding is continuously mutated whenever ssi instructions are encountered. The code is generated and organized in such a way that decoding is made possible during execution. The mutation instructions, like ssi, are also randomly encoded. For example, ssi in the example is encoded with template Mi.
  • As shown, in addition to mutation instructions, other mutations based on the instruction address can be used and combined with mutations with instructions or otherwise. This allows a modification of an encoding on potentially every instruction.
  • There are three types of instruction mutations that occur in this embodiment. Implicit mutations are hardware-generated mutations that are expected but not explicit in the software. Example of usage includes the initialization phase of these processing cores. A second type of ISA mutation is through static security/mutation instructions based on immediates. This type is shown in FIG. 3: opcode is 301 defines how the payload should be interpreted and payload 302 defines the mutation payload.
  • A third type of mutation instruction has a register-defined payload. These instructions can be used and inserted in a number of places in safe zones. When inserted at the top of the zone they modify the encoding of the following instructions of the zone but their encoding is happening with an incoming mutation defined in another safe zone. Mutations can also be added elsewhere as the only condition is that they must be available at the time a particular safe zone (they enable decode) is decoded at runtime.
  • There are two typical usage scenarios for the register-defined mutations: 1) a constant payload is moved to the register in a previous secure zone; or 2) the payload is made dependent on a memory-mapped location that could be either internally-generated or external to the processing core in the embodiment (memory-mapped IO).
  • These mutations allow implementing schemes where a mutation is tied to a different secure zone than where the mutation instruction resides or depends on outside events.
  • In addition to mutation instructions, the processing core in the embodiment also uses an address-based obfuscation scheme with rotating keys: this, in combination with the mutation instructions, creates a unique encoding for almost every instruction in a binary.
  • The mutation payload in an explicit mutation instruction is randomly generated at compile-time and/or runtime; instructions in the affected zone are transformed accordingly during compile-time and/or runtime.
  • A mutation instruction encodes a bit permutation such as an XOR operation and rotation of bits as defined by its payload. Because the bit permutations are simple operations, the decoding of instructions is done on-the-fly in the processor pipeline.
  • Each secure zone is based on a random ISA encoding and ends with an ambiguous branch. There is no correlation between the encodings used. Secure zones are linked together in a random order at compile-time, creating a fully random layout. A binary in the embodiment is protected against differential binary analysis as every compilation would result in a different set of random mutations and layout.
  • Pipeline Design: A pipeline design is shown in FIG. 2. The different types of mutations on instruction encodings are resolved in the decode stage 201 in hardware blocks 203 and 204. 203 represents decoding due h/w based implicit mutations such as discussed above. The block 204 represents mutations due to the ssi security mutation instructions. Any given time there is a mutation Mi available to be used. This Mi can be changed in different ways as mentioned earlier as instructions are decoded and executed. The actual mutation operations are fine grained and therefore can be kept simple so the impact on the decode stage to set up control signals is minimized. This pipeline implementation is not intended to be limiting. Other pipeline implementations are possible including compiler-driven approaches as well as single and multiple issue designs based on speculative implementations with Reservation Stations, Reorder Buffer, Result Shift Registers, virtual registers, etc.
  • First Power On: During the first power-on, additional randomization of a software binary executing on the processor in the embodiment can be supported, making each binary chip-unique without requiring a separate compilation for each chip. During the first startup some or all of the mutation payloads and the rotating keys can be replaced with (runtime) chip-unique random numbers that are persistent across power-on cycles; instructions in the affected secure zones are rewritten at the same time. The compiler embeds enough symbolic information to make this step computationally efficient and straightforward at runtime. A chip-unique encoding is enabled with the help of die-specific circuitry such as based on process-variation. Another approach is based on encoding the die-specific access latency (similarly due to process-related variation) in SRAM arrays. Another alternative is to have a few persistent memory cells on the die, written once by the processing core's non-deterministic random number generator. At the end of the initial boot even the startup code can be modified such that its decoding is based on a chip-unique implicit mutation.
  • Protection Provided by the Processing Cores in the Embodiment
  • At the heart of the embodiment is a unique randomized encoding and execution approach: 1) these processing cores execute instructions whose encodings can be randomly generated; 2) instructions' encodings can be further randomized at runtime in a chip-unique manner; 3) associated code-generation creates secure zones—compromising one zone would not make breaking into another zone easy; 4) this processing core's execution and switching activity cannot be correlated with the operations it executes because its execution remains obfuscated deep into its pipeline; 5) several techniques across compiler-architecture layers are used to additionally mask the power profile of operations during execution in addition to the inherent masking due to obfuscated execution.
  • The randomization affects all state in the processor including buses, caches, branch address tables and branch target address caches (BTAC) and register files. In the case of BTACs its content is randomly kept with the same encoding as the branch instruction's encoding. That means that when the branch instruction is decoded, even BTAC information becomes accessible for the specific branch. Other branch targets in the BTAC would, however, be protected as they are encoded with another branch's encoding that is independent from the current encoding. In the case the register file what registers are used is randomly set up at the initialization time. Content can be similarly mutated. Instruction memory is automatically protected due to the obfuscated encoding. Additional techniques can be used to protect data memory. The compiler maps each temporary memory access statically to a consumer-producer group called a location set; these are extracted by the compiler and/or rely on additional user information. As both memory reads and writes belonging to a location set would use the same obfuscation, correctness of execution is maintained. At runtime, random keys are read in and masking happens in the software uniquely for each location set. The masking varies after each power on or reset. All persistent memory (on-chip as well as off-chip) can be encrypted with a DPA-resilient AES leveraging similarly the obfuscated execution. A protection example of an AES module is presented in a subsequent embodiment.
  • Protection Against Black-Box Reverse Engineering Attacks: A brute-force attack against the instruction obfuscation in this embodiment would consist of quickly running through all possible scrambling permutations and filtering out those which are obviously wrong. To give an approximate idea of breaking this encoding one would need to try 232 permutations (for a 32-bit ISA) for each instruction and try to combine variable length sequences of such instructions into valid instruction sequences. The processor ISA opcodes are mapped uniformly across operations making all bit permutations valid. Furthermore, it would be impossible to distinguish real security instructions from permutations of other ordinary instructions. It is easy to show that brute-force attacks against this scheme would be therefore too complex (from the point of view of computational and storage complexity) to be practical. The reason is that all possible bit patterns in the instruction set are legal and all possibilities would have to be considered. Note that the solution does not in fact require that all bit permutations are valid and another embodiment might choose to reserve instruction space for future extensions. The reason is that if an extremely high fraction of the possible bit patterns in the instruction set is legal, simply filtering out permutations that are syntactically incorrect would not greatly reduce the number of possibilities that would have to be considered. Moreover, in practice the length of a safe zone is not known so different lengths would need to be tried.
  • Protection against Side-Channel Attacks: DPA is based on statistically correlating differences in power profile across instruction sequences at key points. This embodiment, works by breaking up the correlation necessary for successful DPA attacks. By decoupling encoding from execution and combining it with other compiler-driven architecture techniques to randomize the power profile of operations—note that the control instructions are hidden by the obfuscated instruction encoding—the processing core can be protected against side-channel attacks like DPA.
  • Because the processing core's execution in the embodiment is kept obfuscated, the actual switching activity on internal buses, logic and memory structures cannot be correlated with the instructions. Moreover, the same type of instruction has many different encodings during execution so probing the system with different instructions would not work. The only activity that could provide a power signature of the operation is the switching activity in the Arithmetic Logic Unit (ALU) stage. The embodiment has special techniques and ISA to defend against power-analysis based on ALU power traces. These techniques can be turned on in sections of code that are security-sensitive against DPA during the security focused compilation.
  • Examples of techniques in the embodiment for ALU masking are operation masking and phase masking.
  • 1) Operation Masking—It is known that the power consumption varies with each arithmetic and logic operation (for example, an AND will not consume the same power as an ADD operation). A variety of techniques are used to normalize/randomize the power profile, including: Randomly switching ON various arithmetic and logic units even when they are not used by the instruction being executed—the added additional power consumption helps mask the actual operations; Randomly switching input operands to arithmetic and logic units being used by the instruction being executed changes the power consumed by the operation by activating different transistor paths in the circuit. By doing this one can mask the actual input data values to each arithmetic and logic unit. Both this and the previous technique are fairly easy to support and do not affect performance;
  • Some operations, like multiplication, consume significantly more power than other operations, and it is important to mask these operations since attackers can use the power peaks created by these operations as a pivot to find patterns in the execution flow. Letting these units consume power throughout the execution in order to mask actual usage might not always be a good solution since the overall power consumption will increase significantly. The processing core in this embodiment employs a solution to mask the power consumption of these operations by randomly replacing these operations, at runtime, with SWIs (Software Interrupts).
  • These SWIs invoke performance-optimized code to perform requested operation in an alternate way.
  • Another technique is based on multiple path executions—these are equivalent implementations with different power profiles that are randomly selected during runtime.
  • Phase Masking is based on randomly inserting pipeline stalls during execution of security-sensitive codes the boundaries of these phases can be further masked.
  • Another side-channel attack described in the literature is based on injecting faults. Fault-injection attacks would be practically impossible as the encoding and execution of instructions is kept confidential: an attacker cannot find meaningful attack points to inject faults.
  • Protection against Advanced Micro-probing: A processing core in this embodiment has an effective protection against sophisticated micro-probing attacks such as those based on Focus Ion Beam (FIB). In this attack scenario, we assume that the attacker has the ability to understand the design after reverse engineering some of its circuits with Scanning Electron Microscopy (SEM)—note that the randomized execution makes it considerably harder even to find useful probing points compared to conventional designs.
  • Nevertheless, let us assume that an attacker would somehow find the encoding of an instruction Ik and also uncover the mutation used for the instruction, Sk, and has access to the binary. The embodiment would still limit the information this attacker can extract to a few instructions, typically less than the size of a basic block (or secure zone). If the attacker tries to reverse engineer instructions going backwards in the address space from Ik, it would after a few instructions enter another secure zone based on a different encoding not related to the current uncovered mutation Sk (because mutations are randomly picked for each secure zone). If the attacker were to try to go forward, he will always reach an ambiguous, e.g., register based, branch instruction at the end of the zone with a branch address that is defined in a previous secure zone and therefore protected.
  • The microarchitecture in the embodiment can also use static-instruction-based implicit branches that can be inserted in an earlier zone effectively replacing a conditional branch from the binary. Static instruction are control instructions containing control information of various sort. Implicit branching would mean that the control instruction would contain information for a branch at the end of the basic block often in addition to other information. This allows removing the actual branch instruction and completing the branch prediction ahead of time; encoding of the implicit branching can be made differ from the encoding of the safe zone where the branch it replaces normally resides. Secure zones end with an ambiguous unconditional branch with their target address defined in a different secure zone. This enables separation between the encoding used in zones and also creates a randomized layout. The performance overhead of the two branches per secure zone is mitigated by one of them often being an implicit branch, which is a zero-cycle branch in terms of execution because branch prediction is performed ahead of the control-flow it needs to encode.
  • The fact that application codes are based on secure zones increases the hurdles for an attacker because as many successful microprobings as secure zones would be required on many points to even have a chance to gain access to IP hidden in a processing core in this embodiment. The processing core in this embodiment has a number of techniques and a layered defense making this extremely difficult to attack.
  • First, each mutation has a very short lifetime of just a few cycles and is discarded after use (the next secure zone is at an unknown address that is ambiguous and will use a different random mutation key). This is not the case during instruction execution in a conventional processor where if the instructions are encrypted, the same key is used typically every time an instruction is decrypted.
  • Second, the very first mutation in this core is created at randomized times measured from reset—this is accomplished, e.g., by inserting random stalls during the initialization—and is implicit and chip-unique, re-generated at every power-on.
  • In addition, dynamic mutations (these are mutation instructions which are register-based with the register loaded from a memory-mapped IO location in a previous zone) can be correlated with either external or on-chip time-specific events—the attacker would need to capture those events and monitor many points simultaneously to have a chance to bypass the associated secure zones.
  • Protection against Reverse Engineering with RTL Simulation:
  • The attack in this scenario assumes accurate-enough extraction of the design such that an RTL-level simulation can be attempted where instructions can be executed and probed. The embodiment can protect against this attack similarly with a layered defense. First, a core in this embodiment requires comprehensive reverse engineering and additional factors would need to be true for an attacker to have a chance to succeed with simulation: conventional execution would not necessarily require a complete RTL model to simulate most of the instructions—a core in this embodiment would require that because its decoding/ISA of instructions in some secure zones, including the initial one, is tied to a comprehensive RTL state derived from many areas of the design and state that would normally not be required for instruction execution. Secondly, these cores use die-specific (due to process variation) circuits like [41] and similar techniques to make some of the encoding sequence invisible with invasive imaging alone, such as Scanning Electron Microscopy (SEM). Additional protection is introduced by adding a small persistent on-chip memory with its content filled at first power-on with the help of a non-deterministic hardware RNG. An attacker would need to be able to bypass these with microprobing and complete microsurgery to read content by generating the addresses, in addition to also successfully reverse-engineering the entire chip. After reverse engineering, a memory model would need to be constructed at the RTL level to simulate execution of instructions. One key aspect is that even if there is only a small discrepancy in the created RTL for the processor in this embodiment, the instructions would likely not decode at all as decoding is tied to a fairly accurate RTL state across the whole chip. This means that if there is a tamper-protection mechanism in place that would prohibit a fully accurate reverse engineering (even a very small fraction of the die), the RTL simulation would likely not work despite the other micro-probing requirements for a successful attack being all met.
  • The embodiment has additional defense enabled by its dynamic mutation instructions at the boundary between certain secure zones. These mutations are fine-grained core-external or die-specific; they are equivalent to execution authorizations required to enter certain zones, i.e., by allowing correct instruction decoding in those zones. If this authorization is externally provided and in a time-specific manner (e.g., by another sub-system), the RTL simulation would fail as it is considerably slower than the silicon chip, and as a result, the decoding of the instructions executing on the core would fail.
  • An attacker cannot use multiple chips to complete an attack. This is because there is no secret shared across the chips. That means that every chip would need to be attacked separately and information gained from one chip would not help in attacking any other chip.
  • Protection against Cloning: Cloning attacks would require copying the design transistor-by-transistor and associated software bit-by-bit. By executing a uniquely generated code, of which decoding is tied to chip or die-unique aspects, effective defense against cloning can be provided. Even if a chip incorporating a processing core such as described above would be replicated exactly at the transistor level and a copy of the software binary is available, the software would not run on the new chip and the chip would not function.
  • Embodiment 2 Protecting Cryptographic Implementations Against High-Order Differential Power Analysis
  • An embodiment showing protecting a cryptographic implementation is shown below. As mentioned in the standard and noted in the Advanced Encryption Standard (AES) literature, AES is susceptible to differential power analysis (DPA) attacks.
  • The embodiment is based on a software-hardware approach; it is based on the microprocessor technology described earlier for randomization of execution and internal microprocessor switching activity. The objective is to provide high-order DPA protection with minimal area overhead and performance impact on AES.
  • AES is a round-based symmetric block cipher, working on 128 bit chunks of data. The AES algorithm is based on 4 different operations per round, as well as some pre- and post-processing. These operations are SubBytes, ShiftRows, MixColumn, and AddRoundKey. More details can be found in the standard outlining document.
  • One of the main concerns with the AES algorithm is its susceptibility to DPA attacks. Side-channel attacks, such as DPA, work due to the fact that correlation exists between physical measurements taken during execution and the internal state of the algorithm being executed.
  • In FIG. 4 a standard AES algorithm 401 is shown at the top. The microprocessor core with the techniques outlined in the patent, including randomization of encoding and execution, is referred to as TGM.
  • In the AES algorithm an attacker may target the time at which the input data and key are operated on for the first time (see highlighted point 402 in the figure). By monitoring the average power consumption at this point, a correlation can be made between the input data (known to the attacker) and the secret key, to eventually find the key. In order to combat this DPA attack, approaches based on masking the input data have been introduced. Data masking is used to remove the power-trace related correlation between the (known) input data and the data used in the algorithm with the key. Mask correction must be performed during the algorithm (as SBox lookups in the SubBytes stage are non-linear operations) to ensure that the masking will not affect the output cipher-text and that the cipher-text can still be decrypted with the same key. Although various approaches, based on either using separate SBox table(s) for each possible mask or by replacing the SBox lookup with logic to perform equivalent transformation, have been proposed and offer protection against first-order DPA, scaling such a solution to higher order DPA is extremely difficult.
  • See for example the middle implementation 403 in FIG. 4 that uses data masking: while it protects against first-order DPA it is vulnerable to second-order DPA at point 410. In a second-order DPA attack, the attacker monitors the power profile when the mask is exclusive-or-ed with the (known) input data. Capturing traces for both this point and the point when the masked data is used with the key in stage A is sufficient for an attacker to correlate the mask, the input data, and the secret key bit by bit.
  • The proposed third AES implementation 406 shown in the bottom sub-figure in FIG. 4 is leveraging the strength of TGM security core 408 that is based on an embodiment of the randomized encoding and execution approach.
  • During AES encryption the TGM calculates a reversible function, ƒ, in software that takes as inputs the key, the data to be encrypted and a chip-unique random number Z shown as 409 (persistent across power-on cycles). The TGM execution is resistant to high-order DPA as switching activity in TGM buses, memory, etc, is randomized by the random encoding and execution model and by operation masking techniques presented before. Due to the high-order DPA protection in TGM that de-correlates data d from dtgm and key k from ktgm (see the bottom part of FIG. 4), the AES module is now protected against DPA.
  • The additional hardware masking is, in fact, not necessary, since the correlation between the original input data and the data worked on with the key has been removed in the TGM portion of the solution. The flow described above is for encryption; for decryption the initial TGM software layer would pass the data to block A and a TGM software layer will perform the inverse function of f on the data. Furthermore, any DPA would require running the AES in isolation or a modification of the code; however, as the TGM component of AES would not decode correctly without the execution of another secure zone before this code (which in turn requires another secure zone to be decoded and so on) and a modification of that code would essentially mean knowing all the decoding related mutations; a successful attack is therefore extremely unlikely. The performance impact of this scheme is minimal: the TGM-based functionality and the other stages of the AES can be pipelined. Assuming a 256-bit AES, with 16 rounds, the requirement for pipelining without penalty is that the TGM component is completed in less than 16 cycles, assuming each AES round takes one cycle without TGM.
  • Embodiment 3 Protecting Hardware Intellectual Property by Controlling with Security Processor
  • An example is provided in the context of digital filters. Other types of hardware modules could be addressed in a similar way.
  • At the heart of modern processing and communication systems are digital filters (DF) that compute a quantized time-domain representation of the convolution of analog signals in digitized form. DFs can be found in almost any military system from avionic to sonar sub-systems and applications such as image recognition and target tracking. The characteristics (i.e. transfer function, amplitude response, etc.) of a DF can leak information about the intended function of the signal processing system to which it belongs, during both the manufacturing and the deployment of the ASIC.
  • To protect a DF, the key characteristics must be protected: this includes its type (i.e., whether it is IIR or FIR), order of filter (number of previous inputs and/or outputs used to calculate current output), filter coefficients (weighting function of the filter), and algorithm used to adaptively change the coefficients at runtime—if the DF is adaptive.
  • FIG. 5 (top, 501) shows typical implementations for an adaptive filtering algorithms. Filter coefficients 503 weigh the data shifted down the delay line and are responsible for, in conjunction with the number of taps (delays), the amplitude response of the filter. In a non-adaptive filter, the filter coefficients are generally pre-calculated and stored in non-volatile memory. In adaptive filters, an adaptive algorithm 502 computes these coefficients on the fly in response to changing input samples.
  • FIG. 5 (bottom figure) shows an example of how a DF can be protected with TGM. The task of selecting the coefficients in a non-adaptive DF, the algorithm to adaptively compute the coefficients 506 in an adaptive DF (shown as 505), and controlling the order of the coefficients are moved to the TGM core (see 504, 505); these signals are memory-mapped and controlled by secured TGM instructions. To control the programming of the order, support masking, and provide the ability to change on the fly we assume the availability of redundant taps. By transferring key computational steps and the configuration of the DF design to the TGM core, we can harden it against both online and offline attacks.
  • In a typical ASIC implementation the interconnection between the adders, multipliers, and delay elements in a DF is predetermined and can be reverse engineered through Scanning Electron Microscopy (SEM).
  • When the filter is used with the TGM core (implementing randomized encoding and execution), the interconnection is programmed at start-up and can be changed at regular intervals when the filter is in use. This prevents attackers from knowing how the taps are interconnected with respect to the input, output, and from establishing an order for the filter coefficients. In addition, to thwart micro-probing attacks based on FIB probes, the TGM part could implement coefficient masking: e.g., it can mask the actual filter coefficients sent to the filter hardware (a few at a time depending on the number of redundant taps) with randomly generated mask values in the TGM core.
  • To correct the error added to the weighting function of the DF (before it affects the output), the TGM software compensates the weight by altering the coefficients in the redundant taps of the filter accordingly. Masking ensures that the filter coefficients, even for a non-adaptive filter, change constantly, making it extremely difficult for an attacker to figure out whether the filter is adaptive or not or find the coefficients.
  • Other masking schemes are possible, e.g., resembling time-hopping, if the component following the DF would be similarly controlled by the TGM. A TGM solution enables occasional integrity checking on the DF hardware: the transfer function of the DF would be run in the TGM in parallel with the DF and outputs checked for matching. As integrity checking can lag the rate at which the hardware components of the DF process the input, the checking mechanism is not on the critical path of the DF.
  • Overview TGM Core Microarchitecture used in this embodiment: A TGM core is a 32-bit compiler-driven single-issue (or dual-issue) processor that supports 8-16-32-64-bit operations, has cryptographic hardware acceleration, and sophisticated compiler-driven power management. TGM uses both a hardware-based non-deterministic random number generator (NDRNG) and a deterministic random number generator (DRNG) that is FIPS 140-2 compliant. It has a physically-mapped compiler-managed memory system. It incorporates additional techniques to protect its data memory. The compiler maps each temporary memory access statically to a consumer-producer group called a location set; these are extracted by the compiler and/or rely on additional user information. As both memory reads and writes belonging to a location set would use the same obfuscation, correctness of execution is maintained. At runtime, random keys are read in and masking happens in the software uniquely for each location set. The masking varies after each power on. All persistent memory (on-chip as well as off-chip) is encrypted with a DPA-resilient AES.
  • Interfacing with Protected Design: An ASIC with built-in TGM might use an interface between the TGM core and the functionality it protects. The TGM core contains a programmable interface which allows software executing on the TGM core to interact with and control hardware components. Since it is possible that the protected hardware components and the TGM core may be operating at different clock speeds, communication between the two will occur via a handshaking protocol. This interface can contain programmable IO lines (similar to GPIO) and a special interrupt port through which the ASIC will be able to interrupt the current task being performed on the TGM in order to initiate a higher priority task.
  • Embodiment 4 Protecting Software Intellectual Property with Add-on Security Processor in Conventional Systems
  • In this embodiment instructions on a second processor co-execute with instructions on the security processor. This security processor can be added on add-on card such as PCI, PCI-e, etc. The instructions executing on the security processor, such as TGM, could also be encrypted before sent for execution. By inserting an instruction of which encoding is randomly created, or encrypted, into the stream of instructions on a lesser security processor, such as with a fixed instruction set, the computer program running on a lesser security processor could be protected against reverse engineering and tampering attacks, also due to the voids created in the computer program now containing obfuscated codes executing on a security processor. The codes that execute on the security processor could be coupled with each other, forming a graph, for the purpose of protecting against replay attacks or removal attacks of some of the codes targeted to execute on the security processor.
  • Other Embodiments
  • The invention is not limited to the specific embodiments described herein. Other types of obfuscation or encryption can be used for instructions and data and combined with other techniques, in other embodiments. The invention can be used to implement other types of security services or functionality than described in the embodiments. Other embodiments not described herein are also within the scope of the following claims.

Claims (21)

1. A method for use with a compiler architecture framework, the method comprising:
performing a compilation process on a computer program;
encoding an instruction with a selected encoding;
encoding the security mutation information in an instruction set architecture of a processor; and
executing a compiled computer program in the processor using an added mutation instruction, wherein executing comprises executing a mutation instruction to enable decoding another instruction.
2. The method of claim 1, wherein instruction encodings are randomly selected.
3. The method of claim 2, wherein the compiled program consists of safe zones and each safe zone has independent instruction encoding.
4. The method of claim 1, wherein a mutation is modified at runtime making an instruction encoding chip unique.
5. The method of claim 1, wherein an instruction encoding depends on device parameter variation on the die.
6. The method of claim 1, wherein an instruction encoding depends on a content of a persistent memory.
7. The method of claim 1, wherein an instruction encoding depends on a hardware state in the processor.
8. The method of claim 1, wherein an instruction encoding depends on an input output event.
9. A processing framework comprising:
machine storage for storing a compiler that is configured to compile a computer program, the compiler being configured to extract static information about the computer program during compilation, the static information being used to add a mutation instruction in the computer program to help decoding another instruction at runtime;
executing, wherein executing comprises storing of the mutation information encoded in a mutation instruction in the processor such that a subsequent instruction can be decoded by using that mutation.
10. The processing device of claim 9, wherein the encoding of an instruction is randomly selected;
11. The processing device of claim 9, wherein an AES module's power profile is protected against information leakage by feeding its input through the processing device.
12. The processing device of claim 9, wherein a hardware logic is protected by controlling a configuration related to its operation through the processing device.
13. An instruction encoding of claim 9, wherein the mutation information is in a register.
14. An instruction encoding of claim 9, wherein the mutation information is in an immediate.
15. An instruction encoding of claim 9, wherein the mutation information is from an IO device.
16. The system of claim 9 comprising of
the processing framework of claim 9;
a second processor executing instructions from a computer program wherein at least one of the instructions executes on the processor framework of claim 9.
17. The processing device of claim 9, wherein execution time is randomized in time across processor reset cycles with random stall insertion.
18. The processing device of claim 9, wherein instructions encode control for functional units.
19. The processing device of claim 9, wherein an operation is replaced with SWIs.
20. The processing device of claim 9, wherein random stall insertion is controlled by a security mutation instruction.
21. The processing device of claim 9, wherein an instruction executing is encrypted.
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Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040010782A1 (en) * 2002-07-09 2004-01-15 Moritz Csaba Andras Statically speculative compilation and execution
US20050108507A1 (en) * 2003-11-17 2005-05-19 Saurabh Chheda Security of program executables and microprocessors based on compiler-arcitecture interaction
US20050114850A1 (en) * 2003-10-29 2005-05-26 Saurabh Chheda Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control
US20050172277A1 (en) * 2004-02-04 2005-08-04 Saurabh Chheda Energy-focused compiler-assisted branch prediction
US20070147156A1 (en) * 2005-12-22 2007-06-28 Sony Computer Entertainment Inc. Methods and apparatus for random number generation
US20070294181A1 (en) * 2006-05-22 2007-12-20 Saurabh Chheda Flexible digital rights management with secure snippets
US7949912B1 (en) * 2009-01-15 2011-05-24 Xilinx, Inc. System and method of securing data stored in a memory
US20120066162A1 (en) * 2010-09-09 2012-03-15 Texas Instruments Incorporated System and Method for Training an Adaptive Filter in an Alternate Domain with Constraints
US20120201380A1 (en) * 2011-02-08 2012-08-09 Fujitsu Limited Communication apparatus and secure module
US20130007881A1 (en) * 2010-03-25 2013-01-03 Irdeto Canada Corporation System and Method for Dynamic, Variably-Timed Operation Paths as a Resistance to Side Channel and Repeated Invocation Attacks
US8359447B1 (en) 2009-01-15 2013-01-22 Xilinx, Inc. System and method of detecting and reversing data imprinting in memory
US20130202105A1 (en) * 2011-08-26 2013-08-08 Kabushiki Kaisha Toshiba Arithmetic device
US20140192975A1 (en) * 2012-10-17 2014-07-10 Elliptic Technologies Inc. System and method for multichannel cryptographic processing
US20150007323A1 (en) * 2011-03-28 2015-01-01 Sony Corporation Information processing apparatus and method, and program
US20150039864A1 (en) * 2013-07-31 2015-02-05 Ebay Inc. Systems and methods for defeating malware with randomized opcode values
US8972744B1 (en) 2008-02-14 2015-03-03 Xilinx, Inc. Preventing data imprinting in memory
US9069938B2 (en) 2006-11-03 2015-06-30 Bluerisc, Inc. Securing microprocessors against information leakage and physical tampering
WO2015119886A1 (en) * 2014-02-06 2015-08-13 Optimum Semiconductor Technologies, Inc. Method and apparatus for enabling a processor to generate pipeline control signals
US9411964B1 (en) 2014-11-24 2016-08-09 Bluerisc, Inc. Characterizing, detecting and healing vulnerabilities in computer code
US9558000B2 (en) 2014-02-06 2017-01-31 Optimum Semiconductor Technologies, Inc. Multithreading using an ordered list of hardware contexts
CN106415589A (en) * 2014-03-31 2017-02-15 爱迪德技术有限公司 Secured electronics device
US9740498B2 (en) 2011-11-15 2017-08-22 Wuxi Dsp Technologies Inc. Opportunistic multi-thread method and processor
US9754112B1 (en) 2014-11-24 2017-09-05 Bluerisc, Inc. Detection and healing of vulnerabilities in computer code
US20170255591A1 (en) * 2013-10-17 2017-09-07 Stmicroelectronics Sa Processing System with a Secure Set of Executable Instructions and/or Addressing Scheme
US10127160B2 (en) * 2016-09-20 2018-11-13 Alexander Gounares Methods and systems for binary scrambling

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3054344B1 (en) * 2016-07-25 2018-09-07 Tiempo Integrated circuit protected.

Citations (97)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4003033A (en) * 1975-12-22 1977-01-11 Honeywell Information Systems, Inc. Architecture for a microprogrammed device controller
US4067059A (en) * 1976-01-29 1978-01-03 Sperry Rand Corporation Shared direct memory access controller
US4079455A (en) * 1976-12-13 1978-03-14 Rca Corporation Microprocessor architecture
US4138720A (en) * 1977-04-04 1979-02-06 Burroughs Corporation Time-shared, multi-phase memory accessing system
US4181942A (en) * 1978-03-31 1980-01-01 International Business Machines Corporation Program branching method and apparatus
US4255785A (en) * 1978-09-25 1981-03-10 Motorola, Inc. Microprocessor having instruction fetch and execution overlap
US4376977A (en) * 1979-08-27 1983-03-15 U.S. Philips Corporation Computer system with scannable program memory
US4382279A (en) * 1978-04-25 1983-05-03 Compagnie Internationale Pour L'informatique Cii-Honeywell Bull (Societe Anonyme) Single chip microprocessor with on-chip modifiable memory
US4434461A (en) * 1980-09-15 1984-02-28 Motorola, Inc. Microprocessor with duplicate registers for processing interrupts
US4435758A (en) * 1980-03-10 1984-03-06 International Business Machines Corporation Method for conditional branch execution in SIMD vector processors
US4450519A (en) * 1980-11-24 1984-05-22 Texas Instruments Incorporated Psuedo-microprogramming in microprocessor in single-chip microprocessor with alternate IR loading from internal or external program memories
US4577282A (en) * 1982-02-22 1986-03-18 Texas Instruments Incorporated Microcomputer system for digital signal processing
US4592013A (en) * 1981-08-21 1986-05-27 International Business Machines Corp. Method and device for addressing a memory
US4649471A (en) * 1983-03-01 1987-03-10 Thomson Components-Mostek Corporation Address-controlled automatic bus arbitration and address modification
US4665495A (en) * 1984-07-23 1987-05-12 Texas Instruments Incorporated Single chip dram controller and CRT controller
US4720812A (en) * 1984-05-30 1988-01-19 Racal-Milgo, Inc. High speed program store with bootstrap
US4803621A (en) * 1986-07-24 1989-02-07 Sun Microsystems, Inc. Memory access system
US4931986A (en) * 1989-03-03 1990-06-05 Ncr Corporation Computer system clock generator for generating tuned multiple clock signals
US4992933A (en) * 1986-10-27 1991-02-12 International Business Machines Corporation SIMD array processor with global instruction control and reprogrammable instruction decoders
US5021993A (en) * 1987-03-31 1991-06-04 Kabushiki Kaisha Toshiba Device for saving and restoring register information
US5111389A (en) * 1987-10-29 1992-05-05 International Business Machines Corporation Aperiodic mapping system using power-of-two stride access to interleaved devices
US5121498A (en) * 1988-05-11 1992-06-09 Massachusetts Institute Of Technology Translator for translating source code for selective unrolling of loops in the source code
US5127091A (en) * 1989-01-13 1992-06-30 International Business Machines Corporation System for reducing delay in instruction execution by executing branch instructions in separate processor while dispatching subsequent instructions to primary processor
US5193202A (en) * 1990-05-29 1993-03-09 Wavetracer, Inc. Processor array with relocated operand physical address generator capable of data transfer to distant physical processor for each virtual processor while simulating dimensionally larger array processor
US5224214A (en) * 1990-04-12 1993-06-29 Digital Equipment Corp. BuIffet for gathering write requests and resolving read conflicts by matching read and write requests
US5276895A (en) * 1986-09-18 1994-01-04 Digital Equipment Corporation Massively parallel array processing system
US5410669A (en) * 1993-04-05 1995-04-25 Motorola, Inc. Data processor having a cache memory capable of being used as a linear ram bank
US5481693A (en) * 1994-07-20 1996-01-02 Exponential Technology, Inc. Shared register architecture for a dual-instruction-set CPU
US5497478A (en) * 1991-03-20 1996-03-05 Hewlett-Packard Company Memory access system and method modifying a memory interleaving scheme so that data can be read in any sequence without inserting wait cycles
US5524223A (en) * 1994-01-31 1996-06-04 Motorola, Inc. Instruction accelerator for processing loop instructions with address generator using multiple stored increment values
US5598546A (en) * 1994-08-31 1997-01-28 Exponential Technology, Inc. Dual-architecture super-scalar pipeline
US5604913A (en) * 1993-08-10 1997-02-18 Fujitsu Limited Vector processor having a mask register used for performing nested conditional instructions
US5608886A (en) * 1994-08-31 1997-03-04 Exponential Technology, Inc. Block-based branch prediction using a target finder array storing target sub-addresses
US5630143A (en) * 1992-03-27 1997-05-13 Cyrix Corporation Microprocessor with externally controllable power management
US5638525A (en) * 1995-02-10 1997-06-10 Intel Corporation Processor capable of executing programs that contain RISC and CISC instructions
US5637932A (en) * 1990-11-27 1997-06-10 Hitachi, Ltd. Power consumption control system
US5721893A (en) * 1996-05-14 1998-02-24 Hewlett-Packard Company Exploiting untagged branch prediction cache by relocating branches
US5727229A (en) * 1996-02-05 1998-03-10 Motorola, Inc. Method and apparatus for moving data in a parallel processor
US5737572A (en) * 1995-06-06 1998-04-07 Apple Computer, Inc. Bank selection logic for memory controllers
US5737749A (en) * 1996-05-20 1998-04-07 International Business Machines Corporation Method and system for dynamically sharing cache capacity in a microprocessor
US5742804A (en) * 1996-07-24 1998-04-21 Institute For The Development Of Emerging Architectures, L.L.C. Instruction prefetch mechanism utilizing a branch predict instruction
US5752068A (en) * 1994-08-23 1998-05-12 Massachusetts Institute Of Technology Mesh parallel computer architecture apparatus and associated methods
US5758112A (en) * 1994-10-14 1998-05-26 Silicon Graphics, Inc. Pipeline processor with enhanced method and apparatus for restoring register-renaming information in the event of a branch misprediction
US5758176A (en) * 1994-09-28 1998-05-26 International Business Machines Corporation Method and system for providing a single-instruction, multiple-data execution unit for performing single-instruction, multiple-data operations within a superscalar data processing system
US5857104A (en) * 1996-11-26 1999-01-05 Hewlett-Packard Company Synthetic dynamic branch prediction
US5864697A (en) * 1996-06-28 1999-01-26 Texas Instruments Incorporated Microprocessor using combined actual and speculative branch history prediction
US5864707A (en) * 1995-12-11 1999-01-26 Advanced Micro Devices, Inc. Superscalar microprocessor configured to predict return addresses from a return stack storage
US5870581A (en) * 1996-12-20 1999-02-09 Oak Technology, Inc. Method and apparatus for performing concurrent write operations to a single-write-input register file and an accumulator register
US5872987A (en) * 1992-08-07 1999-02-16 Thinking Machines Corporation Massively parallel computer including auxiliary vector processor
US5875464A (en) * 1991-12-10 1999-02-23 International Business Machines Corporation Computer system with private and shared partitions in cache
US5875324A (en) * 1995-06-07 1999-02-23 Advanced Micro Devices, Inc. Superscalar microprocessor which delays update of branch prediction information in response to branch misprediction until a subsequent idle clock
US5884057A (en) * 1994-01-11 1999-03-16 Exponential Technology, Inc. Temporal re-alignment of a floating point pipeline to an integer pipeline for emulation of a load-operate architecture on a load/store processor
US5887166A (en) * 1996-12-16 1999-03-23 International Business Machines Corporation Method and system for constructing a program including a navigation instruction
US5903750A (en) * 1996-11-20 1999-05-11 Institute For The Development Of Emerging Architectures, L.L.P. Dynamic branch prediction for branch instructions with multiple targets
US6021484A (en) * 1997-11-14 2000-02-01 Samsung Electronics Co., Ltd. Dual instruction set architecture
US6044469A (en) * 1997-08-29 2000-03-28 Preview Software Software publisher or distributor configurable software security mechanism
US6049330A (en) * 1997-08-28 2000-04-11 Oak Technology, Inc. Method and apparatus for optimizing storage of compressed images in memory
US6052703A (en) * 1998-05-12 2000-04-18 Oak Technology, Inc. Method and apparatus for determining discrete cosine transforms using matrix multiplication and modified booth encoding
US6058469A (en) * 1995-04-17 2000-05-02 Ricoh Corporation System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization
US6067609A (en) * 1998-04-09 2000-05-23 Teranex, Inc. Pattern generation and shift plane operations for a mesh connected computer
US6067622A (en) * 1996-01-02 2000-05-23 Moore; Steven Jerome Software security system using remove function to restrict unauthorized duplicating and installation of an application program
US6175892B1 (en) * 1998-06-19 2001-01-16 Hitachi America. Ltd. Registers and methods for accessing registers for use in a single instruction multiple data system
US6178498B1 (en) * 1997-12-18 2001-01-23 Idea Corporation Storing predicted branch target address in different storage according to importance hint in branch prediction instruction
US6212542B1 (en) * 1996-12-16 2001-04-03 International Business Machines Corporation Method and system for executing a program within a multiscalar processor by processing linked thread descriptors
US6216223B1 (en) * 1998-01-12 2001-04-10 Billions Of Operations Per Second, Inc. Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor
US6219796B1 (en) * 1997-12-23 2001-04-17 Texas Instruments Incorporated Power reduction for processors by software control of functional units
US20010037450A1 (en) * 2000-03-02 2001-11-01 Metlitski Evgueny A. System and method for process protection
US6341371B1 (en) * 1999-02-23 2002-01-22 International Business Machines Corporation System and method for optimizing program execution in a computer system
US6381668B1 (en) * 1997-03-21 2002-04-30 International Business Machines Corporation Address mapping for system memory
US6385720B1 (en) * 1997-07-14 2002-05-07 Matsushita Electric Industrial Co., Ltd. Branch prediction method and processor using origin information, relative position information and history information
US6393520B2 (en) * 1997-04-17 2002-05-21 Matsushita Electric Industrial Co., Ltd. Data processor and data processing system with internal memories
US20030014742A1 (en) * 2001-07-09 2003-01-16 Sasken Communication Technologies Limited Technique for compiling computer code to reduce energy consumption while executing the code
US20030041230A1 (en) * 1998-12-30 2003-02-27 Lihu Rappoport Method and system for branch target prediction using path information
US6529943B1 (en) * 1998-04-24 2003-03-04 Canon Kabushiki Kaisha Server, client, client server system, method for controlling them and storage medium therefor
US6539543B1 (en) * 1999-11-29 2003-03-25 Adelante Technologies, Nv Method and apparatus for compiling source code by flattening hierarchies
US20030066061A1 (en) * 2001-09-29 2003-04-03 Youfeng Wu Method and apparatus for performing compiler transformation of software code using fastforward regions and value specialization
US6550004B1 (en) * 1999-11-05 2003-04-15 Ip-First, Llc Hybrid branch predictor with improved selector table update mechanism
US6560776B1 (en) * 2000-02-18 2003-05-06 Avaya Technology Corp. Software installation verification tool
US6571331B2 (en) * 1999-03-18 2003-05-27 Ip-First, Llc Static branch prediction mechanism for conditional branch instructions
US6675305B1 (en) * 2000-08-04 2004-01-06 Synopsys, Inc. Power saving in a USB peripheral by providing gated clock signal to CSR block in response to a local interrupt generated when an operation is to be performed
US20040010783A1 (en) * 2002-07-09 2004-01-15 Moritz Csaba Andras Reducing processor energy consumption using compile-time information
US20040010679A1 (en) * 2002-07-09 2004-01-15 Moritz Csaba Andras Reducing processor energy consumption by controlling processor resources
US20040010782A1 (en) * 2002-07-09 2004-01-15 Moritz Csaba Andras Statically speculative compilation and execution
US20040015923A1 (en) * 2001-02-16 2004-01-22 Craig Hemsing Apparatus and method to reduce memory footprints in processor architectures
US6687838B2 (en) * 2000-12-07 2004-02-03 Intel Corporation Low-power processor hint, such as from a PAUSE instruction
US6732253B1 (en) * 2000-11-13 2004-05-04 Chipwrights Design, Inc. Loop handling for single instruction multiple datapath processor architectures
US20050055678A1 (en) * 2003-08-28 2005-03-10 Ryuji Sakai Method and apparatus for managing software in computer system using virtual machine
US20050066153A1 (en) * 1998-10-12 2005-03-24 Harshvardhan Sharangpani Method for processing branch operations
US20050108507A1 (en) * 2003-11-17 2005-05-19 Saurabh Chheda Security of program executables and microprocessors based on compiler-arcitecture interaction
US20050114850A1 (en) * 2003-10-29 2005-05-26 Saurabh Chheda Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control
US6988183B1 (en) * 1998-06-26 2006-01-17 Derek Chi-Lan Wong Methods for increasing instruction-level parallelism in microprocessors and digital system
US7036118B1 (en) * 2001-12-20 2006-04-25 Mindspeed Technologies, Inc. System for executing computer programs on a limited-memory computing machine
US7162617B2 (en) * 2003-02-14 2007-01-09 Fine Arc Incorporated Data processor with changeable architecture
US7185215B2 (en) * 2003-02-24 2007-02-27 International Business Machines Corporation Machine code builder derived power consumption reduction
US20070104077A1 (en) * 2003-10-02 2007-05-10 Mediatek Inc. Apparatus for detecting a pre-pit signal
US7487340B2 (en) * 2006-06-08 2009-02-03 International Business Machines Corporation Local and global branch prediction information storage
US7676661B1 (en) * 2004-10-05 2010-03-09 Xilinx, Inc. Method and system for function acceleration using custom instructions

Family Cites Families (151)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3603934A (en) 1968-07-15 1971-09-07 Ibm Data processing system capable of operation despite a malfunction
US4050058A (en) 1973-12-26 1977-09-20 Xerox Corporation Microprocessor with parallel operation
US4042972A (en) 1974-09-25 1977-08-16 Data General Corporation Microprogram data processing technique and apparatus
US4037090A (en) 1974-11-19 1977-07-19 Texas Instruments Incorporated Multiphase clocking for MOS
CA1059639A (en) 1975-03-26 1979-07-31 Garvin W. Patterson Instruction look ahead having prefetch concurrency and pipe line features
US4090247A (en) 1975-08-11 1978-05-16 Arthur D. Little, Inc. Portable data entry device
US4101960A (en) 1977-03-29 1978-07-18 Burroughs Corporation Scientific processor
US4128873A (en) 1977-09-20 1978-12-05 Burroughs Corporation Structure for an easily testable single chip calculator/controller
JPS5616248A (en) 1979-07-17 1981-02-17 Matsushita Electric Ind Co Ltd Processing system for interruption
US4354228A (en) 1979-12-20 1982-10-12 International Business Machines Corporation Flexible processor on a single semiconductor substrate using a plurality of arrays
US4463421A (en) 1980-11-24 1984-07-31 Texas Instruments Incorporated Serial/parallel input/output bus for microprocessor system
US4403303A (en) 1981-05-15 1983-09-06 Beehive International Terminal configuration manager
US4541045A (en) 1981-09-21 1985-09-10 Racal-Milgo, Inc. Microprocessor architecture employing efficient operand and instruction addressing
US4538239A (en) 1982-02-11 1985-08-27 Texas Instruments Incorporated High-speed multiplier for microcomputer used in digital signal processing system
US4607332A (en) 1983-01-14 1986-08-19 At&T Bell Laboratories Dynamic alteration of firmware programs in Read-Only Memory based systems
US4626988A (en) 1983-03-07 1986-12-02 International Business Machines Corporation Instruction fetch look-aside buffer with loop mode control
US4604695A (en) 1983-09-30 1986-08-05 Honeywell Information Systems Inc. Nibble and word addressable memory arrangement
EP0148478B1 (en) 1983-12-23 1989-08-09 Hitachi, Ltd. A data processor with control of the significant bit lenghts of general purpose registers
US4777591A (en) 1984-01-03 1988-10-11 Texas Instruments Incorporated Microprocessor with integrated CPU, RAM, timer, and bus arbiter for data communications systems
US4562537A (en) 1984-04-13 1985-12-31 Texas Instruments Incorporated High speed processor
US4709329A (en) 1984-06-25 1987-11-24 Data General Corporation Input/output device controller for a data processing system
EP0185215B1 (en) 1984-11-21 1993-09-22 Harris Corporation Forth-like language microprocessor
JPS61175845A (en) 1985-01-31 1986-08-07 Toshiba Corp Microprocessor system
US4713749A (en) 1985-02-12 1987-12-15 Texas Instruments Incorporated Microprocessor with repeat instruction
US4714994A (en) 1985-04-30 1987-12-22 International Business Machines Corp. Instruction prefetch buffer control
US5045995A (en) 1985-06-24 1991-09-03 Vicom Systems, Inc. Selective operation of processing elements in a single instruction multiple data stream (SIMD) computer system
GB2177526B (en) 1985-06-24 1990-02-14 Pixar Selective operation of processing elements in a single instruction, multiple data stream (simd)computer system
US4896258A (en) 1985-07-04 1990-01-23 Hitachi, Ltd. Data processor provided with instructions which refer to both tagged and tagless data
JPH0543151B2 (en) 1985-08-21 1993-06-30 Nippon Electric Co
US4773038A (en) 1986-02-24 1988-09-20 Thinking Machines Corporation Method of simulating additional processors in a SIMD parallel processor array
US4870562A (en) 1986-03-20 1989-09-26 Nec Corporation Microcomputer capable of accessing internal memory at a desired variable access time
US4787032A (en) 1986-09-08 1988-11-22 Compaq Computer Corporation Priority arbitration circuit for processor access
US5230079A (en) 1986-09-18 1993-07-20 Digital Equipment Corporation Massively parallel array processing system with processors selectively accessing memory module locations using address in microword or in address register
US4873626A (en) 1986-12-17 1989-10-10 Massachusetts Institute Of Technology Parallel processing system with processor array having memory system included in system memory
GB2201015B (en) 1987-02-10 1990-10-10 Univ Southampton Parallel processor array and array element
US5038282A (en) 1988-05-11 1991-08-06 Massachusetts Institute Of Technology Synchronous processor with simultaneous instruction processing and data transfer
JP2595314B2 (en) 1988-06-30 1997-04-02 三菱電機株式会社 ic mosquitoes with an erroneous write preventing function - de
US5136697A (en) 1989-06-06 1992-08-04 Advanced Micro Devices, Inc. System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache
US5440749A (en) 1989-08-03 1995-08-08 Nanotronics Corporation High performance, low cost microprocessor architecture
US5157785A (en) 1990-05-29 1992-10-20 Wavetracer, Inc. Process cell for an n-dimensional processor array having a single input element with 2n data inputs, memory, and full function arithmetic logic unit
CA2045790A1 (en) 1990-06-29 1991-12-30 Richard Lee Sites Branch prediction in high-performance processor
US5361363A (en) 1990-10-03 1994-11-01 Thinking Machines Corporation Input/output system for parallel computer for performing parallel file transfers between selected number of input/output devices and another selected number of processing nodes
US5361367A (en) 1991-06-10 1994-11-01 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Highly parallel reconfigurable computer architecture for robotic computation having plural processor cells each having right and left ensembles of plural processors
WO1993008525A3 (en) 1991-10-24 1993-06-24 Intel Corp Data processing system
US5659778A (en) 1992-02-03 1997-08-19 Tm Patents, L.P. System and method of mapping an array to processing elements
US5551039A (en) 1992-02-03 1996-08-27 Thinking Machines Corporation Compiling a source code vector instruction by generating a subgrid loop for iteratively processing array elements by plural processing elements
US5452401A (en) 1992-03-31 1995-09-19 Seiko Epson Corporation Selective power-down for high performance CPU/system
JP2642039B2 (en) 1992-05-22 1997-08-20 インターナショナル・ビジネス・マシーンズ・コーポレイション Array processor
US5479624A (en) 1992-10-14 1995-12-26 Lee Research, Inc. High-performance interleaved memory system comprising a prime number of memory modules
US5542074A (en) 1992-10-22 1996-07-30 Maspar Computer Corporation Parallel processor system with highly flexible local control capability, including selective inversion of instruction signal and control of bit shift amount
JPH06162228A (en) 1992-11-26 1994-06-10 Sharp Corp Data flow processor device
GB2273377A (en) 1992-12-11 1994-06-15 Hughes Aircraft Co Multiple masks for array processors
US5696958A (en) 1993-01-11 1997-12-09 Silicon Graphics, Inc. Method and apparatus for reducing delays following the execution of a branch instruction in an instruction pipeline
CA2116985C (en) 1993-03-11 1999-09-21 Cynthia J. Burns Memory system
US5454117A (en) 1993-08-25 1995-09-26 Nexgen, Inc. Configurable branch prediction for a processor performing speculative execution
EP1338957A3 (en) 1993-11-05 2003-10-29 Intergraph Corporation Software scheduled superscalar computer architecture
JP3415693B2 (en) 1993-12-23 2003-06-09 ノキア モービル フォーンズ リミテッド Interleaving process
US5481684A (en) 1994-01-11 1996-01-02 Exponential Technology, Inc. Emulating operating system calls in an alternate instruction set using a modified code segment descriptor
US5542059A (en) 1994-01-11 1996-07-30 Exponential Technology, Inc. Dual instruction set processor having a pipeline with a pipestage functional unit that is relocatable in time and sequence order
US5781750A (en) 1994-01-11 1998-07-14 Exponential Technology, Inc. Dual-instruction-set architecture CPU with hidden software emulation mode
EP0671685B1 (en) 1994-03-08 1998-11-04 Digital Equipment Corporation Method and apparatus for detecting and executing cross-domain calls in a computer system
US5590352A (en) 1994-04-26 1996-12-31 Advanced Micro Devices, Inc. Dependency checking and forwarding of variable width operands
US5659722A (en) 1994-04-28 1997-08-19 International Business Machines Corporation Multiple condition code branching system in a multi-processor environment
EP0681236B1 (en) 1994-05-05 2000-11-22 Conexant Systems, Inc. Space vector data path
US5579520A (en) 1994-05-13 1996-11-26 Borland International, Inc. System and methods for optimizing compiled code according to code object participation in program activities
US5812811A (en) 1995-02-03 1998-09-22 International Business Machines Corporation Executing speculative parallel instructions threads with forking and inter-thread communication
US5933860A (en) 1995-02-10 1999-08-03 Digital Equipment Corporation Multiprobe instruction cache with instruction-based probe hint generation and training whereby the cache bank or way to be accessed next is predicted
JPH08249306A (en) 1995-03-09 1996-09-27 Sharp Corp Data driven type information processor
US5655122A (en) 1995-04-05 1997-08-05 Sequent Computer Systems, Inc. Optimizing compiler with static prediction of branch probability, branch frequency and function frequency
US5774685A (en) 1995-04-21 1998-06-30 International Business Machines Corporation Method and apparatus for biasing cache LRU for prefetched instructions/data based upon evaluation of speculative conditions
US5704053A (en) 1995-05-18 1997-12-30 Hewlett-Packard Company Efficient explicit data prefetching analysis and code generation in a low-level optimizer for inserting prefetch instructions into loops of applications
US5774686A (en) 1995-06-07 1998-06-30 Intel Corporation Method and apparatus for providing two system architectures in a processor
JP3520611B2 (en) 1995-07-06 2004-04-19 株式会社日立製作所 Method of controlling the processor
US6006328A (en) 1995-07-14 1999-12-21 Christopher N. Drake Computer software authentication, protection, and security system
US5652894A (en) 1995-09-29 1997-07-29 Intel Corporation Method and apparatus for providing power saving modes to a pipelined processor
US5638533A (en) 1995-10-12 1997-06-10 Lsi Logic Corporation Method and apparatus for providing data to a parallel processing array
US6292879B1 (en) 1995-10-25 2001-09-18 Anthony S. Fong Method and apparatus to specify access control list and cache enabling and cache coherency requirement enabling on individual operands of an instruction of a computer
US5930490A (en) 1996-01-02 1999-07-27 Advanced Micro Devices, Inc. Microprocessor configured to switch instruction sets upon detection of a plurality of consecutive instructions
US5822606A (en) 1996-01-11 1998-10-13 Morton; Steven G. DSP having a plurality of like processors controlled in parallel by an instruction word, and a control processor also controlled by the instruction word
US5930509A (en) 1996-01-29 1999-07-27 Digital Equipment Corporation Method and apparatus for performing binary translation
US5664950A (en) 1996-02-13 1997-09-09 Lawrence; Richard J. Hardware mechanism for computer software security
US5835968A (en) 1996-04-17 1998-11-10 Advanced Micro Devices, Inc. Apparatus for providing memory and register operands concurrently to functional units
US5949995A (en) 1996-08-02 1999-09-07 Freeman; Jackie Andrew Programmable branch prediction system and method for inserting prediction operation which is independent of execution of program code
US5854934A (en) 1996-08-23 1998-12-29 Hewlett-Packard Company Optimizing compiler having data cache prefetch spreading
US6089460A (en) 1996-09-13 2000-07-18 Nippon Steel Corporation Semiconductor device with security protection function, ciphering and deciphering method thereof, and storage medium for storing software therefor
US5805907A (en) 1996-10-04 1998-09-08 International Business Machines Corporation System and method for reducing power consumption in an electronic circuit
US5966544A (en) 1996-11-13 1999-10-12 Intel Corporation Data speculatable processor having reply architecture
US5924117A (en) 1996-12-16 1999-07-13 International Business Machines Corporation Multi-ported and interleaved cache memory supporting multiple simultaneous accesses thereto
US5946222A (en) 1996-12-20 1999-08-31 Oak Technology, Inc. Method and apparatus for performing a masked byte addition operation
US6108775A (en) 1996-12-30 2000-08-22 Texas Instruments Incorporated Dynamically loadable pattern history tables in a multi-task microprocessor
JPH10254839A (en) 1997-03-11 1998-09-25 Sony Corp Simd controlling parallel processor and arithmetic method
US6286135B1 (en) 1997-03-26 2001-09-04 Hewlett-Packard Company Cost-sensitive SSA-based strength reduction algorithm for a machine with predication support and segmented addresses
DE69804708T2 (en) 1997-03-29 2002-11-14 Imec Vzw Method and apparatus for size optimization of memory units
JPH10289305A (en) 1997-04-11 1998-10-27 Mitsubishi Electric Corp Image processing device and its method
US5996061A (en) 1997-06-25 1999-11-30 Sun Microsystems, Inc. Method for invalidating data identified by software compiler
WO1999014685A1 (en) 1997-09-16 1999-03-25 Hitachi, Ltd. Data processor and data processing system
US5933650A (en) 1997-10-09 1999-08-03 Mips Technologies, Inc. Alignment and ordering of vector elements for single instruction multiple data processing
US6289505B1 (en) 1997-11-18 2001-09-11 Sun Microsystems, Inc. Method, apparatus and computer programmed product for binary re-optimization using a high level language compiler
US6119205A (en) 1997-12-22 2000-09-12 Sun Microsystems, Inc. Speculative cache line write backs to avoid hotspots
US6412105B1 (en) 1997-12-31 2002-06-25 Elbrus International Limited Computer method and apparatus for compilation of multi-way decisions
US6272676B1 (en) 1998-01-13 2001-08-07 Intel Corporation Method and apparatus for finding loop— lever parallelism in a pointer based application
US6374349B2 (en) 1998-03-19 2002-04-16 Mcfarling Scott Branch predictor with serially connected predictor stages for improving branch prediction accuracy
JPH11272546A (en) 1998-03-23 1999-10-08 Nec Corp Variable length register device
US6121905A (en) 1998-05-11 2000-09-19 Oak Technology, Inc. Method and apparatus for decoding JPEG symbols
US6130631A (en) 1998-05-11 2000-10-10 Oak Technology, Inc. Method and apparatus utilizing a simplified content-addressable memory for JPEG decoding
EP2280502B1 (en) 1998-06-03 2018-05-02 Cryptography Research, Inc. Using unpredictable information to Resist Discovery of Secrets by External Monitoring
US6105139A (en) 1998-06-03 2000-08-15 Nec Usa, Inc. Controller-based power management for low-power sequential circuits
US6334175B1 (en) 1998-07-22 2001-12-25 Ati Technologies, Inc. Switchable memory system and memory allocation method
US6301705B1 (en) 1998-10-01 2001-10-09 Institute For The Development Of Emerging Architectures, L.L.C. System and method for deferring exceptions generated during speculative execution
EP0992916A1 (en) 1998-10-06 2000-04-12 Texas Instruments France Digital signal processor
US6272512B1 (en) 1998-10-12 2001-08-07 Intel Corporation Data manipulation instruction for enhancing value and efficiency of complex arithmetic
GB9825102D0 (en) 1998-11-16 1999-01-13 Insignia Solutions Plc Computer system
JP3297389B2 (en) 1998-12-07 2002-07-02 インターナショナル・ビジネス・マシーンズ・コーポレーション Power control method and electrical equipment
US6430674B1 (en) 1998-12-30 2002-08-06 Intel Corporation Processor executing plural instruction sets (ISA's) with ability to have plural ISA's in different pipeline stages at same time
US6487640B1 (en) 1999-01-19 2002-11-26 International Business Machines Corporation Memory access request reordering to reduce memory access latency
US6282628B1 (en) 1999-02-24 2001-08-28 International Business Machines Corporation Method and system for a result code for a single-instruction multiple-data predicate compare operation
US7024393B1 (en) 1999-03-27 2006-04-04 Microsoft Corporation Structural of digital rights management (DRM) system
US6477646B1 (en) 1999-07-08 2002-11-05 Broadcom Corporation Security chip architecture and implementations for cryptography acceleration
US7430670B1 (en) * 1999-07-29 2008-09-30 Intertrust Technologies Corp. Software self-defense systems and methods
US6446197B1 (en) 1999-10-01 2002-09-03 Hitachi, Ltd. Two modes for executing branch instructions of different lengths and use of branch control instruction and register set loaded with target instructions
US6502188B1 (en) 1999-11-16 2002-12-31 Advanced Micro Devices, Inc. Dynamic classification of conditional branches in global history branch prediction
EP1107123B1 (en) 1999-12-06 2007-11-21 Texas Instruments France Smart cache
US6625740B1 (en) 2000-01-13 2003-09-23 Cirrus Logic, Inc. Dynamically activating and deactivating selected circuit blocks of a data processing integrated circuit during execution of instructions according to power code bits appended to selected instructions
US7124286B2 (en) 2000-01-14 2006-10-17 Advanced Micro Devices, Inc. Establishing an operating mode in a processor
US6452864B1 (en) 2000-01-31 2002-09-17 Stmicroelectonics S.R.L. Interleaved memory device for sequential access synchronous reading with simplified address counters
US6282623B1 (en) 2000-02-04 2001-08-28 Motorola Inc. Method for digital signal processing, DSP, mobile communication and audi o-device
EP1130517B1 (en) 2000-03-02 2004-05-26 STMicroelectronics S.r.l. Redundancy architecture for an interleaved memory
US6446181B1 (en) 2000-03-31 2002-09-03 Intel Corporation System having a configurable cache/SRAM memory
JP2002007359A (en) 2000-06-21 2002-01-11 Sony Corp Method and device for parallel processing simd control
US6931518B1 (en) 2000-11-28 2005-08-16 Chipwrights Design, Inc. Branching around conditional processing if states of all single instruction multiple datapaths are disabled and the computer program is non-deterministic
US20020073301A1 (en) 2000-12-07 2002-06-13 International Business Machines Corporation Hardware for use with compiler generated branch information
CA2327911A1 (en) * 2000-12-08 2002-06-08 Cloakware Corporation Obscuring functions in computer software
US6813693B2 (en) 2000-12-11 2004-11-02 Microsoft Corporation System and method for the discovery and use of repetitively accessed data
JP3681647B2 (en) 2001-02-21 2005-08-10 株式会社半導体理工学研究センター Cache memory system unit
US6643739B2 (en) 2001-03-13 2003-11-04 Koninklijke Philips Electronics N.V. Cache way prediction based on instruction base register
US20040205740A1 (en) 2001-03-29 2004-10-14 Lavery Daniel M. Method for collection of memory reference information and memory disambiguation
US6795781B2 (en) 2002-06-27 2004-09-21 Intel Corporation Method and apparatus for compiler assisted power management
US7467377B2 (en) 2002-10-22 2008-12-16 Intel Corporation Methods and apparatus for compiler managed first cache bypassing
US7500126B2 (en) 2002-12-04 2009-03-03 Nxp B.V. Arrangement and method for controlling power modes of hardware resources
US20040154010A1 (en) 2003-01-31 2004-08-05 Pedro Marcuello Control-quasi-independent-points guided speculative multithreading
US7299500B1 (en) 2003-07-17 2007-11-20 Copyright Clearance Center, Inc. Method and apparatus for secure delivery and rights management of digital content at an unsecure site
US7089594B2 (en) 2003-07-21 2006-08-08 July Systems, Inc. Application rights management in a mobile environment
US7293164B2 (en) 2004-01-14 2007-11-06 International Business Machines Corporation Autonomic method and apparatus for counting branch instructions to generate branch statistics meant to improve branch predictions
US8607209B2 (en) 2004-02-04 2013-12-10 Bluerisc Inc. Energy-focused compiler-assisted branch prediction
KR101254209B1 (en) 2004-03-22 2013-04-23 삼성전자주식회사 Apparatus and method for moving and copying right objects between device and portable storage device
US7664109B2 (en) 2004-09-03 2010-02-16 Microsoft Corporation System and method for distributed streaming of scalable media
EP1842203A4 (en) 2004-11-12 2011-03-23 Verayo Inc Volatile device keys and applications thereof
US7600265B2 (en) 2005-03-09 2009-10-06 Nokia Corporation System and method for applying an OMA DRM permission model to JAVA MIDP applications
US7613921B2 (en) 2005-05-13 2009-11-03 Intel Corporation Method and apparatus for remotely provisioning software-based security coprocessors
US20070294181A1 (en) 2006-05-22 2007-12-20 Saurabh Chheda Flexible digital rights management with secure snippets
US20080126766A1 (en) 2006-11-03 2008-05-29 Saurabh Chheda Securing microprocessors against information leakage and physical tampering

Patent Citations (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4003033A (en) * 1975-12-22 1977-01-11 Honeywell Information Systems, Inc. Architecture for a microprogrammed device controller
US4067059A (en) * 1976-01-29 1978-01-03 Sperry Rand Corporation Shared direct memory access controller
US4079455A (en) * 1976-12-13 1978-03-14 Rca Corporation Microprocessor architecture
US4138720A (en) * 1977-04-04 1979-02-06 Burroughs Corporation Time-shared, multi-phase memory accessing system
US4181942A (en) * 1978-03-31 1980-01-01 International Business Machines Corporation Program branching method and apparatus
US4382279A (en) * 1978-04-25 1983-05-03 Compagnie Internationale Pour L'informatique Cii-Honeywell Bull (Societe Anonyme) Single chip microprocessor with on-chip modifiable memory
US4255785A (en) * 1978-09-25 1981-03-10 Motorola, Inc. Microprocessor having instruction fetch and execution overlap
US4376977A (en) * 1979-08-27 1983-03-15 U.S. Philips Corporation Computer system with scannable program memory
US4435758A (en) * 1980-03-10 1984-03-06 International Business Machines Corporation Method for conditional branch execution in SIMD vector processors
US4434461A (en) * 1980-09-15 1984-02-28 Motorola, Inc. Microprocessor with duplicate registers for processing interrupts
US4450519A (en) * 1980-11-24 1984-05-22 Texas Instruments Incorporated Psuedo-microprogramming in microprocessor in single-chip microprocessor with alternate IR loading from internal or external program memories
US4592013A (en) * 1981-08-21 1986-05-27 International Business Machines Corp. Method and device for addressing a memory
US4577282A (en) * 1982-02-22 1986-03-18 Texas Instruments Incorporated Microcomputer system for digital signal processing
US4649471A (en) * 1983-03-01 1987-03-10 Thomson Components-Mostek Corporation Address-controlled automatic bus arbitration and address modification
US4720812A (en) * 1984-05-30 1988-01-19 Racal-Milgo, Inc. High speed program store with bootstrap
US4665495A (en) * 1984-07-23 1987-05-12 Texas Instruments Incorporated Single chip dram controller and CRT controller
US4803621A (en) * 1986-07-24 1989-02-07 Sun Microsystems, Inc. Memory access system
US5276895A (en) * 1986-09-18 1994-01-04 Digital Equipment Corporation Massively parallel array processing system
US4992933A (en) * 1986-10-27 1991-02-12 International Business Machines Corporation SIMD array processor with global instruction control and reprogrammable instruction decoders
US5021993A (en) * 1987-03-31 1991-06-04 Kabushiki Kaisha Toshiba Device for saving and restoring register information
US5111389A (en) * 1987-10-29 1992-05-05 International Business Machines Corporation Aperiodic mapping system using power-of-two stride access to interleaved devices
US5121498A (en) * 1988-05-11 1992-06-09 Massachusetts Institute Of Technology Translator for translating source code for selective unrolling of loops in the source code
US5127091A (en) * 1989-01-13 1992-06-30 International Business Machines Corporation System for reducing delay in instruction execution by executing branch instructions in separate processor while dispatching subsequent instructions to primary processor
US4931986A (en) * 1989-03-03 1990-06-05 Ncr Corporation Computer system clock generator for generating tuned multiple clock signals
US5224214A (en) * 1990-04-12 1993-06-29 Digital Equipment Corp. BuIffet for gathering write requests and resolving read conflicts by matching read and write requests
US5193202A (en) * 1990-05-29 1993-03-09 Wavetracer, Inc. Processor array with relocated operand physical address generator capable of data transfer to distant physical processor for each virtual processor while simulating dimensionally larger array processor
US5637932A (en) * 1990-11-27 1997-06-10 Hitachi, Ltd. Power consumption control system
US5497478A (en) * 1991-03-20 1996-03-05 Hewlett-Packard Company Memory access system and method modifying a memory interleaving scheme so that data can be read in any sequence without inserting wait cycles
US5875464A (en) * 1991-12-10 1999-02-23 International Business Machines Corporation Computer system with private and shared partitions in cache
US5630143A (en) * 1992-03-27 1997-05-13 Cyrix Corporation Microprocessor with externally controllable power management
US5872987A (en) * 1992-08-07 1999-02-16 Thinking Machines Corporation Massively parallel computer including auxiliary vector processor
US5410669A (en) * 1993-04-05 1995-04-25 Motorola, Inc. Data processor having a cache memory capable of being used as a linear ram bank
US5604913A (en) * 1993-08-10 1997-02-18 Fujitsu Limited Vector processor having a mask register used for performing nested conditional instructions
US5884057A (en) * 1994-01-11 1999-03-16 Exponential Technology, Inc. Temporal re-alignment of a floating point pipeline to an integer pipeline for emulation of a load-operate architecture on a load/store processor
US5524223A (en) * 1994-01-31 1996-06-04 Motorola, Inc. Instruction accelerator for processing loop instructions with address generator using multiple stored increment values
US5481693A (en) * 1994-07-20 1996-01-02 Exponential Technology, Inc. Shared register architecture for a dual-instruction-set CPU
US5752068A (en) * 1994-08-23 1998-05-12 Massachusetts Institute Of Technology Mesh parallel computer architecture apparatus and associated methods
US5598546A (en) * 1994-08-31 1997-01-28 Exponential Technology, Inc. Dual-architecture super-scalar pipeline
US5608886A (en) * 1994-08-31 1997-03-04 Exponential Technology, Inc. Block-based branch prediction using a target finder array storing target sub-addresses
US5758176A (en) * 1994-09-28 1998-05-26 International Business Machines Corporation Method and system for providing a single-instruction, multiple-data execution unit for performing single-instruction, multiple-data operations within a superscalar data processing system
US5758112A (en) * 1994-10-14 1998-05-26 Silicon Graphics, Inc. Pipeline processor with enhanced method and apparatus for restoring register-renaming information in the event of a branch misprediction
US5638525A (en) * 1995-02-10 1997-06-10 Intel Corporation Processor capable of executing programs that contain RISC and CISC instructions
US6058469A (en) * 1995-04-17 2000-05-02 Ricoh Corporation System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization
US5737572A (en) * 1995-06-06 1998-04-07 Apple Computer, Inc. Bank selection logic for memory controllers
US5875324A (en) * 1995-06-07 1999-02-23 Advanced Micro Devices, Inc. Superscalar microprocessor which delays update of branch prediction information in response to branch misprediction until a subsequent idle clock
US5864707A (en) * 1995-12-11 1999-01-26 Advanced Micro Devices, Inc. Superscalar microprocessor configured to predict return addresses from a return stack storage
US6067622A (en) * 1996-01-02 2000-05-23 Moore; Steven Jerome Software security system using remove function to restrict unauthorized duplicating and installation of an application program
US5727229A (en) * 1996-02-05 1998-03-10 Motorola, Inc. Method and apparatus for moving data in a parallel processor
US5721893A (en) * 1996-05-14 1998-02-24 Hewlett-Packard Company Exploiting untagged branch prediction cache by relocating branches
US5737749A (en) * 1996-05-20 1998-04-07 International Business Machines Corporation Method and system for dynamically sharing cache capacity in a microprocessor
US5864697A (en) * 1996-06-28 1999-01-26 Texas Instruments Incorporated Microprocessor using combined actual and speculative branch history prediction
US5742804A (en) * 1996-07-24 1998-04-21 Institute For The Development Of Emerging Architectures, L.L.C. Instruction prefetch mechanism utilizing a branch predict instruction
US5903750A (en) * 1996-11-20 1999-05-11 Institute For The Development Of Emerging Architectures, L.L.P. Dynamic branch prediction for branch instructions with multiple targets
US5857104A (en) * 1996-11-26 1999-01-05 Hewlett-Packard Company Synthetic dynamic branch prediction
US6212542B1 (en) * 1996-12-16 2001-04-03 International Business Machines Corporation Method and system for executing a program within a multiscalar processor by processing linked thread descriptors
US5887166A (en) * 1996-12-16 1999-03-23 International Business Machines Corporation Method and system for constructing a program including a navigation instruction
US5870581A (en) * 1996-12-20 1999-02-09 Oak Technology, Inc. Method and apparatus for performing concurrent write operations to a single-write-input register file and an accumulator register
US6381668B1 (en) * 1997-03-21 2002-04-30 International Business Machines Corporation Address mapping for system memory
US6393520B2 (en) * 1997-04-17 2002-05-21 Matsushita Electric Industrial Co., Ltd. Data processor and data processing system with internal memories
US6385720B1 (en) * 1997-07-14 2002-05-07 Matsushita Electric Industrial Co., Ltd. Branch prediction method and processor using origin information, relative position information and history information
US6049330A (en) * 1997-08-28 2000-04-11 Oak Technology, Inc. Method and apparatus for optimizing storage of compressed images in memory
US6211864B1 (en) * 1997-08-28 2001-04-03 Oak Technology, Inc. Method and apparatus for optimizing storage of compressed images in memory
US6044469A (en) * 1997-08-29 2000-03-28 Preview Software Software publisher or distributor configurable software security mechanism
US6021484A (en) * 1997-11-14 2000-02-01 Samsung Electronics Co., Ltd. Dual instruction set architecture
US6178498B1 (en) * 1997-12-18 2001-01-23 Idea Corporation Storing predicted branch target address in different storage according to importance hint in branch prediction instruction
US6219796B1 (en) * 1997-12-23 2001-04-17 Texas Instruments Incorporated Power reduction for processors by software control of functional units
US6216223B1 (en) * 1998-01-12 2001-04-10 Billions Of Operations Per Second, Inc. Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor
US6067609A (en) * 1998-04-09 2000-05-23 Teranex, Inc. Pattern generation and shift plane operations for a mesh connected computer
US6529943B1 (en) * 1998-04-24 2003-03-04 Canon Kabushiki Kaisha Server, client, client server system, method for controlling them and storage medium therefor
US6052703A (en) * 1998-05-12 2000-04-18 Oak Technology, Inc. Method and apparatus for determining discrete cosine transforms using matrix multiplication and modified booth encoding
US6175892B1 (en) * 1998-06-19 2001-01-16 Hitachi America. Ltd. Registers and methods for accessing registers for use in a single instruction multiple data system
US6988183B1 (en) * 1998-06-26 2006-01-17 Derek Chi-Lan Wong Methods for increasing instruction-level parallelism in microprocessors and digital system
US20050066153A1 (en) * 1998-10-12 2005-03-24 Harshvardhan Sharangpani Method for processing branch operations
US20030041230A1 (en) * 1998-12-30 2003-02-27 Lihu Rappoport Method and system for branch target prediction using path information
US6341371B1 (en) * 1999-02-23 2002-01-22 International Business Machines Corporation System and method for optimizing program execution in a computer system
US6571331B2 (en) * 1999-03-18 2003-05-27 Ip-First, Llc Static branch prediction mechanism for conditional branch instructions
US6550004B1 (en) * 1999-11-05 2003-04-15 Ip-First, Llc Hybrid branch predictor with improved selector table update mechanism
US6539543B1 (en) * 1999-11-29 2003-03-25 Adelante Technologies, Nv Method and apparatus for compiling source code by flattening hierarchies
US6560776B1 (en) * 2000-02-18 2003-05-06 Avaya Technology Corp. Software installation verification tool
US20010037450A1 (en) * 2000-03-02 2001-11-01 Metlitski Evgueny A. System and method for process protection
US6675305B1 (en) * 2000-08-04 2004-01-06 Synopsys, Inc. Power saving in a USB peripheral by providing gated clock signal to CSR block in response to a local interrupt generated when an operation is to be performed
US6732253B1 (en) * 2000-11-13 2004-05-04 Chipwrights Design, Inc. Loop handling for single instruction multiple datapath processor architectures
US6687838B2 (en) * 2000-12-07 2004-02-03 Intel Corporation Low-power processor hint, such as from a PAUSE instruction
US20040015923A1 (en) * 2001-02-16 2004-01-22 Craig Hemsing Apparatus and method to reduce memory footprints in processor architectures
US20030014742A1 (en) * 2001-07-09 2003-01-16 Sasken Communication Technologies Limited Technique for compiling computer code to reduce energy consumption while executing the code
US20030066061A1 (en) * 2001-09-29 2003-04-03 Youfeng Wu Method and apparatus for performing compiler transformation of software code using fastforward regions and value specialization
US7036118B1 (en) * 2001-12-20 2006-04-25 Mindspeed Technologies, Inc. System for executing computer programs on a limited-memory computing machine
US20040010782A1 (en) * 2002-07-09 2004-01-15 Moritz Csaba Andras Statically speculative compilation and execution
US20040010679A1 (en) * 2002-07-09 2004-01-15 Moritz Csaba Andras Reducing processor energy consumption by controlling processor resources
US7493607B2 (en) * 2002-07-09 2009-02-17 Bluerisc Inc. Statically speculative compilation and execution
US20040010783A1 (en) * 2002-07-09 2004-01-15 Moritz Csaba Andras Reducing processor energy consumption using compile-time information
US7162617B2 (en) * 2003-02-14 2007-01-09 Fine Arc Incorporated Data processor with changeable architecture
US7185215B2 (en) * 2003-02-24 2007-02-27 International Business Machines Corporation Machine code builder derived power consumption reduction
US20050055678A1 (en) * 2003-08-28 2005-03-10 Ryuji Sakai Method and apparatus for managing software in computer system using virtual machine
US20070104077A1 (en) * 2003-10-02 2007-05-10 Mediatek Inc. Apparatus for detecting a pre-pit signal
US20050114850A1 (en) * 2003-10-29 2005-05-26 Saurabh Chheda Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control
US20050108507A1 (en) * 2003-11-17 2005-05-19 Saurabh Chheda Security of program executables and microprocessors based on compiler-arcitecture interaction
US7676661B1 (en) * 2004-10-05 2010-03-09 Xilinx, Inc. Method and system for function acceleration using custom instructions
US7487340B2 (en) * 2006-06-08 2009-02-03 International Business Machines Corporation Local and global branch prediction information storage

Cited By (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10101978B2 (en) 2002-07-09 2018-10-16 Iii Holdings 2, Llc Statically speculative compilation and execution
US20090300590A1 (en) * 2002-07-09 2009-12-03 Bluerisc Inc., A Massachusetts Corporation Statically speculative compilation and execution
US9235393B2 (en) 2002-07-09 2016-01-12 Iii Holdings 2, Llc Statically speculative compilation and execution
US20040010782A1 (en) * 2002-07-09 2004-01-15 Moritz Csaba Andras Statically speculative compilation and execution
US7493607B2 (en) 2002-07-09 2009-02-17 Bluerisc Inc. Statically speculative compilation and execution
US20050114850A1 (en) * 2003-10-29 2005-05-26 Saurabh Chheda Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control
US9569186B2 (en) 2003-10-29 2017-02-14 Iii Holdings 2, Llc Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control
US20050108507A1 (en) * 2003-11-17 2005-05-19 Saurabh Chheda Security of program executables and microprocessors based on compiler-arcitecture interaction
US9582650B2 (en) 2003-11-17 2017-02-28 Bluerisc, Inc. Security of program executables and microprocessors based on compiler-architecture interaction
US7996671B2 (en) 2003-11-17 2011-08-09 Bluerisc Inc. Security of program executables and microprocessors based on compiler-architecture interaction
US8607209B2 (en) 2004-02-04 2013-12-10 Bluerisc Inc. Energy-focused compiler-assisted branch prediction
US9697000B2 (en) 2004-02-04 2017-07-04 Iii Holdings 2, Llc Energy-focused compiler-assisted branch prediction
US9244689B2 (en) 2004-02-04 2016-01-26 Iii Holdings 2, Llc Energy-focused compiler-assisted branch prediction
US20050172277A1 (en) * 2004-02-04 2005-08-04 Saurabh Chheda Energy-focused compiler-assisted branch prediction
US20070147156A1 (en) * 2005-12-22 2007-06-28 Sony Computer Entertainment Inc. Methods and apparatus for random number generation
US7676531B2 (en) * 2005-12-22 2010-03-09 Sony Computer Entertainment Inc. Methods and apparatus for random number generation
US20070294181A1 (en) * 2006-05-22 2007-12-20 Saurabh Chheda Flexible digital rights management with secure snippets
US9940445B2 (en) 2006-11-03 2018-04-10 Bluerisc, Inc. Securing microprocessors against information leakage and physical tampering
US9069938B2 (en) 2006-11-03 2015-06-30 Bluerisc, Inc. Securing microprocessors against information leakage and physical tampering
US8972744B1 (en) 2008-02-14 2015-03-03 Xilinx, Inc. Preventing data imprinting in memory
US8359447B1 (en) 2009-01-15 2013-01-22 Xilinx, Inc. System and method of detecting and reversing data imprinting in memory
US7949912B1 (en) * 2009-01-15 2011-05-24 Xilinx, Inc. System and method of securing data stored in a memory
US20130007881A1 (en) * 2010-03-25 2013-01-03 Irdeto Canada Corporation System and Method for Dynamic, Variably-Timed Operation Paths as a Resistance to Side Channel and Repeated Invocation Attacks
US20120066162A1 (en) * 2010-09-09 2012-03-15 Texas Instruments Incorporated System and Method for Training an Adaptive Filter in an Alternate Domain with Constraints
US20120201380A1 (en) * 2011-02-08 2012-08-09 Fujitsu Limited Communication apparatus and secure module
US9152773B2 (en) * 2011-02-08 2015-10-06 Fujitsu Limited Communication apparatus and secure module including function for disabling encrypted communication
US9514302B2 (en) * 2011-03-28 2016-12-06 Sony Corporation Information processing apparatus and method, and program
US20150007323A1 (en) * 2011-03-28 2015-01-01 Sony Corporation Information processing apparatus and method, and program
US9389855B2 (en) * 2011-08-26 2016-07-12 Kabushiki Kaisha Toshiba Arithmetic device
US8953783B2 (en) * 2011-08-26 2015-02-10 Kabushiki Kaisha Toshiba Arithmetic device
US20130202105A1 (en) * 2011-08-26 2013-08-08 Kabushiki Kaisha Toshiba Arithmetic device
US20150121042A1 (en) * 2011-08-26 2015-04-30 Kabushiki Kaisha Toshiba Arithmetic device
US9740498B2 (en) 2011-11-15 2017-08-22 Wuxi Dsp Technologies Inc. Opportunistic multi-thread method and processor
US20140192975A1 (en) * 2012-10-17 2014-07-10 Elliptic Technologies Inc. System and method for multichannel cryptographic processing
US10103876B2 (en) * 2012-10-17 2018-10-16 Synopsys, Inc. System and method for multichannel cryptographic processing
US20150039864A1 (en) * 2013-07-31 2015-02-05 Ebay Inc. Systems and methods for defeating malware with randomized opcode values
US9916281B2 (en) * 2013-10-17 2018-03-13 Stmicroelectronics Sa Processing system with a secure set of executable instructions and/or addressing scheme
US20170255591A1 (en) * 2013-10-17 2017-09-07 Stmicroelectronics Sa Processing System with a Secure Set of Executable Instructions and/or Addressing Scheme
WO2015119886A1 (en) * 2014-02-06 2015-08-13 Optimum Semiconductor Technologies, Inc. Method and apparatus for enabling a processor to generate pipeline control signals
US9558000B2 (en) 2014-02-06 2017-01-31 Optimum Semiconductor Technologies, Inc. Multithreading using an ordered list of hardware contexts
US9766894B2 (en) 2014-02-06 2017-09-19 Optimum Semiconductor Technologies, Inc. Method and apparatus for enabling a processor to generate pipeline control signals
CN106415589A (en) * 2014-03-31 2017-02-15 爱迪德技术有限公司 Secured electronics device
US9754112B1 (en) 2014-11-24 2017-09-05 Bluerisc, Inc. Detection and healing of vulnerabilities in computer code
US9411964B1 (en) 2014-11-24 2016-08-09 Bluerisc, Inc. Characterizing, detecting and healing vulnerabilities in computer code
US10127160B2 (en) * 2016-09-20 2018-11-13 Alexander Gounares Methods and systems for binary scrambling

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