JP2002007359A - Method and device for parallel processing simd control - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the memory capacity and processing speed by effectively utilizing a processor element(PE), which is not practically contributing to processing. SOLUTION: In SIMD control for controlling one-dimensionally located plural PE corresponding to the same command, ID codes, which are repeatedly assigned in the same array for every plural groups 2 composed of PE0, PE1 and PE2, for example, capable of specifying the arbitrary PE within each of groups 2 are applied for every PE. Then, data are inputted to the PE 0-2, the same processing is executed, the result in the middle of processing in the specified PE1 inside the group 2 is stored in the other PE0 and PE2 designated with a specified identification code (ID=1) as a reference, and the stored middle result is read out with (ID=1) as a reference and used for following processing. The result of processing is selected and outputted with (ID=1) as a reference.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a number of PE (Pro
The present invention relates to a parallel processing device of a SIMD (Single Instruction Multiple Data) control method for executing multi-parallel processing with a single instruction for a processor element and a control method thereof.

[0002]

2. Description of the Related Art In a SIMD-controlled multi-parallel processor,
A plurality of element processors PE are arranged one-dimensionally, and the plurality of element processors (PE) are controlled by a single instruction. Conventionally, in this SIMD-controlled multi-parallel processor, the same data has not been assigned, and the data has always been one-to-one or one-to-many for each element processor. It also has a function of performing inter-element processor communication, but this function is provided for use only when the result of another element processor is used for one process.

[0003]

In a conventional SIMD-controlled multi-parallel processor, a shortage of a local memory (LM) and a shortage of processing steps are often problems. Further, while the number of element processors is fixed due to the structure of the SIMD control processor, the length of the data stream does not always match the number of element processors. There may be many missing element processors, and these element processors have been wasted. In addition, there are many processes in which predetermined different processes are periodically performed in a data stream. In the SIMD control, when one of the element processors is in a valid process every predetermined number of times, the other element processors perform the same process, but in the periodic processing, the processing results of the other element processors are not output. For this reason, the processing of the other element processors does not contribute to the effective processing at all, and this point is wasteful.

[0004] An object of the present invention is to perform a process of effectively increasing the local memory multiple times for such a data stream in which the element processor is wasted, while effectively utilizing the element processor. The point is to realize the configuration as it is. Further, another object of the present invention is to enable an element processor which has not conventionally contributed to the calculation of output data, in the case of processing such as filtering processing in which exactly the same processing is repeated with only different parameters. An object of the present invention is to realize highly efficient processing using the number of parallel processes substantially multiple times by using the hardware configuration as it is.

[0005]

According to a first aspect of the present invention, there is provided an SIMD control parallel processing method for controlling a plurality of one-dimensionally arranged element processors by a single instruction.
An MD control parallel processing method, wherein an identification code that is repeatedly assigned in the same arrangement for each group of a predetermined number of element processors and that can specify an arbitrary element processor in each group is assigned to each element processor. ,
Data is input to the plurality of element processors, and the same processing is executed.In a specific element processor in the group, an intermediate result of the processing is transmitted to another element processor specified based on a specific identification code. The stored intermediate result is read out according to the specification based on the specific identification code and used for the subsequent processing. Preferably,
The result of the above processing is selected and output according to a specification based on a specific identification code.

A SIMD control parallel processing method according to a second aspect of the present invention is a SIMD control parallel processing method for controlling a plurality of one-dimensionally arranged element processors by a single instruction. An identification code that is repeatedly assigned in the same arrangement for each group of element processors and that can identify an arbitrary element processor within each group is assigned to each element processor, and data and parameters are input to the plurality of element processors. Then, the same processing is executed, some of the processing results of the element processors are integrated with reference to the identification code, and the result of the integration processing is selected by specification with the identification code as the reference. Output.

A SIMD control parallel processing device according to a third aspect of the present invention includes a memory unit for storing information and a processing unit for executing processing based on the information stored in the memory unit. And a SIMD control circuit for performing SIMD control of the plurality of element processors by a single instruction. The SIMD control includes a predetermined number of elements. It is repeatedly assigned in the same arrangement for each group of processors, and, in each group, assigns an identification code capable of specifying an arbitrary element processor to each element processor, and inputs data to the plurality of element processors, Execute the same process and specify the intermediate result of the above process on the specific element processor in the above group based on the specific identification code It has been stored in the other element processor,
The stored intermediate result is read out based on the specification based on the specific identification code and used for subsequent processing. Preferably, the SIMD control further includes a control for selecting and outputting the result of the processing based on the specification based on the specific identification code.

A SIMD control parallel processing apparatus according to a fourth aspect of the present invention includes a memory unit for storing information and a processing unit for executing processing based on the information stored in the memory unit. And a SIMD control circuit for performing SIMD control of the plurality of element processors by a single instruction. The SIMD control includes a predetermined number of elements. An identification code that is repeatedly assigned in the same arrangement for each group of processors and that can identify an arbitrary element processor in each group is assigned to each element processor, and data and parameters are input to the plurality of element processors. Then, the same processing is executed, and some of the processing results of the element processors are integrated based on the identification code as a reference. The result of the process, including control to select and output the specified relative to the identification code.

In the SIMD control parallel processing method and apparatus according to the present invention, a group of element processors is divided into a group consisting of a predetermined number of element processors by repeatedly arranging recognition codes, and a plurality of element processors in this group are divided. Are operated as one virtual element processor.

Specifically, in the SIMD control parallel processing method and apparatus according to the first and third aspects, the memory units of a plurality of element processors are virtually allocated to one data and used. In writing to and reading from the memory unit, the memory unit is specified based on the recognition code. With the memory designation based on the recognition code, writing and reading to and from the memory unit can be performed normally only by the reference element processor. In other element processors, the write destination is not specified, or data is read from another location, so that the processing result is incorrect. Then, normal output data can be obtained only from the reference element processor. In such a control, when the number of element processors in an element processor block is n, the number of data that can be processed at a time by the entire parallel processing apparatus is 1 / n, but the memory capacity that can be used for one data Can be substantially increased by a factor of n. Such a virtual memory expansion method requires output data only intermittently, but is suitable when a large amount of memory space is required for processing. Further, since it can be performed by program control of the SIMD control circuit, there is no need to change the hardware configuration of the conventional SIMD control parallel processing device at all.

In the SIMD control parallel processing method and apparatus according to the second and fourth aspects, the same data is input to all the element processors in the same group and different parameters are input, so that On the other hand, processing with different parameters is executed completely in parallel. When integrating the processing results based on the recognition code of each element processor, normal integration processing can be performed only for the reference element processor. Finally, the output of each element processor is selectively controlled by the recognition code. Thereby, one correct processing result is obtained as output data in each group. In this processing, if each group is regarded as one virtual element processor, the virtual element processor has a higher processing capability than the individual element processors. In effect, the number of element processors that can obtain an effective output by this processing method is reduced. However, in the field of image processing and the like, pixels that are desired to be processed in parallel at one time are often intermittent. Therefore, this method can reduce the processing power of element processors that have conventionally only contributed to processing once every several times. This means that it was used effectively. Moreover, in the present embodiment, a highly efficient SIMD control processor with an increased number of parallel processes is:
There is no need to change the hardware configuration at all.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to, for example, one horizontal scan line of an image as a unit of one data stream, one-to-one correspondence of pixel data in the horizontal direction to each element processor PE, and the next scan. SIMD-controlled multi-parallel image DS that performs processing during one horizontal scanning period up to the line
SIMD effective for P (Digital Signal Processor)
Provide a control method. Embodiments of the present invention will be described based on specific cases using drawings and flowcharts.

First Embodiment In the first embodiment, in a multi-parallel SIMD control processor, one data is allocated to a plurality of element processors, and an intermediate result of the data processing is distributed to the plurality of element processors. A method is proposed in which the local memory LM (Local Memory) per one data is substantially increased multiple times by storing the data.

First, SIMD (Single)
A multi-parallel digital processor controlled by Instruction Multiple Data will be described. FIG. 1 shows the S according to the embodiment.
1 shows a main configuration of an IMD-controlled multi-parallel processor.

A large number of processor elements (Processor Elements) are one-dimensionally arranged inside the processor 1. FIG. 1 shows only three continuous element processors PE0, PE1, and PE2 as a part thereof. Each of the element processors PE0, PE1, PE2 includes a local memory (Local Memory) LM0, LM1, LM2 and a logic circuit. Further, it has a SIMD control circuit 10 for performing SIMD control on these element processors.

FIG. 1 shows only the central element processor PE1 as a representative of the logic circuit and the main part of the wiring portion. The SIMD control multi-parallel processor 1 according to the present embodiment includes local memories LM0, LM1, and LM2, which are the minimum required as processors, and an ALU (Arithmetic).
Logic Unit) and a logic circuit or wiring having some functions.

The local memory LM of a certain element processor PE1 and its adjacent element processors PE0 and PE2
0, LM2, the data path 3 for realizing the function of communicating data with each of the element processors PE as shown in FIG.
0, PE1, and PE2 may be at least one each on the left and right. As a result, the ALU of the element processor PE1 becomes
The data in the local memories LM0 and LM2 of the adjacent element processors PE0 and PE2 can be read and processed. Conversely, the ALU of the element processor PE1 processes the data, and the adjacent element processors PE0 and PE2 receive the data stored in the local memory LM1.
You can also process it as your own data.

In order to simplify the following description, the data path 3 for realizing the data communication function with the local memories LM0 and LM2 of the adjacent element processors PE0 and PE2 is connected to the adjacent left and right element processors. LM
It is assumed that one exists for each of 0 and LM2. Of course, a configuration having a data path with two or more adjacent element processors on one side may be used. If this is complicated, for example, an ALU communication function is provided, and this function is used to connect to a distant element processor. Data exchange is also possible.

The element processor PE1 stores a value stored in the local memory LM1 (specifically, an ID
No.), a memory selection means 4 for selecting one of the local memories LM0, LM1, and LM2 connected by the data path 3, and a validity determination for determining whether the output data sent from the ALU is valid or invalid. Means 5 are also provided. Note that the memory selection unit 4 and the validity determination unit 5 in the present embodiment are not actually added with a new physical configuration, but are realized by a program of the SIMD control circuit 10 using an existing configuration. The memory selection means 4 changes the logic of a control line (not shown) to 1 or 0, for example, in the form of a 1-bit flag for memory selection, whereby the local memories LM0, LM1, L
This is realized by giving permission such as reading to M2. In addition, the validity determining means 5 includes element processors PE0, PE
This is realized by using an existing function of an external block for processing the output data of the PE1, PE2, for example, an output circuit not shown, by controlling whether or not the output data to be sent is taken in.

Thus, SIMD to which the present invention can be applied
The controlling multi-parallel processor 1 reads a data communication function between the element processors, in particular, data used for processing of the element processor by using the data communication function from a local memory of another element processor in addition to the normal ALU. It is assumed that it has a function and a function of controlling selection of outputs of element processors.

FIG. 2 is a flowchart showing an example of specific processing of the SIMD-controlled multi-parallel processor 1 having the above-described configuration.

First, in step ST0, in order to make a plurality of continuous element processors PE0, PE1 and PE2 into one virtual group 2, each element processor group is utilized by utilizing a data communication function between element processors. Each of the local memories LM0, LM1, and LM2 in 2,... Is assigned a unique ID number. In this ID number setting, for example, the illustrated three element processors PE0, PE0 are connected via a data path 3 connecting the element processors.
PE1, ID of each PE2 number ID _0, ID _1, ID ₂
Are assigned as 0, 1, and 2. At this time, the array of ID numbers is repeatedly assigned to other groups in the same manner as 0, 1, 2, 0, 1, 2, 0, 1,. Then, the unique ID number in each group is stored at the same address in the local memory in all the element processors.

As a more specific ID number setting method,
First, the three element processors PE0 and PE shown in FIG.
1, one of all element processors including PE2
When the leftmost one attempts to read out from the element processor on the left side, the hardware state is always set to be readable. For example, it is determined that it is optimal to divide the number of element processors into n groups according to processing, but if the number of element processors is divided by n, a fraction is generated. An ID number meaning access prohibition is assigned to one of the element processors. This prevents that there is no element processor to read when a certain processor performs processing. First, the values of the local memory at the addresses where the ID numbers are stored are cleared for all the element processors.

Subsequently, the ID is stored in the memory area of the address for storing the ID number of the leftmost element processor among the group of processable element processors whose access is not prohibited.
= 0 is written. Then, by utilizing the characteristic of the SIMD control, all other element processors are notified that "the value of the ID of the element processor PE on the left side is added by one, and the ID of the own element processor is" ID ".
Is returned to 0 when the value of becomes "3". As a result, the first ID write (ID = 0)
Then, from the left side, the ID numbers are 1, 2, 0, 1,
It is decided as 2,0,1, ... In such ID number setting, even if the number of element processors is large, a regular ID number is propagated to the rightmost element processor, and the last ID number is always 2. The confirmed ID number is
It is stored at a predetermined address in each local memory.

Next, in step ST1, the input data is distributed to only one specific element processor in each group. That is, for example, the ID number ID shown in FIG.
₀ , ID ₁ , and ID ₂ are three consecutive element processors PE 0, PE 1, and PE 2 from left to right in order of 0, 1, and 2, respectively.
2 as one element processor group 2, data is input only to a specific element processor in one element processor group 2. Here, 3
It is assumed that valid data is input only to the central element processor PE1 of the two element processors PE0, PE1, PE2.

Next, the operation proceeds to the arithmetic processing 1 in step ST2. Here, a single common processing instruction is issued to all the element processors including the element processors PE0, PE1, and PE2 by SIMD control. . However, as described above, only the central element processor PE1 actually receives valid data. Then, along with the given processing instruction, each element processor P
E0, PE1, and PE2 execute the operation processing 1.

In the course of this processing, the central element processor PE1 wants to store the intermediate processing result as temporary data in its own local memory LM1 in the course of the operation. The capacity may reach the limit. In such a case,
The memory areas of the local memories LM0 and LM2 of the left and right element processors PE0 and PE2 which are not actually processing valid data are used for temporary data storage. Also,
Even if the local memory LM1 has a sufficient free area, the free area may be desired to be reserved for the purpose of temporarily saving data during the later synthesis processing. In this case, the local memories LM0 and LM2 are also used. Use temporarily. In any case, the calculation result in the middle of the processing is changed to the intermediate result 1
However, the intermediate result 1 (the same applies to an intermediate result 2 described later) is assumed to be an operation result that is not immediately used for the subsequent processing. For example, the calculation result at the time when some routine work of the repetition calculation is completed corresponds to the intermediate result here. However, in many cases, the calculation result to be output has to be a calculation result used in the subsequent processing. In that case, although not particularly mentioned in the following description, the next step ST
3, after storing through ST4, etc., the intermediate result stored in the local memory LM0 or LM2 is read and used at any time as appropriate, as is performed by a SIMD control processor having a normal communication function. Will be.

Prior to storing the intermediate result 1, first, in step ST3, the element processors PE0, PE1,
In each PE2, it is determined whether or not its own ID number matches a predetermined ID number other than the element processor PE1 that has input the valid data. In this example, first, it is determined whether the predetermined ID number (ID ₀ = 0) matches its own ID number. The central element processor PE1 of interest
Since the ID numbers of the element processors PE2 on the right side do not match, the intermediate processor 1 holds the intermediate result 1 and is in a standby state until another element processor requests the sweeping of the intermediate result 1. If there is no sweep request after a predetermined period, the process is continued.

On the other hand, the element processor PE0 on the left side
Since the D numbers match, in step ST4, the intermediate result 1 is stored according to the common processing instruction. This processing instruction includes, for example, “the self ID is ID = m−1 (m:
If it is the ID number of the PE that input the valid data), then PEm
Is stored in LM (m-1). "Therefore, the element processor PE0
Requests an intermediate result 1 from an adjacent element processor PE1,
The received intermediate result 1 is stored in its own local memory LM.
After saving to 0, proceed to the next processing step. The element processor PE1 proceeds to the next processing step when the intermediate result 1 is discharged.

Each element processor PE0, PE1, PE2
Executes the arithmetic processing 2 in step ST5 in the same manner. If it becomes necessary to store the temporary data again during this process, the ID number coincidence determination and the data storage are performed in the same manner as described above. That is, in step ST6, it is determined whether the own ID number matches another ID number (ID = 2) not used in step ST3. Since the ID of the central element processor PE1 of interest and the element processor PE0 on the left side do not match, the intermediate element processor PE1 holds the intermediate result 2 and keeps holding the intermediate result 2 until another element processor requests the sweeping of the intermediate result 2. In standby state. If there is no sweep request after waiting for a predetermined period,
continue processing.

On the other hand, the element processor PE2 on the right
Since the D numbers match, in step ST7, the intermediate result 2 is stored according to the common processing instruction. This processing instruction includes, for example, “the self ID is ID = m + 1 (m:
If it is the ID number of the PE that input the valid data), then PEm
Is stored in LM (m + 1). ”Therefore, the element processor PE2
Requests an intermediate result 2 from the adjacent element processor PE1,
The received intermediate result 2 is stored in its own local memory LM.
After storing in step 2, the process proceeds to the next processing step. The element processor PE1 proceeds to the next processing step when the intermediate result 2 is discharged.

At this point, as viewed from the central element processor PE1 of the three element processors PE0, PE1 and PE2 of a certain PE group 2, the left and right element processors PE1
In the local memories LM0 and LM2 of 0 and PE2, the intermediate results 1 and 2 of the arithmetic processing performed by themselves are stored, respectively. Therefore, for the element processor PE1,
It is as if the local memories LM0 and LM2 functioned as a part of their own local memory LM1. On the other hand, the other two element processors PE0, PE
In E2, the intermediate results 1 and 2 are similarly calculated, but valid data is not originally input, and arithmetic processing requiring such a large memory space cannot be correctly executed. This is because there is no place to store the intermediate results 1 and 2.

As described above, when one PE group 2 is regarded as one virtual element processor PE, it can be understood that the local memory capacity can be three times that of the original element processor.

In the next step ST8, the element processors PE0, PE1 and PE2 perform the final operation processing 3. If the result of this operation processing 3 becomes the final output data as it is, steps ST9 and ST1
Skipping 0, the process flow proceeds to step ST11.

When it is desired to combine the result of the arithmetic processing 3 with one of the intermediate results 1 and 2 calculated previously, the combining processing 1 is executed in the next step ST9. At this time, when the intermediate result 1 is read and used for the synthesizing process 1, the intermediate result 1 is read from the element processor having the ID number of (own ID number -1). When the intermediate result 2 is read and used for the synthesizing process 1, the (self ID number + 1) I
The intermediate result 2 is read from the element processor of the D number. Such processing instructions are transmitted to all the element processors PE0, P
It is common to E1 and PE2. Therefore, other element processors P other than the element processor PE1 using the valid data
E0 and PE2 cannot read a normal intermediate result. For example, for the element processor PE2, as described above, the intermediate result cannot be stored in the adjacent element processors, and if there is a margin in its own memory capacity, the intermediate results 1 and 2 should be stored there. . Nevertheless, this common instruction causes element processor PE2 to erroneously read an unrelated intermediate result from the adjacent element processor PE1 (or PE4 if present). Therefore, the result after the synthesis processing 1 is an unintended result. This is the same for the other element processor PE0.

By making good use of the fact that the common instruction is issued under the SIMD control as described above, correct data can be read out only from the central element processor PE1 to which valid data has been given, and thus the data can be normally read out. Compositing process 1
Can be performed. When the result of the synthesis processing 1 is to be final output data, the processing flow skips the next step ST10.

Further, when it is desired to combine the result of the combining process 1 with another intermediate result which has not been combined, the combining process 2 is executed in the next step ST10. At this time, as in the case of the synthesizing process 1, only the central element processor PE1 can correctly read data, and the other element processors PE0 and PE2 read incorrectly. Therefore, a correct result of the synthesis processing 2 is output only from the central element processor PE1.

Next, the validity of the output data is determined in steps ST11 to ST13. As described above, since only the central element processor PE1 has obtained the correct operation result (or the combined result), at first glance, it does not seem necessary to determine the validity. However, the SI
When data is output from the MD-controlled multi-parallel processor to the outside, only the correct data is output. For this purpose, some output selection is performed. The operation of the output pointer circuit, that is, the control is not limited to such a control that the output unit prepares a validity determination flag and changes it to 1 (valid) or 0 (invalid). Ignoring the result is also included in this validity determination in a broad sense. In the case where processing cannot be performed unless two or more local memories are used, a common instruction may include "stop processing when own memory reaches a limit". The output data itself is not sent from other than the central element processor PE1. Such control is also one type of the validity determination here.

In the example of FIG. 2, in step ST11, all ID numbers in the PE group 2 are checked, and
Only when D = 1, the output data of the element processor PE1 is validated in step ST12 and output in step ST13. On the other hand, the output data of the other element processors PE0 and PE2 that do not have ID = 1 are invalidated in step ST14 and are not output in step ST13, or are output after being invalidated in step ST14. The invalidated output data is not output to the outside.

FIG. 3 shows the flow of data in this embodiment in an easy-to-understand manner. In the above description,
The case where valid data is input to the central element processor PE1 has been described.
Valid data may be input to PE2. In this case, it is assumed that there is no element processor that stores the intermediate result. However, at the beginning of the processing, the PE group is set so that the element processor to which valid data is input is always located at the center. We will deal with it by changing the division. Alternatively, this situation can be avoided if the ID numbers 0, 1, and 2 are set to a rule that changes in a circular manner. For example, when the element processor that has input valid data is PE0 at the left end, when the intermediate result 1 is stored, if “the self ID is ID = m−1 (m: the ID number of the PE that has input valid data), For example, if the intermediate result 1 of PEm is stored in LM (m-1), the ID of the own device becomes −1, such ID number does not exist, and the intermediate result 1 is stored. It will not be. To avoid this situation, if the ID number is changed cyclically, ID = −
Since 1 = 2, the element processor PE2 determines that the intermediate result 1
Save. Then, (the own ID number -1) =-1 = 2 included in the command at the time of reading, and the intermediate result 1 can be read normally. This method has an advantage that when the processing flow of FIG. 2 is repeatedly performed in the PE group, step ST0 can be omitted from the second time on.

In the above description, the three element processors PE0, PE1 and PE2 are treated as one PE group 2. However, if a data communication function for a local memory between adjacent element processors is used, the PE group is theoretically considered. There is no upper limit on the number of element processors in 2. At this time, when referring to the data in the local memory of the distant element processor, if the element processor located in the middle is merely relayed and the data is transferred in a bucket brigade format, the data path 3 as hardware can be added. Is not required.

In the first embodiment, the local memories LM0, LM of the plurality of element processors PE0, PE1, PE2
1 and LM2 are virtually allocated to one data and used. Therefore, when the number of element processors in the PE block 2 is n, the number of data that can be processed at a time by the SIMD control processor 1 is 1 / n, but the local memory that can be used for one data is substantially. It becomes possible to increase the number substantially n times. Since such a virtual memory expansion method can be performed by a program of the control unit,
This is extremely useful in that it can be realized without changing the hardware configuration of the conventional SIMD control processor at all.

Second Embodiment In the second embodiment, one processor is assigned to each of a plurality of element processors.
One valid data is allocated, but at the same time, by inputting different parameters to the element processors to which the same data is allocated, and performing the processing according to the common instruction code, the processing per one data is substantially performed. We propose a method to increase the number of steps multiple times.

In this processing, a SIMD having the same structure as that of FIG.
A control processor is used. Further, as a specific example of the processing, as shown in FIG. 4, there are three parallel FIR filtering processing P1 and processing P2 for mixing the processing results. In the FIR filtering process P1, data at a plurality of sampling points in the original image is weighted by a predetermined coefficient. Then, in the next mixing process P2,
The weighted data is combined. The image data after the synthesis is obtained by interpolating image information missing at a new sampling point.

FIG. 5 is a flowchart showing a processing procedure according to the second embodiment. First, in step ST0, 0, 1, 2, 2, and 3 are performed in the same manner as in the first embodiment.
..., ID numbers are stored in the local memory of each element processor, and ID numbers ID ₀ , ID
_The three element processors PE 0, PE 1, and PE 2 in which ₁ , ₁ and ID ₁ are lined up from the left with 0, 1, and 2 are collectively referred to as one element processor (PE) group 2.

In step ST21, unlike the first embodiment, each of the element processors PE0, PE0,
The same valid data is input to PE1 and PE2. Here, since the FIR filtering processing is performed, the data is image data at the time of sampling the original image, for example, data such as luminance Y or hue Cr, Cb, and the same data is used by a plurality of element processors in the PE group. . In this case, each element processor PE0, PE0,
It is not necessary to input valid data to all PE1 and PE2, but to input data only to, for example, the central element processor PE1 in the PE group 2 and to internally input it to the other element processors PE0 and PE2 in group 2. May be delivered.

In the following step ST22, filter coefficients of a plurality of FIR filters are input to the respective element processors PE0, PE1 and PE2 as parameter sets of different combination patterns, apart from the data. The parameter set includes three different combinations of parameters (filter coefficients), but it is necessary that at least parameters necessary for generating output data of the central element processor PE1 are dispersed.

Then, in step ST23, FIR filtering processing P1 is executed using the input data and parameter set. During this process, SI
A common instruction code of the MD control program is issued, and all the element processors PE0, PE1, PE
2 performs the FIR filtering process P1 in parallel in the same procedure.

After the FIR filtering process P1, the mixing process P2 is executed in the next steps ST24 and ST25. Specifically, for example, as shown in FIG. 5, the combining process 1 is performed in the first step ST24, and the combined result is further subjected to the next step ST25.
Performs the synthesis process 2. These combining processes 1 and 2
For example, each of the element processors PE0, PE1, and PE is utilized by using a communication path between ALUs not shown in FIG.
2, while taking in the processing results from the left and right element processors centering on itself.

For example, the first synthesis processing 1 (step S
The common command of T24) is “combine the processing result of itself with the processing result of the PE of (own ID number) −1”, and the next common command of the combining processing 2 (step ST25) is The result of processing 1 is (self ID number) +
According to this command, the element processor PE1 performs the synthesis processing 1 using the processing result of the element processor PE0, and further combines the result with the processing result of the element processor PE2. However, the element processor PE0 combines its own processing result with the processing result of the other PE group to the left of the PE group 2 at the time of the combining processing 1 and outputs an error. Similarly, the element processor PE2 compares the result of its own synthesis processing 1 with the other Ps on the right of the PE group 2 during the synthesis processing 2.
The result is combined with the processing result in the E group, and an erroneous processing is performed. Therefore, only the central element processor PE1 can obtain correct output data.

Thereafter, the validity of the output data is determined in steps ST11 to ST13 in the same procedure as in the first embodiment. In this last step ST13, for example, the result is output only from the central element processor PE1, and the processing flow shown in FIG. 5 is completed. In this processing method, if three element processors PE0, PE1, and PE2 are regarded as one PE group 2, and considered as one virtual element processor, one FIR filtering is performed with a processing capacity three times as large as that of a normal element processor. Processing will be performed.

In the second embodiment, the ID number does not change cyclically, and the number of element processors in one PE group 2 has no theoretical upper limit.

As described above, in the second embodiment, the same PE
If valid data is input to all of the element processors in the group and a different parameter set is input to each of the element processors in the PE group, different processing of the parameters is performed on each of the valid data completely in parallel. it can. After performing the integration process while distinguishing the processed data by the ID number of each element processor, finally, the output of each element processor is selectively controlled by, for example, the ID number. As a result, one correct processing result is obtained as output data in each PE group. In this processing, if each group is regarded as one virtual element processor, the virtual element processor has a higher processing capability than the individual element processors. In effect, the number of element processors that can obtain an effective output by this processing method is reduced. However, in the field of image processing and the like, pixels that are desired to be processed in parallel at one time are often intermittent.
This means that the processing capability of the element processor, which has conventionally contributed only once in several processes, has been effectively utilized.
Moreover, in the present embodiment, a highly efficient SIMD control processor with an increased number of parallel processes can be realized without any change in the hardware configuration.

[0054]

According to the SIMD control parallel processing method and apparatus according to the present invention, a local memory is effectively multiplied by a plurality of times for a data stream in which the element processor is wasted, while effectively utilizing the element processor. It has become possible to realize the increase processing without changing the hardware configuration.

Further, according to another SIMD control parallel processing method and apparatus according to the present invention, the number of parallel processes that repeats exactly the same process except for different parameters (filter coefficients), such as FIR filtering, can be reduced by hardware. , The processing efficiency can be increased.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a main configuration of a SIMD-controlled multi-parallel digital processor according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating a processing procedure according to the first embodiment.

FIG. 3 is a schematic diagram illustrating a flow of data between element processors according to the first embodiment.

FIG. 4 is a diagram illustrating processing blocks implemented in a second embodiment.

FIG. 5 is a flowchart illustrating a processing procedure according to a second embodiment.

[Explanation of symbols]

1: SIMD-controlled multi-parallel digital processor (SI
MD control parallel processing device), 2 ... virtual element processor group, 3 ... data path, 4 ... memory selection means,
5 ... validity determining means, PE0, PE1, PE2 ... element processors, LM0, LM1, LM2 ... local memory (memory unit), ALU ... processor, ID _0, etc. ... ID number (identification code).

Claims (6)

[Claims] 1. An SIMD control parallel processing method for controlling a plurality of one-dimensionally arranged element processors by a single instruction, wherein the SIMD control parallel processing method is repeatedly assigned in the same arrangement for each group of a predetermined number of element processors, In addition, an identification code that can specify an arbitrary element processor in each group is assigned to each element processor, data is input to the plurality of element processors, and the same processing is executed. In the element processor, the intermediate result of the above processing is stored in another element processor specified based on the specific identification code, and the stored intermediate result is read out by the specification based on the specific identification code and the subsequent SIMD control parallel processing method used for processing. 2. The SIMD control parallel processing method according to claim 1, wherein a result of said processing is selected and output by designation based on a specific identification code. 3. A SIMD control parallel processing method for controlling a plurality of one-dimensionally arranged element processors by a single instruction, wherein the method is repeatedly assigned in the same arrangement for each group of a predetermined number of element processors, In addition, an identification code that can specify an arbitrary element processor within each group is assigned to each element processor, data and parameters are input to the plurality of element processors, and the same processing is executed. A SIMD control parallel processing method in which some processing results are integrated based on an identification code as a reference, and the result of the integration processing is selected and output according to the specification based on the identification code. 4. A plurality of one-dimensionally arrayed ones each including a memory unit for storing information and a processing unit for executing processing based on the information stored in the memory unit, and capable of data communication between adjacent ones. SIMD by using a single instruction
A SIMD control circuit for controlling the SIMD control, wherein the SIMD control is provided with an identification code that is repeatedly assigned in the same arrangement for each group of a predetermined number of element processors, and that can specify an arbitrary element processor in each group. Assigned for each element processor, input data to the plurality of element processors, execute the same processing, and, in a specific element processor in the group, determine an intermediate result of the processing based on a specific identification code. SIMD including control for storing in another designated element processor, reading out the stored intermediate result by designation based on the specific identification code, and using the same for subsequent processing
Control parallel processing unit. 5. The SIMD control parallel processing apparatus according to claim 4, wherein said SIMD control further includes a control for selecting and outputting a result of said processing by designating said specific identification code as a reference. 6. A plurality of memory units each of which is one-dimensionally arranged including a memory unit for storing information and a processing unit for executing processing based on the information stored in the memory unit, and capable of data communication between adjacent ones. SIMD by using a single instruction
A SIMD control circuit for controlling the SIMD control, wherein the SIMD control is provided with an identification code that is repeatedly assigned in the same arrangement for each group of a predetermined number of element processors, and that can specify an arbitrary element processor in each group. Assigned for each element processor, inputting data and parameters to the plurality of element processors, causing the same processing to be executed, and integrating and processing some of the processing results of the element processors with reference to an identification code. And a SIMD control parallel processing apparatus including a control for selecting and outputting the result of the integration processing by designating the identification code as a reference.