JP3408888B2 - Data processing processor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data encoding device for data compression, a data decoding device for data expansion, or a data processing device for data editing.

[0002]

2. Description of the Related Art There is an example in which a conventional general-purpose processor, in which a multiplier and a cumulative adder are the basics of an arithmetic unit, is provided with a dedicated circuit in order to speed up the processing . For example, as a processor for performing image signal processing, DCT circuit (an image signal circuit for converting the frequency components are often used in high-efficiency coding of an image signal.) The configuration with the dedicated arithmetic circuit, It is generally known.

[0003] a plurality of processor elements and memory elements that operate simultaneously and independently, the image processing apparatus having a plurality of independent bus coupling them,
It is described in JP-A-60-159973.

[0004]

[SUMMARY OF THE INVENTION However, in the data processor device of traditional, although faster processing by pipelining and the dedicated arithmetic circuit has been achieved, processing data occupies the data bus 120 of the processor The rate was high, and it was necessary to supply data to the data bus at high speed.

Further, the data-only bus and a plurality placed, a method to enhance the speed and parallel processing has been invented, output and operation of data to the switching control and dedicated circuits of the data bus The instruction for controlling the request had to be incorporated in the instruction system of the processor, and the independence of the data dedicated processing circuit was low.

[0006]

In a data processor device according to a representative embodiment of the present invention, input data to a data dedicated processing circuit and output data processed by the circuit are respectively referred to as a data bus of the processor. It uses an independent dedicated bus and has a circuit configuration connected to a memory managed by the processor.

A data processor unit according to a typical embodiment of the present invention has a plurality of data dedicated processing circuits, and each data dedicated processing circuit is independent of the data bus of the processor as in the first invention. Use a dedicated bus,
It has a circuit configuration connected to a memory managed by a processor, and is connected so that output data processed by one dedicated data processing circuit can be input as an input to another dedicated circuit via a memory managed by the processor. It has a circuit configuration.

A data processor unit according to a typical embodiment of the present invention uses a serial port capable of sequentially outputting data as an input of the above-mentioned data dedicated processing circuit, that is, as a data output port of a memory managed by the processor. .

A data processor unit according to a typical embodiment of the present invention uses a serial port capable of sequentially inputting data as an output of the above-described data dedicated processing circuit, that is, as a data input port of a memory managed by the processor. .

A data processor unit according to a typical embodiment of the present invention has two memories managed by the above-mentioned processor, and when one is connected to a data bus of the processor, the other is connected to a data dedicated processing circuit. Has a configuration.

A data processor unit according to a typical embodiment of the present invention is the above-mentioned data processor unit, and in the above-mentioned data processor unit, an operation request or a stop request to an exclusive data processing circuit, an operation parameter, an operating state of the exclusive data processing circuit, Information is exchanged with data to be written in or read from a register managed at any address on a memory map managed by the processor. .

A data processor device according to a typical embodiment of the present invention includes an FP in addition to the data dedicated processing circuit described above.
By using a rewritable device of GA, the circuit can be changed as needed.

A data processor device according to a typical embodiment of the present invention is configured to define a layout position on a chip of the above-described data dedicated processing circuit and perform layout synthesis of a necessary dedicated circuit on the chip.

[0014]

In the data processor unit according to the typical embodiment of the present invention, the data processed by the data dedicated processing circuit is supplied from the memory managed by the processor through a dedicated bus independent of the data bus of the processor. At the same time, the data processed by the data dedicated processing circuit operates so as to be output to another memory managed by the processor using a dedicated bus independent of the data bus of the processor.

In a data processor unit according to a typical embodiment of the present invention, at least two sets of data dedicated circuits of the data processor unit of the first invention are laid out on a chip and the first data dedicated process is performed. The image data processed by the circuit operates as the input image data of the second data dedicated processing circuit via the memory managed by the processor.

A data processor unit according to a typical embodiment of the present invention uses a serial port as an interface between a data dedicated processing circuit and a memory managed by the processor, and transmits data in response to a request from the data dedicated processing circuit. It operates to read or write sequentially.

A data processor unit according to a typical embodiment of the present invention has a memory managed by the data processor unit with a capacity of two sides for the same address, and one of the memories is a data bus of the processor. When connected, the other memory operates as if it were connected to the data dedicated processing circuit.

The data processor unit according to a typical embodiment of the present invention is a processor for exchanging information such as an operation request or a stop request for a data dedicated processing circuit, an operation parameter, or an operation state of the data dedicated processing circuit. The data is written or read in the register managed by any address on the memory map managed by the.

Further, the data processor unit according to the typical embodiment of the present invention uses a device capable of rewriting the data dedicated processing circuit, so that the data dedicated circuit can be freely changed according to the application and need. To work.

In addition, the data processor unit according to the typical embodiment of the present invention limits the layout position of the data dedicated processing circuit on the chip in advance, so that the data dedicated processing circuit can be changed as necessary. , So that it can be performed without changing the layout of other parts of the data processor unit.

[0021]

FIG. 1 shows a first embodiment of the present invention. This drawing shows the basic configuration of the arithmetic unit of the data processor device of the invention by taking image signal processing, particularly image signal encoding processing as an example.

The processor of this embodiment is the arithmetic operation unit 2
(ALU) and a cumulative adder 4 (ACC) as its basic configuration. The processor of FIG. 1 has an instruction memory (which is composed of a ROM or a RAM) which stores instructions, and the ALU performs addition, subtraction, shift, etc. according to the instructions stored in the instruction memory. Arbitrary arithmetic processing is performed and the result is stored in ACC which is a register connected to the ALU. ALU
Since it is configured so that various calculations can be performed according to instructions, it is suitable for performing calculation processing including different calculation contents. Further, since the calculation result is stored in the ACC, it is suitable when the next calculation content changes depending on the calculation result of the ALU or when the next calculation process is performed using the ALU calculation result.

Although not particularly limited, the processor of this embodiment further includes an integrator 3 (MPY) for performing an integration operation, and a ROM 5 for storing operation coefficients such as quantization coefficients and used for data conversion. Generally, when image data is encoded, a large amount of integration processing such as quantization processing and inverse quantization processing is required.
By having the above, it becomes possible to perform efficient image processing.

In the present embodiment, further, there are memories 6, 7, 8 for storing data, a DCT circuit 9 for performing discrete cosine transform as a data dedicated processing circuit between the memories, and a filter circuit for performing arithmetic processing of image data. It has a circuit configuration including A (FLT).

As shown in FIG. 1, the image data read from the data memory 6 and input to the DCT circuit 9 is connected by providing a dedicated bus independent of the data bus 1 of the processor. Also, the image data processed by DCT is
A dedicated bus independent of the data bus 1 of the processor is provided and connected to a memory 7 different from the memory 6 used for input. Further, the image data in the memory 7 is FLT.
The circuit A is connected to the data bus 1 of the processor by a dedicated bus, and the image data processed by the FLT circuit A is similarly connected to another memory 8 by an independent dedicated bus.

With such a configuration, the dedicated data processing circuit and the memory are connected by a bus independent of the data bus 1 of the processor, so that the occupation rate of the data bus 1 can be reduced. . Further, since the input / output of the image data used in the data line processing circuit is all through the memory, the independence of the data dedicated processing circuit and the basic arithmetic unit of the processor is enhanced.

In the present embodiment, an example of image signal encoding processing is taken for convenience of explanation, but it can be applied to the case of image signal decoding processing. For example, in the case of performing the decoding process of the image signal, the DCT circuit 9 and the FLT circuit A are replaced with a circuit for performing the inverse discrete cosine transform (IDCT) and a circuit for performing the motion compensation to configure the image signal decoding device. You can also Also in this case, as in the case of FIG. 1, the data input memory and the IDCT circuit are connected to each other via a bus different from the data bus of the processor, and the IDCT circuit is connected to the output memory via a dedicated bus. Similarly, the input memory (the output memory of the IDCT circuit) and the output memory can be connected by a dedicated bus. When the motion compensation circuit is provided as a dedicated processing circuit, a memory for storing the reference image data is required for the motion compensation processing, but the memory space of the input memory of the motion compensation circuit is divided into two, ID in one memory space
By storing the conversion result of the CT circuit and storing the reference image data in the other memory space, a single memory shares the input memory of the motion compensation circuit with the memory for storing the reference image. be able to.

Further, even when the image signal is encoded, the data dedicated processing circuit can be changed depending on the type of the encoding process. For example, in the case of performing a moving image coding process using motion detection and discrete cosine transform, a motion detection circuit and a DCT circuit can be arranged instead of the DCT circuit 9 and the FLT circuit A. Also in this case, as in FIG. 1, the input memory of the motion detection circuit and the motion detection circuit are connected by a bus independent of the data bus of the processor, and the output memory of the motion detection circuit and the motion detection circuit are dedicated. Connected by bus, DCT circuit, input memory of DCT circuit (output memory of motion detection circuit) and DCT
It is possible to employ a configuration in which the circuit and the output memory of the DCT circuit are connected by a dedicated bus.

Even in such a case, since the ratio of the data bus occupied by the processor can be reduced, the same effect as the embodiment shown in FIG. 1 can be obtained.

Further, according to this embodiment, the DCT circuit 9 and the FLT circuit A are adopted as the data dedicated processing circuit, but the present invention is not limited to this, and various data dedicated processing circuits as described above may be adopted. You can As in this example,
As a data dedicated processing circuit connected to an independent bus, a processing circuit whose contents of processing or operation are fixed, a processing circuit which sequentially processes input data and outputs the data, and its circuit It is possible to use a processing circuit in which the contents of the next processing are not changed by the result of the operation performed in the above and the result of the operation is used in another processing circuit. The above-described DCT circuit or IDCT circuit is for sequentially converting input image data and outputting it, and since the amount of calculation is relatively large, a configuration using a dedicated bus and memory as in this embodiment is used. Is more effective.

Further, in FIG. 1, for convenience, the data memory 6,
Although 7 and 8 are represented as different memories, it is only necessary that these memories can be distinguished in terms of memory space. Therefore, the memory space of a single memory is divided and allocated as data memories 6, 7, and 8, respectively. It can also be realized by

FIG. 2 shows an example of the configuration of the present invention. This configuration example is an example in which a serial port is used as an output interface with the data dedicated processing circuits of the data memories 6 and 7.

The data memory 6 includes a random port connected to the data bus 1 and a DC dedicated data processing circuit.
It is configured to have a serial port connected to the T circuit 9. The data memory 7 has a random port and receives data from the DCT circuit 9 via the selector 73 or is connected to the data bus 1. Further, the data memory has a serial port connected to the FLT circuit A which is a data dedicated processing circuit. In addition, the data memory 8
Has a random port and receives data from the FLT circuit A via the selection 82 or is connected to the data bus 1. In this embodiment, a DCT is used as a data dedicated processing circuit.
Since the data memory 8 has only the circuit 9 and the FLT circuit A, the data memory 8 is a single port memory having no serial port.

As a concrete operation, the image data processed by the processor is written in the RAM 61 from the data bus 1 through the random port of the data memory 6. The reason why the port connected to the processor is a random port is that it is necessary to perform address conversion and output to the RAM 61 when image data output from the processor is zigzag scanned.

The RAM 61 transfers the image data in parallel to the serial register 62 in the order of processing, and the serial register 62 serially outputs the image data via the serial port in response to the read request from the DCT circuit 9. . Since the image data processing, particularly the conversion processing in the DCT circuit 9, processes the image data in order, the data memory 6 can output the data serially. Therefore, the configuration of this embodiment is suitable. There is.

Next, the image data (here, DCT coefficient) processed by the DCT circuit 9 is written to the RAM 71 from the random port via the selector 73. In the present embodiment, the selector 73 selectively connects the image data processed by the DCT circuit 9 and the data bus 1. As a result, the port for receiving the output of the DCT circuit 9 and the port for exchanging data with the data bus of the processor can be made common. D
To use the image data (DCT coefficient) as the CT result in the basic circuit section of the processor by encoding or quantizing,
The selector 73 is switched to RA on the data bus 1 of the processor.
Switch to connect the random port of M71.
Further, since the output of the DCT circuit 9 is serial data, it is possible to use this port as a serial port, but a random port is adopted in order to have a degree of freedom in exchanging data with the processor.

As with the RAM 61, the output of the RAM 71 is a plurality of bits of data transferred in parallel to the serial register 72 and output via the serial port.

The image data from the RAM 71 is input to the RAM 81 via the selector 82 as in the data memory 7. The output of the RAM 81 is a selector 82 from a random port.
Is connected to the data bus 1 via.

In this embodiment, the data dedicated processing circuit is FL.
The data memory 8 does not have a serial output port like the data memory 7 because it ends in the T circuit A. As a matter of course, when only the DCT circuit 9 is provided as a data dedicated processing circuit, the memory on the output side of the DCT circuit 9 can have a structure like the data memory 8. When a plurality of dedicated data processing circuits are provided, the last memory in the data processing flow has a configuration like the data memory 8.

Further, according to this embodiment, the image data RA
The image data of M71 can be filtered by the FLT circuit A as in the DCT operation. The result is also written in the RAM 81 and can be read from the data bus 1 of the processor.

FIG. 3 shows an embodiment in which a serial port is used as an input / output interface with the data dedicated processing circuits of the data memories 6, 7, and 8.

The data memory 6 has a random port connected to the data bus 1 and a serial port connected to the DCT circuit 9, as shown in FIG. Data memory 7
Has a serial port for receiving the image data from the DCT circuit 9, a serial port for outputting the image data to the FLT circuit A, and a random port connected to the data bus 1. There is. The data memory 8 has a serial port for receiving the output of the FLT circuit A and a random port connected to the data bus 1.

As a concrete operation, image data to be DCT processed is written from the data bus 1 of the processor to the RAM 61. The RAM 61 transfers the image data to the serial register 62 in the order of processing. Serial register 6
The image data of No. 2 are sequentially read out and DCTed by a read request from the DCT circuit 9. The processed image data (DCT coefficient) is written in another memory 7. At this time, DCT processed image data (DCT coefficients) are sequentially output and input to the serial register 74 in the memory. The serial register 74 stores RA every time a fixed number is stored.
Transfer to M75 and store. The image data (DCT coefficient) stored in the RAM 75 can be more freely read by the random port connected to the data path 1 of the processor, and the operation can be performed in the basic circuit portion of the processor.
Further, independently of that, the image data in the image data RAM 75 can be filtered by the FLT circuit 8 as in the DCT operation. With the FLT circuit A,
The filtered image data is also written in the memory 8 and can be read out from the data bus 1 of the processor.

In FIG. 4, the data memories 6 and 7 have two sides of R.
This is an embodiment having a configuration having an AM. As a concrete operation, the image data to be DCT processed from the data bus 1 of the processor is connected to the data bus of two planes.
Write to AM6A. Next, when the image data is processed by the DCT circuit 9, the selector 6C is switched and the bus connected to the data bus 1 of the processor is connected to the DCT circuit 9. At this time, at the same time, the other RAM 6B
Switches the selector 6D to be connected to the data bus 1 of the processor. The image data in the RAM 6A is D
The CT circuit 9 reads the data and performs DCT. The processed image data (DCT coefficient) is written in another memory 7. Also at this time, the DCT processed image data (DCT coefficient) is written in the RAM 7B connected to the DCT circuit 9, and the other RAM 7A in the memory is stored in the data bus 1 of the processor or the next FLT circuit A. It is connected. The image data (D
The CT coefficient) is switched by selecting the selector 7D and connected to the data bus 1 of the processor, and is freely read, and calculation in the basic circuit portion of the processor becomes possible. At this time, at the same time, the other RAM 7A operates so as to be connected to the DCT circuit 9. Also, when the image data in the memory 7 is filtered by the FLT circuit A, one of the RAMs 7B in the memory 7 is connected to the DCT circuit 9 when the processing result of the DCT is used, or a processor is used as in the DCT. When the image data desired to be FLT is input from the data bus 1 of the above, the selector 7D is switched so as to be connected to the data bus 1 of the processor, and the other RAM 7A is
The selector 7C is controlled so as to be connected to the FLT circuit A. Then, these two RAMs 7A and 7B are switched and used as in the case of DCT. The filtered image data is also written in the memory 8 and can be read from the data bus 1 of the processor.

FIG. 5 shows the overall construction of a data processor unit which is an embodiment of the present invention.

In the data dedicated processing circuit portion (inside the dotted line in the figure), as a processor, a multiplier MPY3 and an arithmetic operation unit ALU are provided.
2. Cumulative adder ACC4, RAM6, ROM5, instruction ROM_G, program counter PC_E, program register REG_F, instruction decoder DEC_D, control unit CONT_C, and external interface unit H as the control unit of the processor, data bus 1 and address bus B. It is an example of connecting with. Similar to the first embodiment, the processor includes an arithmetic unit 2 (ALU) and a cumulative adder 4.
(ACC) as its basic configuration. In the processor, the order of program execution is controlled by the program counter PC_E, and the program is sequentially read from the instruction ROM_G by relative to the program counter PC_E. The read instruction is interpreted by the instruction decoder DEC_D, and the result is read by the control unit CONT_C.
Outputs various control signals. AL by this control signal
U3 and ACC4 are controlled so that the ALU performs arithmetic processing such as addition, subtraction and shift, and the result is stored in ACC which is a register connected to the ALU.

As in the first embodiment, the ALU is configured to be able to perform various operations in accordance with instructions, so it is suitable for performing operations including different operation contents. Further, since the calculation result is stored in the ACC, it is suitable when the next calculation content changes depending on the calculation result of the ALU or when the next calculation process is performed using the ALU calculation result.

In this embodiment, the memory map is constructed as shown in FIG.

A 24-bit space is taken as an example of the memory address space, and a system area for control (system),
The operation program area (program), internal memory area (internal memory), data dedicated circuit I / O (dedicated circuit), and external memory area are mapped as shown in FIG. In the internal memory area, memories dedicated to the data processing circuit and memories for inputting / outputting data (memory 6, 7, 8 in FIG. 5) are also mapped as shown in the figure. Here, the operation command and the usage parameter of the data dedicated processing circuit, and the status indicating the operation status of the dedicated circuit are also mapped as shown in the figure on the memory map so that they can be controlled by accessing the memory address space.

Specifically, when an address (for example, address 700000) mapped for the data dedicated processing circuit is output to the address bus B, the data dedicated processing circuit performs the processing corresponding to the address. When the address 700000 is assigned to control the start / stop / hold of the process, the data dedicated processing circuit takes in the data on the data bus in response to the address appearing on the address bus and outputs it to the data bus. It is configured to perform either start / stop / hold processing according to the stored data.

As described above, by controlling the data-dedicated processing circuit by writing and reading data in the space on the memory map, the data-dedicated processing circuit can be additionally changed without changing the instruction system of the processor. Becomes

FIG. 7 shows a DCT which is a data dedicated processing circuit.
It is one configuration example of the circuit 9. This example is a block configuration diagram for realizing the two-dimensional DCT by performing the one-dimensional DCT twice. The image data input to the input port 91 is appropriately multiplied by the DCT transform coefficient by the multiplier 93, and the selector 94 (SE
L) and is accumulated in the cumulative adder 95. After the cumulative addition of a certain number, the transpose RAM is passed through the selector 96 (SEL).
Written at 97. The operation up to now has been the operation of the one-dimensional DCT. In the transposition RAM 97, the data is rearranged and output, and the above-described operation is performed once through the selector 92 to complete the two-dimensional DCT, and the image data (DC) is output to the output port 98.
T coefficient) is output. Also, as a control system for this operation,
Interface register 99 with processor, instruction decoder 9A, controller 9B, memory address generator 9C,
There is 9D. The interface register 99 is mapped on the memory map.

FIG. 8 shows an FLT which is a data dedicated processing circuit.
3 is a configuration example of a circuit A. This example realizes a two-dimensional filter by performing horizontal and vertical filtering. The image data input to the input port A1 is first subjected to the horizontal filter A2, then to the vertical filter A3, and output to the output port A4. As a control system for this operation, there are an interface register A5 with the processor, an instruction decoder A6, a controller A7, and memory address generators A8 and A9. The interface register A5 is mapped on the memory map.

In addition to the DCT circuit 9 and the FLT circuit A, a large number of data dedicated processing circuits such as a motion compensation circuit, a pattern matching circuit, a variable length coding circuit, and a variable length decoding circuit can be considered.

9 and 10 show examples of the chip configuration of the data processor unit of the present invention. In this embodiment, an example of forming a data processor device on a single silicon semiconductor substrate is shown. When the data processor device is formed on a single semiconductor substrate, it can be realized by using a so-called cell-based IC,
It can also be realized with a full custom design.

FIG. 9 is an FP capable of electrically rewriting the logical contents of the data dedicated processing circuit section from the outside.
GA (Field Programmable Gate Array) 104, 105
It is an example configured using.

In FIG. 9, the rewrite control port 10 of the FPGA is
0, a switch 102, etc., and when changing the circuit of the FPGA unit, the switch 102 is switched by setting the FPGA rewriting mode by a method such as inputting a control signal to the rewriting control port 100 of the FPGA. The circuit signal of the FPGA is input from 101. FPGA 104 which is a data dedicated processing circuit by the circuit signal,
The circuit configuration of 105 is changed.

Further, FIG. 10 shows an example in which only the data dedicated processing circuit section is realized by the gate array. In FIG. 10, only the data-dedicated processing circuit portion is provided for the gate arrays 106 and 107.
By doing so, it becomes possible to promptly deal with the data processor unit of various processes only by changing this part.

FIG. 11 is an example in which the layout position 10A on the chip of the data dedicated processing circuit portion on the data processor device is determined in advance. In this way, since the layout position is determined in advance, when another dedicated LSI 108 is used as a data dedicated processing circuit on the present data processor unit, layout can be easily performed by only changing the interface specifications.
Further, it is possible to easily change it to another data dedicated processing circuit 109 without affecting other parts of the data processor unit.

[0060]

According to the data processor device of the present invention, image data does not occupy the data bus of the processor, the degree of parallel processing between the basic functions of the processor and the data dedicated processing circuit and the parallelism between the data dedicated processing circuits. The degree of processing is increased and high-speed data processing becomes possible. Also,
The input / output of the image data processed by the data dedicated processing circuit and the image data processed by the data is performed from the memory managed by the processor, and the start / stop of the data dedicated processing circuit is controlled in the memory address space of the processor. By mapping, the data dedicated processing circuit can be changed without changing the instruction system of the basic function of the processor.

[Brief description of drawings]

FIG. 1 is a diagram of a basic configuration of an arithmetic unit of a data processor device according to an embodiment of the invention.

FIG. 2 is a diagram of an example configuration of an inventive portion of a data processor device.

FIG. 3 is a diagram of an exemplary configuration of an inventive portion of a data processor device.

FIG. 4 is a diagram of an exemplary configuration of an inventive portion of a data processor device.

FIG. 5 is a diagram of an overall configuration of a data processing processor device that is an embodiment of the invention.

FIG. 6 is a diagram of a memory map.

FIG. 7 is a diagram showing a configuration example of a DCT dedicated module.

FIG. 8 is a diagram of a configuration example of an FLT dedicated module.

FIG. 9 is a diagram of a configuration example in which an FPGA has a dedicated circuit.

FIG. 10 is a diagram of a configuration example in which a dedicated circuit is realized by a gate array.

FIG. 11 is a diagram of an application configuration example.

[Explanation of symbols]

1 ... Data bus, 2 ... Arithmetic operation unit, 3 ... Multiplier, 4 ... Cumulative adder, 5 ... ROM, 6 ... Memory, 7 ... Memory, 8 ...
Memory, 9 ... DCT circuit, A ... FLT circuit, B ... Address bus, C ... Control circuit, D ... Instruction decoder, E ... Program counter, F ... Register, G ... Instruction ROM, H ... External interface, 61 ... RAM, 62 ... Serial register, 6A ... RAM, 6B ... RAM, 6C ... Selector,
6D ... Selector, 71 ... RAM, 72 ... Serial register, 73 ... Selector, 74 ... Serial register, 75 ... R
AM, 76 ... Serial register, 7A ... RAM, 7B ...
RAM, 7C ... selector, 7D ... selector, 81 ... RAM,
82 ... Selector, 83 ... Serial register, 84 ... RA
M, 91 ... Input port, 92 ... Selector, 93 ... Multiplication circuit, 94 ... Selector, 95 ... Cumulative adder, 96 ... Selector,
97 ... Transpose RAM, 98 ... Output port, 99 ... Register, 9A ... Decoder, 9B ... Control circuit, 9C ... Address controller, 9D ... Address controller, A1 ... Input port, A
2 ... Horizontal filter, A3 ... Vertical filter, A4 ... Output port, A5 ... Register, A6 ... Decoder, A7 ... Controller, A8 ... Address controller, A9 ... Address controller, 1
00 ... FPGA rewrite control signal, 101 ... Input port, 1
02 ... switch, 103 ... processor main circuit, 104
... FPGA circuit, 105 ... FPGA circuit, 106 ... Gate array circuit, 107 ... Gate array circuit, 108 ... Dedicated LSI, 109 ... Data dedicated processing circuit, 10A ... Layout position, 120 ... Data bus, 121 ... RAM, 1
22 ... ROM, 123 ... Multiplier, 124 ... Arithmetic operation unit,
125 ... Cumulative adder, 126 ... DCT, 130 ... Data bus, 131 ... Processor, 132 ... Memory, 13
3 ... memory, 134 ... processor element, 135 ...
Processor element 136 ... Data dedicated bus, 13
7 ... Data dedicated bus, 138 ... Data dedicated bus, 139
… Data-only bus.

Continuation of front page (56) Reference JP-A-3-225478 (JP, A) JP-A-3-132841 (JP, A) JP-A-1-162971 (JP, A) JP-A-4-211854 (JP , A) JP 6-52101 (JP, A) JP 5-40776 (JP, A) JP 60-159973 (JP, A) JP 3-77178 (JP, A) JP 5-257872 (JP, A) JP-A-6-339018 (JP, A) JP-A-3-268054 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 12/00 -12/06 G06F 13/16-13/18 G06F 15/16-15 / 177,15 / 78 G06T 1 / 00,1 / 20 H04N 7/12-7/137

Claims (15)

(57) [Claims] 1. A data processor for processing data,
First, second and third memories for storing data, and first and second data for performing a predetermined operation on the data
A dedicated processing circuit, a first bus connected to the data processor and the first, second and third memories, a first data dedicated processing circuit and the first memory, and from the first memory Dedicate the data to the first data above
Second bus for transfer to the data processing circuit and the first data exclusive use
It is connected to use processing circuit and the second memory, the first de
The processed data in over data dedicated processing circuit, the first de
A third bus for transferring from over data dedicated processing circuit in the second memory, the second is connected to the memory and the second data dedicated processing circuit, de data of the second from the second memory
A fourth bus for transferring to a data dedicated processing circuit, the second data dedicated processing circuit and the third memory, and the data processed by the second data dedicated processing circuit is dedicated to the second data. A fifth bus transferring data from a processing circuit to the third memory, wherein the data processor can read data from the first, second and third memories via the first bus. Data processing system. 2. The exclusive use of the first data according to claim 1.
The data processing system is characterized in that the processing circuit is a discrete cosine transform circuit that takes in image data from the first memory, performs discrete cosine transform processing on the image data, and outputs discrete cosine transform coefficients. 3. The method of claim 1 or 2, and an instruction memory for storing instructions the data processor is to be performed, and a processing unit that performs the instructions stored in the instruction memory, the first data-only processing A data processing system, wherein the circuit performs the predetermined operation on the data of the execution result by the processing unit. 4. The first data-only processing circuit according to claim 1, wherein the first data-only processing circuit is connected in series to sequentially perform an operation on the processed data from the first memory. A data processing system including a sub-circuit of. 5. The first memory according to claim 1, wherein the first memory continuously processes the processed data .
A data processing system having a serial port for outputting to a data dedicated processing circuit. 6. The data processing circuit according to claim 1, wherein the first and second data dedicated processing circuits, the data processor, and the first, second and third memories are on a single semiconductor substrate. Is dedicated to the first and second data
The data processing system, wherein the processing circuit is individually arranged on the semiconductor substrate at a position different from that of the data processor. 7. In any of claims 1 to 6, the second memory comprises a connection between the first bus, the first selector to switch selectively the connections between the third bus, The data processing system, wherein the third memory includes a second selector that selectively switches between connection with the first bus and connection with the fifth bus . 8. The method according to claim 1, wherein the second memory includes a serial port for receiving data from the third bus and a random port connected to the first bus. Data processing system. 9. The method according to claim 1, wherein the first memory includes two memories, and when one of the two memories is connected to the first bus, the second memory is used. The other memory of the memories is connected to the second bus. 10. The method according to claim 1, wherein the second memory includes two memories, and when one of the two memories is connected to the first bus,
A data processing system, wherein the other memory of the two memories is connected to the third bus. 11. The method according to any one of claims 1 to 10,
The address signal output from the data processor is
Via the address bus, the first and second dedicated data processing
It is supplied to the sense circuit, the first and second data-only processing <br/> circuit is characterized in that it has an operating state is controlled based on the address signal supplied via address bus Data processing system. 12. The method according to any one of claims 1 to 11,
The first and second data dedicated processing circuits are configured to be electrically changeable so that the logic circuit elements of the first and second data dedicated processing circuits perform other predetermined operations. Data processing system characterized by. 13. The first and second aspects as set forth in claim 12.
The data-only processing circuit, the first and second data-only
A control port for receiving a control signal indicating whether to change the logic circuit elements use processing circuit, said data processor, to one among the first or second data dedicated processing circuit, by the control ports And a switch for selecting whether to supply an input signal from the outside of the system based on the received control signal. 14. The first memory according to claim 1, wherein the first memory stores the processed data in the first data.
A data processing system having a serial port for serial output to a dedicated processing circuit. 15. The discrete cosine transform circuit according to claim 2, wherein the discrete cosine transform circuit performs a two-dimensional discrete cosine transform by performing a one-dimensional discrete cosine transform twice, and the discrete cosine transform circuit has an input port for inputting image data. , A multiplier that multiplies the image data by a discrete cosine transform coefficient, a cumulative adder that accumulates the image data multiplied by the multiplier, and a predetermined amount of the cumulative image data that is stored as one-dimensional discrete cosine transform data The operations of the multiplier, the cumulative adder, and the memory are controlled according to an instruction from the data processor on the memory and the address bus, and the one-dimensional discrete cosine transform data stored in the memory is multiplied. Input to the cumulative adder and output to the output port of the two-dimensional discrete cosine transform data. Data processing system according to claim Mukoto.