JPS5917625A - Single-chip microcomputer - Google Patents

Abstract

PURPOSE:To reduce the load of a testing program, by connecting a testing device to a bus directly and testing a memory or an I/O device without using a CPU. CONSTITUTION:When a test terminal 210 is inactive, a CPU207 is kept at a normal processing state. When an I/O device 209 is to be tested for instance, the test terminal is activated, the CPU207 is stopped, the address signal and mode data of the I/O device 209 are inputted from an unshown testing device to a two-way address bus buffer 203 and a two-way data bus buffer 206, and then a write signal is inputted to a write signal terminal 212. Consequently, the mode data can be directly set up in the I/O device 209, and if the I/O device 209 is a measuring device, measuring data at the time of a test can be directly outputted by inputting a read signal to a read signal terminal 211.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a single-chip microcomputer in which a central processing unit, program memory, data memory, and various peripheral devices are all stored on one chip.

Conventionally, a single-chip microcomputer has a central processing unit (hereinafter referred to as CPU), a program memory, a data memory, and various peripheral devices (hereinafter referred to as 10 devices).
General-purpose LSI testers and dedicated test equipment are used to test this single-chip microcomputer, which is built into the chip. In conventional tests using these LSI testers and test equipment, a test program is executed on a microcomputer to be tested.For example, when testing a data memory among various devices built into a microcomputer, a data memory test program is executed. Mata. Testing the I10 device requires 1 step.
0 Execute a program for device testing and check the execution status of the test program and the operating status of the target device 2L
SI testers and test equipment monitor and make all pass/fail decisions.

Usually, the I10 device built into a microcomputer has various functions for the purpose of versatility.

Therefore, when testing, you must test all the functions it has.

For example, if a general-purpose counter is set at 10% I, it is necessary to test its various functions such as a pulse width measurement function, a frequency measurement function, and a rectangular wave output function. The functions of the I10 device are set by data (hereinafter referred to as mode data) stored in an accompanying function setting register (hereinafter referred to as mode register).

FIG. 1 is a block diagram for explaining a conventional single-step microconbeater testing method.

The test device 100 is an I in the microcomputer 101.
10 device 1103, test device 10
0 is mode data and other data necessary for testing @
It must be set in a register such as a mode register in the I/O device 103. However, in the conventional method, it is not possible to directly set data in the I10 device 103 from the TESH device 100, so the microcomputer 101
The CPU 102 receives data such as mode data from the test device 100 through the input terminal 104'', and all data settings are performed in the following procedure: (1) The CPU 102 receives data such as mode data from the test device 100 through the input terminal 104'', and sets the data in the device 103 under the control of the data 20PUi02.

In addition, as the I10 device 103, when testing a measuring device such as an A/D converter, the measured value total test device 1
In order to transfer the data to 00, the output terminal 105 of the microcomputer 101 had to be specially allocated for data transfer. Well, microcomputer 1
01 is frequently used for data exchange with the test equipment 100, so all terminals are specially assigned, and furthermore, a program to control this terminal, a program to set received data in a predetermined register, and a program to transfer data to the test equipment 100. In order to transfer data, it was necessary to prepare a program to read data from a specified register.

Therefore, even though the I10 device 103 is simply tested, the data transfer program and the I10
A transfer program with the device must be executed. Therefore, when testing a microcomputer, it is not a waste of time to create all of these control programs, and most of the test time is spent testing between the I10 device 103 and the test device 100 controlled by the input terminal 104. This was a major cause of increasing the total test time. TFC, there is no other way to judge the internal state of the chip by the output state from the terminal, and the number of terminals is controlled. Allocating a special allocation to the test results in a significant decrease in test efficiency.

Furthermore, the test program, including the control program for exchanging data, is written in a machine language specific to the microcombiator being tested, making it highly compatible with other microcombinators and When testing micro combinators.

A new control program had to be created in a machine language specific to the micro combinator, which required an enormous amount of time and effort. Namely.

5- In conventional testing of single-chip microcomputers, (1) despite the limited number of terminals, specific terminals must be allocated for data exchange with the test equipment; (2) the above terminals (3) A large amount of time is spent on the above-mentioned terminal control during the test, increasing the test time;
(4) There is a drawback that test programs are not compatible between different microcomputer models, and a separate test program must be created for testing different microcomputers.

The purpose of the present invention is to eliminate the above-mentioned drawbacks, to enable data exchange with other devices without setting all specific terminals, to eliminate the need for a terminal control program, to enable testing in an extremely short time, and to achieve high test efficiency. Our objective is to provide a single-chip micro combinator.

The present invention provides a single-chip microcomputer having a central processing unit, a memory, and a peripheral device, in which the central processing unit specifies an address t of another device, and data is transferred between the central processing unit and the other device. means for specifying addresses of the memory and the peripheral device from another information processing device, and a means for specifying addresses of the memory or the peripheral device specified in the other information processing device and the other information processing device; All features include means for transferring data between the two.

Next, embodiments of the present invention will be described using the drawings.

FIG. 2 is a block diagram of one embodiment of the present invention.

The microcomputer 200 has a bidirectional read/write (
read/write) control circuit 202. Bidirectional a) "L/S buffer 203. Program memo 1J for storing all programs
204. Data memory 2051 for storing calculation data
Bidirectional data bus buffer 206° central processing unit (CP)
[J)207. I10 device 209° is configured to include an internal address a and an internal data bus b2.

The bidirectional read/write control circuit 202 has a test terminal 21
The read signal and write signal output from the CPU 207 or the read signal and write signal input from the read signal terminal 211 and the write signal terminal 212 are switched according to the 00 input state, and the program memory 204, data memory 205, and I10 device are switched. 209.

When the inactive novel is input to the test terminal 210, the microcomputer J 200 is in a normal operating state. That is, the bidirectional IJ-dry drive control circuit 202 is output from the CPU 207. Read and write signals are supplied to program memory 204, data memory 205, and machine 10 device 209. The CPU 207 sequentially executes the program memories stored in the program memory 204, and executes the programs stored in the program memory 204 and the data memory 205 and l as necessary.
Outputs the address signal for the 10H position 209 onto the internal address bus a, controls read signals and write signals,
All data is transferred to and from the designated device via internal data bus a.

When single-chip microcomputer 200 accesses an externally connected program memory or data memory, it outputs the address signal on internal address bus a to external address bus 213 under the control of bidirectional read/write control circuit 202.

At the same time, the bidirectional read/write control circuit 202
CPU according to read cycle and write cycle of 07
The read signal and write signal output from 207 are output from read signal terminal 211 and write signal terminal 212 to the outside. The bidirectional data bus buffer 206 controls the external data bus 2 according to read cycles and write cycles of the CPU 207 under the control of the bidirectional read/write control circuit 202.
14 is input to internal data bus b, and data on internal data bus b is output to external data bus 214.

When an active level is input to the test terminal 210, C
The PU 207 is in a stopped state, and the bidirectional AT7 bus buffer 203 is in an input state, supplying the address signal on the external S address bus 213 to the internal address bus A. The bidirectional read/write control circuit 202 transfers read signals and write signals input from the read signal terminal 2119- and the write signal terminal 212 to the program memory 204 and the data memory 20.
5 and I10 device 209.

Under the control of the bidirectional read/write control circuit 202, the bidirectional data bus buffer 206 outputs all data on the internal data bus b to the external data bus 214 when a read signal is input, and outputs all data on the external data bus 214 when a write signal is input. Data on bus 214 is input to internal data bus b.

When testing the microcomputer 200, an active level is input to the test terminal 210, read signals and write signals are supplied from the test device 100 to the read signal terminal 211 and the write signal terminal 212, respectively, and address signals are sent to the bidirectional address bus buffer 203.
' Data from the test device 100 is supplied to the internal address bus a via the data memory 205 and the device 2.
When writing to 09, the address signals from the data memory 205 and I10 device 209 are supplied from the device 100 to the internal address bus a through the bidirectional address bus buffer 203, and the write data is A write signal is supplied to the bidirectional data bus buffer 206 from the write signal terminal 212 to the bidirectional read/write control circuit 20.
2, writing to the designated device is performed.

Data memo 1J205 from test device 100. Program memory 204. When reading data from the I10 device 209, the test device 100 supplies the address signal t'' of the device to the internal address bus a via the bidirectional address bus buffer 203, and bidirectional read signals are sent from all read signal terminals 211. Data is supplied to the write control circuit 202. In synchronization with this read signal, data is output from the device specified by the address signal onto the internal data bus b, and then output onto the external data bus 214 via the bidirectional data bus buffer 206. The test device 100 takes in the data in synchronization with the read signal.

For example, when testing l10fi location 209.

The address signals and mode data of the I10 device 209 are transferred from the test device 100 to the bidirectional address bus buffer 203.
is input to the bidirectional data bus buffer 206, and a write signal is input to the write signal terminal 212.
All mode data can be directly set in 0i location 209, I10
If the device 209 is a measuring device, the test device 1.00
By inputting the address signal of the I10 device 209 to the bidirectional address bus buffer 203 and inputting the read signal to the read signal terminal 211, 1) all measured data can be directly output from the I10 device 209 to the terminal;

As explained in detail above, the single-chip microcomputer according to the present invention can perform
It is possible to directly exchange data between the microcomputer's built-in program memory, data memory, and other equipment. Therefore, (1) there is no longer any need to specially configure specific terminals for data exchange, and (2) there are no terminal control programs or data setting programs.

No longer needed. (3) Setting the mode data and receiving the measurement data from the evaluation device is very easy and can be completed in a short time, which greatly reduces test time. (4)
) Since there is no need for programs that must be executed by the microcomputer itself, such as control programs for data exchange terminals, the problem of compatibility between different microcomputer models is solved. (5) The time spent on creating a test program for each model due to the above (4) is no longer necessary, and the time and labor required for creating the program can be significantly reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining the entire conventional testing method for a single-chip microcomputer, and FIG. 2 is a block diagram of an embodiment of the present invention. 100...Test device, 101...Microcomputer, 102...CPU, 10
3...■10 device, 104...input terminal, 105...output terminal, 200-=- microcomputer, 202...bidirectional read/write Control circuit, 203...Two-way address bus buffer, 204...Program memory, 205...Data memory 206
・River... Bidirectional data bus buffer, 2o7... Group C
P.U. 209... I10 device, 21o... Test terminal, 211... Group/read signal terminal, 212...
Old...Write signal terminal, 213...External address bus, 214...External data bus, a...
...Internal address bus, b...Internal data bus. 14-

Claims (1)

Claims: A single-chip microcomputer having a central processing unit, a memory, and peripheral devices, in which the central processing unit specifies addresses for other devices. means for transferring data between the central processing unit and the other information processing device; and means for specifying addresses of the memory and the peripheral device from the other information processing device; f: A single-chip microcomputer characterized by comprising a memory or means for transferring data between the peripheral device and the other information processing device.