JPS62192824A - Access system for processor - Google Patents

Abstract

PURPOSE:To simplify the hardware by providing an access means for a register of one processing part of plural processors, so that write and read-out can be executed directly to and from its register from other processor. CONSTITUTION:In an information processing system provided with plural processors 1, 2 the processor 2 is constituted by connecting a processing part 3, a memory part 4, a line corresponding part 5, line control mechanisms 6, 6' and an interface part 7, to an internal bus 8, and an access means 9 is provided on an interface part 7 and connected to registers 3a, 3b,... in the processing part 3. In this way, write and read-out can be executed directly to and from the registers 3a, 3b... from the processor 1, therefore, the memory part 4 can be constituted of only a RAM.

Description

[Detailed Description of the Invention] [Summary] The present invention provides an information processing system including a plurality of processing devices each operating under program control, and provides access means for the registers of the processing devices, so that access from one processing device to another processing device is provided. By directly writing to or reading from the registers, programs can be loaded and other processing devices can be diagnosed, thereby making it possible to simplify hardware.

[Industrial application field]

The present invention provides a processing device access method for loading a program from one processing device to another processing device at the initial time and for diagnosing when a failure occurs in an information processing device composed of a plurality of processing devices. It is related to.

[Conventional technology]

An example of an information processing system configured with a plurality of processing devices is one configured with a central processing unit and a peripheral control device connected to the central processing unit and having a processing section.

The programs necessary for the processing operations of this peripheral control device are stored in a read-only memory (hereinafter referred to as ROM), or have a ROM for bootstrapping, and the bootstrapping allows the program to be stored in an auxiliary storage device such as a floppy disk. It was to be loaded from.

Furthermore, when a failure occurs in a peripheral control device, etc., the conventional diagnostic method for grasping the situation is to attach a diagnostic adapter that is not required under normal conditions to the peripheral control device when necessary or in advance, and to use this adapter and a special ink cartridge. The user entered necessary troubleshooting information via the computer's interface to analyze the cause.

[Problem that the invention seeks to solve]

However, in the conventional program storage method for the peripheral control device, the program and bootstrap are stored in the RO.
With the M method, there is a problem that it is not easy to deal with because it involves rewriting or replacing the ROM when the program is revised when changing the system, and it involves attaching and detaching A-ware. Ta.

Furthermore, the conventional method for diagnosing a peripheral control device has a drawback in that the central processing unit cannot directly collect information about a failure from the peripheral control device.

Furthermore, the hardware such as the conventional bootstrap ROM, the diagnostic adapter necessary for the diagnostic method, and the dedicated ink face for that purpose are not required for normal operation and complicate the hardware. .

The present invention has been made in order to solve the above-mentioned conventional problems, and makes it possible to easily deal with program revisions in an information processing system equipped with a plurality of processing devices, and improves the failure diagnosis function. The purpose of the present invention is to reduce the amount of hardware required by eliminating the need for a program, a ROM for bootstrapping, and hardware dedicated to diagnosis.

[Means for solving problems]

As shown in the block diagram for explaining the principle of the present invention in FIG. This is a processing device access method in which a means for accessing the register 3a of the processing unit 3 is provided, and one processing device 1 can directly write to or read from the register 3a of another processing device 2. Note that the number of processing devices is not limited to the above two, and may be many.

[Effect]

By providing the processing device 2 with the access means 9,
Although the ink face between processing devices is the same as before,
For example, one processing device 1 such as a central processing unit can directly write to and read from the instruction register, data register, other harmful species control register, etc. of the processing unit 3 in the processing device 2, so the processing device 2 Even if the memory section of the computer is configured with only a random access memory (hereinafter referred to as RAM), at the initial stage, the central processing unit 1 controls the registers 3a, etc., and stores the boot program in the RAM.
can be transferred to. As a result, the processing device 2 does not need to have the program as a ROM, and can easily deal with revisions of the program. Also in diagnosis, the central processing unit 1 uses the register 3a of the processing unit 2.
Since an instruction can be written to the register 3a and the execution result can be read from the register 3a, it becomes possible to directly collect failure information, and there is no need for a diagnostic adapter or a dedicated ink face.

〔Example〕

Embodiments of the present invention will be described in detail below based on the drawings. FIG. 2 is a block diagram for explaining the present invention in detail, and FIG. 3 is a block diagram for explaining the access means.

In FIG. 2, the information processing system to which the present invention is applied is as follows:
Two processing units, namely host computers (hereinafter referred to as host CPUs)
1 and a communication control device (hereinafter referred to as CCP) 2. The CCP 2 includes a processing unit (hereinafter referred to as CC) 3 that decodes and executes processing procedures, and a memory unit (hereinafter referred to as CC) 3 that stores the processing procedures and other information.
A plurality of line control mechanisms (hereinafter referred to as MS) 4, a line corresponding unit (hereinafter referred to as LIC) 5 connected to each line and equipped with a modem, a buffer, etc., and a plurality of line control mechanisms (hereinafter referred to as LIC) that control the connection with the LIC 5 and exchange data with the CC 3. It consists of C3) 6.6' and an interface section (CA) 7 with cpUl.
, MS4. C36, 6' and CA7 are connected by an internal bus 8. This CA7 is connected to the host CPU I through a channel ink face, and to the CC3 through an internal bus 8. In addition, the CA7 is connected to an access means 9 which is a main part of the present invention, which will be described later, ie, an instruction register and a data register in the CCa. It is connected to the internal bus 8 through an ink face for interrupt control and an ink face for DMA (direct memory access) transfer. MS4 is RO
It is configured only with RAM without using M. Furthermore, host c
The channel ink face on the pui side is the same as before,
No special hardware required.

Next, according to FIG. 3, from CA7 to CC3, which are the main parts of the present invention.
The configuration of the means for accessing various registers in the system will be explained. Access means 9 is integrally provided in each of CA7 and CC3.

The CAT side includes an instruction identification register 10 that temporarily stores instructions sent from the host CPU 1 prior to data transfer.
and a decoder 1) that identifies whether it is a general instruction (conventional instruction) that uses the interface with the internal bus 8 or a special instruction that accesses the registers of CC3, and issues the necessary command; A timing generation circuit 12 that issues a read signal (read) or a write signal (write) to the register by timing the necessary transfer, and a timing adjustment circuit that temporarily stores write data from the host CPUI when writing and read data when reading. It is composed of a register 13 and the like. C.C.
The a side receives a register address signal issued from the instruction identification register 10 and decoder 1) on the CAT side, decodes it, and sends a select signal specifying the register to be read or written to the corresponding registers 3a and 3b.
, 3c, . . . address decoder 14
Consists of etc.

Each register 3a, 3b, 3c, . It is constructed so that it can be connected to the data signal line of the ink face on the means 9 side. This data signal line may be bidirectional or may be read/write separately. In the case of bidirectional operation, switching is performed using a known tri-state buffer circuit or the like.

The operation of this embodiment in the information processing system configured as above will be explained. Host C prior to data transfer.
The command output from the PUI is temporarily stored in the command identification register 10 via the channel ink face of the CA7. Subsequently, the decoder 1) identifies whether the instruction is a general instruction or a special instruction. If it is a general instruction, an interrupt is issued to CC3, the ink face of internal pass 8 is used to issue a normal data transfer request, and CC3
Data transfer processing using the internal bus 8 is performed by control over by the program in 4. If the result of the above identification is a special instruction, an interrupt is issued to the CC3, and then the instruction register 3a, data register 3b,
Other control registers 3c, etc. can be directly accessed.

It is assumed that the CC3 interrupt acceptance processing is performed by hardware rather than program control.

Describing the operation of this access means 90 in detail, first, the decoder 1) that receives a special command further identifies whether the command is a read or a write, and instructs the timing generation circuit 12. For reading, the timing generation circuit is CC
3 accepts the interrupt, confirms with the interrupt control ink face that the interrupt is enabled, and issues a read signal.

Prior to this read signal, the address decoder 1 whose register address code of the instruction identification register 10 is CC3
4, a select signal is issued to any of the registers 3a, 3b, 3c, . sends the contents of that register on the line. The timing adjustment register 1
A read data set signal is issued from the timing generation circuit to the read data register 13a of No. 3 to temporarily store this data. Thereafter, the read data of the read register 13a is transmitted to the CPU 1 using the channel ink face of the CA7 according to the normal procedure.

When the special instruction instructs writing, the timing generation circuit 12 receives an instruction from the channel interface that the next write data transmitted from the CPUI has been determined, and writes the write data register 13b of the timing adjustment register 13. A write data set signal is issued to temporarily store the write data. The write data in the write data register 13b is sent to the data signal line of the access means 9. A write signal is issued from the timing generation circuit 12 at the timing when the write data on the data signal line is determined. Prior to this write signal, the address code temporarily stored in the instruction identification register IO is input to the address decoder 14 via the register address signal line and decoded, and one register 3a to which the select signal is to be written is selected. . . . Only the register that receives this select signal accepts the write signal and writes the write data on the data signal line into that register.

As described above, from the CPUI, register 3B of CC3,
3b, 3c, etc. can be directly accessed, and this includes instruction registers, etc., so special instructions from the host 1-CPU can interrupt other processing devices and execute various instructions. can be transferred and executed.

One example of using this is to host a boot program or program for bootstrapping.
There is a method of transferring data from the PUI to the communication control device CCP 2. The CCP2 described above does not have a program or a boot program as a ROM.

Then, when the host CPUI initializes, the C
A special command for CP 2 causes the data register (3b
) is issued to the memory unit (MS4).

A series of contents transferred to this data register is a boot program for bootstrap. The above-mentioned special command is processed by the above-mentioned function of the access means 9 of the CCP 2 as follows.

+8) The special command sent by the channel ink face is temporarily stored in the command identification register 10.

(b) Since a special instruction is formatted so that, for example, one bit of its signal code is different from a general instruction, it is identified as a special instruction by the decoder 1),
Furthermore, writing is similarly identified.

(C) The register address in the special instruction in the instruction identification register IO is decoded by the address decoder 14, and a select signal is issued to the designated register.

+d) Write data sent from the channel ink face at Vt is written to the write register 13b. Note that this write data may be sent in a time-sharing manner with the special command, or may be transferred concurrently with the special command, or each bit may be serially transferred along with the special command via a line.

(G) A write signal is issued from the timing generation circuit 12, and write 1 data is written only to the register to which the select signal has been issued.

By repeating the above (al~(el), for example, the instruction register 3a stores the transfer command between the registers and memories, the data register 3b stores the data to be stored, the memory address register stores the memory address value, and other necessary information. After setting the flag to the appropriate register, set and reset the flag in the control flag register for instruction execution, and execute the instruction stored in the instruction register 3a.By repeating this, the boot program can be written from the reset start address of the MS4. When writing of this boot program is completed, a "reset start" command or special command is issued from the CPUI to start the boot program, and the CC3 receives general commands and internal bus from auxiliary memory such as a floppy disk (not shown) or from the CPU. 8, a program for communication control can be loaded.

Next, another usage example will be described. The above-mentioned information processing system does not have a diagnostic interface or adapter to simplify the hardware. Therefore, by using the above-described register reading by the special instruction, information necessary for diagnosis is directly collected when a failure occurs in the CCP2. To execute this reading, a "test" instruction is written to the register in advance and executed in the same manner as described above. If the execution result can be determined by the control flags and input/output data registers, those registers are read by a special instruction and transferred to the host CPU 1 as read data.

If the execution result is stored in the memory unit (MS4), the above reading may be performed after writing and executing a transfer command from the memory unit to the data register using a special command. By analyzing this read data, the host CPU can easily identify the part where the abnormality has occurred and understand the details of the abnormality. Since diagnostic results can be collected through test operations in this way, in this embodiment, the host CPU
And CCP 2 also eliminates the need to store extensive processing history for troubleshooting.

As an application of the above embodiment, an operational example shown in FIG. 4 is also performed. In the information processing system shown in Figure 2, C3 is used during operation.
If an abnormality occurs in C36, the processing cycle of CC3 is time-divided into a diagnostic cycle and an operation cycle as shown in Figure 4 in order to continue online operation of the device and diagnose the abnormality in C36. . Host CP during diagnostic cycle
Diagnosis is performed using special commands from the UI, and during the operation cycle, normal operation is performed using C36' according to general commands. In addition,
Needless to say, when switching between a processing cycle and a diagnostic cycle, the contents of registers and the like are saved and restored.

Although this embodiment describes an information processing system having a communication control device, the present invention is not limited to the above, and various modifications, applications, and applications are possible in accordance with the gist of the present invention.

〔Effect of the invention〕

As described above, in the information processing system according to the present invention, since the processing device is provided with means for accessing the registers of the processing unit, it is possible to directly read the registers from the outside,
As it becomes possible to write and execute instructions, it becomes possible to transfer the boot program, eliminating the need for ROM to store it in the processing unit, and when updating the program, the hardware This has the effect of making it easier to deal with the problem without having to replace it.

Additionally, during diagnostics, test instructions can be executed and the results can be collected directly, eliminating the need to store extensive processing history for troubleshooting purposes and eliminating the need for special hardware or interfaces for diagnostics. Therefore, economic effects can be obtained.

[Brief explanation of drawings]

Fig. 1 is a block diagram for explaining the principle of the present invention, Fig. 2 is a block diagram for explaining the invention in detail, Fig. 3 is a block diagram for explaining the access means, and Fig. 4 is a block diagram for explaining the operational example. It is an explanatory diagram. 1... Processing unit (central processing unit, host CPU) 2.
...Processing device (communication control device, CCP) 3...Processing section (CC) 3a, 3b, 3c...Register 4...Memory section (MS) 5...Line correspondence section (L I C) 6.6'...Line control mechanism (C3) 7...Ink face section 8...Internal bus 9...Access means 10...Register for instruction identification 1)...Decoder 12... Timing creation circuit 13...Explanatory diagram of an example of timing adjustment register operation FIG. 4

Claims (4)

[Claims] (1) Multiple processing devices each operating under program control (
1) and (2), an access means (9) for accessing the register (3a) of the processing unit (3) of the processing device (2) without being under program control of the processing device; ) and one processing device (1)
A processing device access method characterized by directly writing to or reading from a register (3a) of another processing device (2). (2) The access means (9) decodes the instruction given from the one processing device (1), and in the case of a general instruction, the access means (9) decodes the instruction to the processing unit (3) via the internal bus of the processing device (2). Claim 1, characterized in that in the case of a specific instruction that requests processing by control, the register (3a) of the processing unit (3) is directly accessed via an interface other than the internal bus. Processor access method described in . (3) The writing to the register (3a) is for loading a program from the one processing device (1) to the other processing device (2). processing unit access method. (4) Writing to or reading from the register (3a) is performed from one of the processing devices (1) to the other processing device (1).
2) The processing device access method according to claim 1, wherein the method instructs the diagnostic processing of item 2).