CN117271236A

CN117271236A - Processor for debugging CPU core by multiplexing JTAG debugging channel and application method

Info

Publication number: CN117271236A
Application number: CN202311164523.5A
Authority: CN
Inventors: 龚国辉; 刘子瑜; 伍玉良; 王永庆; 艾明哲
Original assignee: Hunan Greatwall Galaxy Technology Co ltd
Current assignee: Hunan Greatwall Galaxy Technology Co ltd
Priority date: 2023-09-08
Filing date: 2023-09-08
Publication date: 2023-12-22
Anticipated expiration: 2043-09-08
Also published as: CN117271236B

Abstract

The invention discloses a processor for multiplexing JTAG debugging channels to debug CPU cores and an application method thereof. The invention can realize the debugging of the CPU core through bus control by multiplexing JTAG debugging logic after a series of registers are configured not by configuring JTAG interfaces but by directly programming, and can support access to the private space or resource of the self-developed CPU core.

Description

Processor for debugging CPU core by multiplexing JTAG debugging channel and application method

Technical Field

The invention relates to the technical field of chip debugging, in particular to a processor for debugging a CPU core by multiplexing JTAG debugging channels and an application method.

Background

With the increase of high performance demands of applications, single-core processor chips have become increasingly unable to meet the application demands, and multi-core processor chips should be used, but whether the chips are single-core processors or multi-core processors, there may be problems in the design, manufacturing, packaging and application processes, so in order to ensure the correctness of the chips, the chips must be debugged. JTAG (Joint Test Action Group, joint test working group) interfaces are mainly used for testing the inside of chips, and most advanced devices such as DSPs, CPU IPs, FPGAs and the like support JTAG protocols, and JTAG interfaces are an integral part of SOC chips.

In the prior art, both single core processors and multi-core processors typically use a JTAG interface to access their internal circuit logic for debugging. JTAG is an International standardized protocol for chip internal debug and is IEEE1149.1 compliant, and a standard JTAG interface typically has 5 signals, respectively: reset signal TRST, mode select signal TMS, clock signal TCK, data input signal TDI and data output signal TDO. The basic principle of debugging a chip by JTAG is that a test access port TAP (Test Access Port) is defined and realized in the chip, and a JTAG simulator tests the inside of the chip through the test access port TAP.

The chinese patent document with publication number CN101154184a discloses a prior art for debugging a microprocessor through a JTAG interface, and although the debugging method introduced in the prior art is that the object of debugging through the JTAG interface is a microprocessor, the prior art only embodies a basic method for debugging a single processor through the JTAG interface: the JTAG interface is configured, and the external upper software is utilized to access the simulation debugging module by using a standard or extended standard TAP command, so that the debugging command is executed, and the purpose of debugging is achieved.

For heterogeneous multi-core processors, since the heterogeneous multi-core processors comprise a plurality of single-core processors such as CPUs and/or DSPs, each single-core processor is provided with a debugging access port TAP belonging to the single-core processor, and the single-core processors are connected through a peripheral logic circuit, so that joint debugging of the multi-core processors is complicated. In the prior art, there is a method for debugging a multi-core processor in a serial manner, where the multi-core processor includes a plurality of processor cores (also called IP cores), and each processor core is provided with a test access port TAP belonging to itself. The test access ports TAP of the processor cores adopt a daisy-chained connection mode, namely, a data output signal TDO of the upper-stage test access port TAP is accessed to a data input signal TDI of the lower-stage test access port TAP, and a clock signal TCK, a mode selection signal TMS and a reset signal TRST of the JTAG simulator are accessed to all TAPs.

The chinese patent publication No. CN102103535a discloses a prior art technique for implementing debugging of a multiprocessor through a single JTAG interface through a chip-level TAP and other supporting modules. Although the method skillfully realizes the debugging method of the multi-core processor through a single JTAG interface by adding the TAP of one chip and other supporting modules under the condition of not changing the standard TAP interface and the standard simulator port design.

However, whether the multi-core processor is debugged by adopting a JTAP serial mode or a parallel mode, the main idea is still: the simulation debugging module is accessed by using standard or extended standard TAP commands through configuring JTAG interface and utilizing external upper software, and the processor core to be tested is selected and the debugging command is executed, so that the purpose of debugging is achieved. However, in the event that the JTAG interface is not available or has other uses, debugging of the multi-core processor cannot be achieved. Moreover, when CPU cores of different architectures are integrated in heterogeneous multi-core SOC chips, these heterogeneous CPU cores typically only can access the addressable space on the chip and the respective internal private spaces or resources (including private memory, register file, control register, PC pointer, etc.), but cannot access the private spaces or resources of other cores (including private memory, register file, control register, PC pointer, etc.), let alone control the running, suspension, and single-step of the instruction pipeline in the core.

Disclosure of Invention

The invention aims to solve the technical problems: aiming at the problems in the prior art, the invention provides a processor for debugging a CPU core by multiplexing JTAG debugging channels and an application method thereof.

In order to solve the technical problems, the invention adopts the following technical scheme:

the processor comprises a JTAG interface, a simulation debugging module, a configuration bus, an on-chip host module and a CPU core, wherein the JTAG interface is connected with the simulation debugging module, the simulation debugging module is connected with the on-chip host module through the configuration bus, the simulation debugging module is connected with the CPU core through a data bus, the configuration bus comprises a host interface for accessing the simulation debugging module, the simulation debugging module comprises a slave interface connected with the host interface and a corresponding decoding module for being accessed by the on-chip host module, and the simulation debugging module further comprises a group of registers and selectors for realizing multiplexing control of the JTAG interface and the on-chip host module on the simulation debugging module.

Optionally, the registers in the set of registers and selectors comprise:

an enable register PE for representing global enable of on-chip host module debugging;

a selection register PJ for representing the channel occupation states of JTAG debugging and on-chip host module debugging;

the debug instruction register is used for storing debug instructions;

the debugging data register is used for storing debugging data;

and the state register is used for storing the debugging state.

Optionally, the enable register PE includes a first enable register PE1 and a second enable register PE2, where the first enable register PE1 and the second enable register PE2 are used to represent global enabling of other host debug, and the on-chip host module is allowed to implement a debug function for the CPU core and access a private space or resource of the CPU core by using the register and the selector multiplexing emulation debug module only when the first enable register PE1 is equal to a first set value and the second enable register PE2 is equal to a second set value.

Optionally, the debug instruction register includes a debug instruction register 0 and a debug instruction register 1, the debug instruction register 0 is used for storing the low 32 bits of the debug instruction, and the debug instruction register 1 is used for storing the high 16 bits of the debug instruction; the status register comprises a status register 0 and a status register 1, wherein the status register 0 is used for storing the low 32 bits of the debugging state, and the status register 1 is used for storing the high 16 bits of the debugging state.

Optionally, the set of registers and selectors comprises: a first selector for selecting whether to write the debug instruction through the configuration slave interface or scan the debug instruction through the JTAG interface by the on-chip host module; a second selector for selecting whether to return the collected state to the JTAG interface or to generate the on-chip host module of the debug request; a third selector for selecting whether to return the collected state to the JTAG interface or to generate the on-chip host module of the debug request; and a fourth selector for selecting whether to write or scan debug data through the configuration slave interface or through the JTAG interface by the on-chip host module.

Optionally, the coding module includes: the simple decoding module is used for decoding the instruction latched in the instruction register under the TCK clock domain in the simulation debugging module to generate access control signals for the enable register PE, the select register PJ and the instruction register under the system clock domain in the simulation debugging module; and the configuration bus slave interface register decoding module is used for decoding the bus request generated by the on-chip host module to generate access control signals for an enable register PE, a selection register PJ and an instruction register and a data register in a system clock domain in the emulation debugging module.

Optionally, the number of the CPU cores is a plurality.

In addition, the invention also provides a computer device which comprises a microprocessor and a memory which are connected with each other, wherein the microprocessor is a processor for debugging a CPU core by the multiplexing JTAG debugging channel.

In addition, the invention also provides an application method of the processor for debugging the CPU core by multiplexing JTAG debugging channels, which comprises the following steps:

s101, turning on debugging enabling: configuring a first enabling register PE1 to enable to be opened and writing a first set value into the first enabling register PE1, configuring a second enabling register PE2 to enable to be opened and writing a second set value into the second enabling register PE2, and jumping to the step S102 if the first enabling register PE1 is equal to the first set value and the second enabling register PE2 is equal to the second set value and the second set value is simultaneously established;

s102, realizing the designated debugging function of the designated CPU core or accessing the private space or resource of the designated CPU core by using the register and the selector multiplexing simulation debugging module through the on-chip host module without using the JTAG interface, comprising: continuously reading the state of the selection register PJ, waiting for the value of the selection register PJ to be changed into 01, wherein when the value of the selection register PJ is changed into 01, the on-chip host module occupies a JTAG debugging channel, and after the value of the selection register PJ is changed into 01, writing a debugging command into a debugging instruction register 0 and a debugging instruction register 1 and writing debugging data into a debugging data register according to the debugging operation of pipeline suspension required to be executed by the on-chip host module aiming at a designated CPU core; then reading the state register 0 and the state register 1 to obtain debugging states and debugging data so as to judge whether the designated CPU core passes the debugging or whether the private space or the resource of the designated CPU core is accessed successfully;

S103, turning off debugging enabling: the first enable register PE1 is configured to enable shutdown and write all 0 s thereto, and the second enable register PE2 is configured to enable shutdown and write all 0 s thereto.

Optionally, the designated debug function in step S102 includes controlling a designated CPU core execution pipeline to halt, controlling a designated CPU core pipeline to single step, and controlling some or all of the designated CPU core pipeline operations;

the control-specified CPU core execution pipeline suspension includes: continuously reading the state of the selection register PJ, waiting for the value of the selection register PJ to be changed into 01, wherein when the value of the selection register PJ is changed into 01, the on-chip host module occupies a JTAG debugging channel, and after the value of the selection register PJ is changed into 01, writing a debugging command into a debugging instruction register 0 and a debugging instruction register 1 and writing debugging data into a debugging data register according to the debugging operation of pipeline suspension required to be executed by the on-chip host module aiming at a designated CPU core; then reading the state register 0 and the state register 1 to obtain debugging states and debugging data so as to judge whether the appointed CPU core passes the debugging, if the appointed CPU core execution pipeline is judged to be paused according to the debugging states and the debugging data and a program counter PC pointer is not moved, judging that the appointed CPU core execution pipeline pauses the debugging to pass, otherwise, judging that the appointed CPU core execution pipeline pauses the debugging to not pass; releasing JTAG debugging channel, writing all 0 to the selection register PJ;

The control-specified CPU core pipeline single step includes: continuously reading the state of the selection register PJ, waiting for the value of the selection register PJ to be changed into 01, and writing a debugging command into the debugging instruction register 0 and the debugging instruction register 1 and writing debugging data into the debugging data register according to the single step debugging operation of the pipeline required to be executed by the on-chip host module aiming at the appointed CPU core after the value of the selection register PJ is changed into 01; then reading the state register 0 and the state register 1 to obtain debugging states and debugging data so as to judge whether the appointed CPU core passes the debugging, if the appointed CPU core execution pipeline is judged to be paused and the program counter PC pointer walks one beat according to the debugging states and the debugging data, judging that the appointed CPU core execution pipeline single step passes the debugging, otherwise, judging that the appointed CPU core execution pipeline single step does not pass the debugging; releasing JTAG debugging channel, writing all 0 to the selection register PJ;

the control-specified CPU core pipeline operation includes: continuously reading the state of the selection register PJ, waiting for the value of the selection register PJ to be changed into 01, and writing a debugging command into the debugging instruction register 0 and the debugging instruction register 1 and writing debugging data into the debugging data register according to the debugging operation of the on-chip host module aiming at the pipeline operation required to be executed by the appointed CPU core after the value of the selection register PJ is changed into 01; then reading the state register 0 and the state register 1 to obtain debugging states and debugging data so as to judge whether the designated CPU core passes the debugging; the JTAG debug channel is released, and all 0 s are written to the select register PJ.

Optionally, accessing the private space or the resource of the specified CPU core in step S102 includes reading the on-chip general register of the specified CPU core, writing the on-chip general register of the specified CPU core, reading the specified on-chip and off-chip resources, writing the specified on-chip and off-chip resources, reading the on-chip storage, writing part or all of the on-chip storage;

the reading the on-chip general purpose registers of the specified CPU core includes: continuously reading the state of the selection register PJ, waiting for the value of the selection register PJ to be changed into 01, and writing a debugging command into a debugging instruction register 0 and a debugging instruction register 1 and writing debugging data into a debugging data register according to the debugging operation of the on-chip host module for reading the on-chip general register of the appointed CPU core, which is required to be executed by the appointed CPU core, after the value of the selection register PJ is changed into 01; then reading the state register 0 and the state register 1 to obtain debugging states and debugging data so as to judge whether the access to the on-chip general purpose registers of the CPU core appointed by reading is successful or not; releasing JTAG debugging channel, writing all 0 to the selection register PJ;

the writing of the on-chip general purpose registers of the specified CPU core includes: continuously reading the state of the selection register PJ, waiting for the value of the selection register PJ to be changed into 01, and writing a debugging command into the debugging instruction register 0 and the debugging instruction register 1 and writing debugging data into the debugging data register according to the debugging operation of the on-chip host module for writing the on-chip general register of the appointed CPU core, which is required to be executed by the appointed CPU core, after the value of the selection register PJ is changed into 01; then reading the state register 0 and the state register 1 to obtain debugging states and debugging data so as to judge whether the writing of the on-chip general purpose registers of the appointed CPU core is successful or not; releasing JTAG debugging channel, writing all 0 to the selection register PJ;

The read-specified on-chip and off-chip set resources include: continuously reading the state of the selection register PJ, waiting for the value of the selection register PJ to be changed into 01, and writing a debugging command into the debugging instruction register 0 and the debugging instruction register 1 and writing debugging data into the debugging data register according to the debugging operation of the on-chip host module for reading the appointed on-chip external resources, which is required to be executed by the appointed CPU core, after the value of the selection register PJ is changed into 01; then reading the state register 0 and the state register 1 to obtain debugging states and debugging data so as to judge whether accessing the on-chip and off-chip resources specified by reading is successful or not; releasing JTAG debugging channel, writing all 0 to the selection register PJ;

the write-designated on-chip and off-chip set resources include: continuously reading the state of the selection register PJ, waiting for the value of the selection register PJ to be changed into 01, and writing a debugging command into the debugging instruction register 0 and the debugging instruction register 1 and writing debugging data into the debugging data register according to the debugging operation of the on-chip host module for writing the appointed on-chip internal and external resources required to be executed by the appointed CPU core after the value of the selection register PJ is changed into 01; then reading the state register 0 and the state register 1 to obtain debugging states and debugging data so as to judge whether writing of the specified on-chip and off-chip resources is successful or not; releasing JTAG debugging channel, writing all 0 to the selection register PJ;

The on-chip storage includes: continuously reading the state of the selection register PJ, waiting for the value of the selection register PJ to be changed into 01, and writing a debug command into a debug instruction register 0 and a debug instruction register 1 and writing debug data into a debug data register according to the debug operation stored on a read chip required to be executed by the on-chip host module aiming at a specified CPU core after the value of the selection register PJ is changed into 01; then reading the state register 0 and the state register 1 to obtain debugging states and debugging data so as to judge whether the on-chip storage is successful or not; releasing JTAG debugging channel, writing all 0 to the selection register PJ;

the on-write-chip storage includes: continuously reading the state of the selection register PJ, waiting for the value of the selection register PJ to be changed into 01, and writing a debug command into a debug instruction register 0 and a debug instruction register 1 and writing debug data into a debug data register according to the debug operation stored on a write chip required to be executed by the on-chip host module aiming at a specified CPU core after the value of the selection register PJ is changed into 01; then reading the state register 0 and the state register 1 to obtain debugging states and debugging data so as to judge whether the on-chip storage is successful or not; the JTAG debug channel is released, and all 0 s are written to the select register PJ.

Compared with the prior art, the invention has the following advantages:

1. The invention comprises a host interface for accessing the simulation debugging module, the simulation debugging module comprises a slave interface connected with the host interface and a corresponding decoding module for being accessed by the on-chip host module, and a group of registers and selectors for realizing multiplexing control of the JTAG interface and the on-chip host module to the simulation debugging module.

2. The simulation debugging module also comprises a group of registers and a selector for realizing multiplexing control of the JTAG interface and the on-chip host module on the simulation debugging module, so that the on-chip host module accesses the private space or resource of the self-developed CPU core through the bus control multiplexing JTAG debugging channel after passing through the register configured by the program.

3. The invention makes redundant design for the processor to debug the function, and the use is more flexible and convenient.

Drawings

FIG. 1 is a schematic diagram of a processor according to an embodiment of the invention.

Fig. 2 is a schematic structural diagram of a simulation debugging module in an embodiment of the present invention.

Fig. 3 is a flowchart of an application method of a processor in an embodiment of the invention.

Detailed Description

As shown in fig. 1, the processor for debugging the CPU core through the multiplexing JTAG debug channel of the present embodiment includes a JTAG interface, a simulation debug module, a configuration bus, an on-chip host module, and a CPU core, where the JTAG interface is connected to the simulation debug module, the simulation debug module is connected to the on-chip host module (shown as other hosts in fig. 1) through the configuration bus, the simulation debug module is connected to the CPU core through the data bus, the configuration bus includes a host interface (shown as a in fig. 1) for accessing the simulation debug module, the simulation debug module includes a slave interface (shown as b in fig. 1) connected to the host interface and a corresponding decoding module for being accessed by the on-chip host module, and the simulation debug module further includes a set of registers and selectors for implementing multiplexing control of the simulation debug module by the JTAG interface and the on-chip host module, and implementing a debug function for the CPU core and a private space or resource for accessing the CPU core by multiplexing the simulation debug module by the on-chip host module without using the on-chip host module. Referring to fig. 1, in this embodiment, the on-chip and off-chip resources include a low-speed peripheral (low-speed peripheral 1 to low-speed peripheral m) and a high-speed peripheral (high-speed peripheral 1 to high-speed peripheral n) which are mounted on a configuration bus, and on-chip storage and mounting on a data bus, according to the characteristics of access speeds thereof. The number of CPU cores is plural, and is denoted as self-grinding CPU0 and self-grinding CPU1, and it should be noted that the number of CPU cores may be one or plural, and that "self-grinding" in the self-grinding CPU0 and self-grinding CPU1 merely indicates that the CPU core is a CPU core as a debug target, and should not be construed as depending on a specific CPU model or instruction set architecture. In developing a CPU core, the on-chip host module generally adopts a mature CPU core, so that the on-chip host module and the CPU core in fig. 1 can be of different CPU models or instruction set architectures. The thick solid line in fig. 1 represents the master-slave control relationship between the master interface and the slave interface. When the chip is debugged through the JTAG interface, the simulation debugging module analyzes the debugging signals which are fed in from the JTAG interface and accord with the JTAG protocol, latches and decodes the test and debugging instructions, so that the JTAG interface signals are converted into bus control signals which can be accessed from ports of the module to be accessed (such as a CPU core, on-chip and off-chip built-in resources, on-chip storage and the like), and the internal logic of the chip is debugged. Meanwhile, a host interface of a simulation debugging module is added in the configuration bus, and a slave interface and a corresponding decoding module are added in the simulation debugging module, so that the debugging function of the internal logic of the chip can be realized by controlling the simulation debugging module through the bus by other hosts, and the redundancy design is carried out on the debugging function, so that not only can the chip be debugged through the JTAG interface, but also the other hosts can be enabled to configure a series of registers through the bus to realize the debugging function of the internal logic of the chip. In the prior art, only the function of debugging the chip through the JTAG interface is basically realized. In this embodiment, a part of JTAG debug logic is multiplexed through a redundancy design for the debug function of the chip, so that the heterogeneous CPU cores can be used as hosts to access the addressable space on the chip and the private space or resource of the self-grinding CPU core through multiplexing the JTAG debug channel after a series of registers are configured by the program, and when other heterogeneous CPU cores are used as debug hosts, the private space or resource of the self-grinding CPU core can be accessed through the program after a series of registers are configured by the program. In the prior art, in order to access the private space or resource of the self-developed CPU core, a new complex logic is required to convert the private space or resource into an addressable space for access.

Fig. 2 is a schematic structural diagram of a simulation debugging module in this embodiment, in which a part without a bold identifier represents a structural part of an original chip debugging through JTAG, and a part with a bold identifier represents newly added logic based on an original debugging scheme to support other hosts to realize a debugging function of internal logic through a bus control simulation debugging module. In fig. 2, a configuration bus is designed with a plurality of configuration network hosts and slaves; a plurality of data network hosts and slaves are also designed in the data network. ETC_TCK is the core control unit of the emulation debugging unit, and specific functions are: providing a TAP state machine, an instruction register JIR and a test data register compatible with JTAG standard; the instructions and data serially scanned in from the JTAG interface are latched into instruction registers (48 b) and data registers (16 b) under the control of the TAP state machine under the TCK clock domain, where b represents a bit. Etc_clk is an access debug feature decode portion, and specific functions are: the clock domain crossing conversion is responsible for the simulation debugging component to access other resources of the chip; decoding the scanned JTAG instruction and data to generate a bus request corresponding to access operation (the simulation debugging component accesses kernel data, the simulation debugging component controls a kernel pipeline, the simulation debugging component accesses addressable space such as on-chip storage, on-chip and off-chip resources and the like); collecting summarized access state information and returning.

Referring to fig. 2, the registers in the set of registers and the selector in the present embodiment include:

the debug instruction register is used for storing debug instructions;

the debugging data register is used for storing debugging data;

and the state register is used for storing the debugging state.

As an optional implementation manner, the enabling register PE in this embodiment includes a first enabling register PE1 and a second enabling register PE2, where the first enabling register PE1 and the second enabling register PE2 are used to represent global enabling of other host debug, and only when the first enabling register PE1 is equal to a first set value (denoted as a specific value 1) and the second enabling register PE2 is equal to a second set value (denoted as a specific value 2) and are simultaneously established, the on-chip host module is allowed to implement a debug function on the CPU core and access a private space or resource of the CPU core by using the register and the selector multiplexing emulation debug module.

In this embodiment, the first enable register PE1 is 32 bits valid, readable and writable, and the default value is all 0; when the written value matching is valid, the global enabling of other host debugging is ready to be opened, and a second enabling register PE2 is further configured in sequence when the global enabling is truly opened; when other hosts independently debug the self-grinding CPU, the enabling is closed, and the previous debugging state is cleared; in the starting process of JTAG debugging, the debugging state of other hosts is also forced to be cleared; the default values 31b:0b of the first enable register PE1 are all 0, with a value of 1 being a particular value, 1 on enable, and 32' h0 off enable.

In this embodiment, the second enable register PE2 is 32 bits valid, readable and writable, and the default value is all 0; when the write-in value matching is valid, the global enabling of other host debugging is ready to be opened, and the real opening is needed to be completed by configuring PE1 last time; when other hosts independently debug the self-grinding CPU, the enabling is closed, and the previous debugging state is cleared; in the starting process of JTAG debugging, the debugging state of other hosts is also forced to be cleared; the second enable register PE231b, 0b default to all 0, has a value of a particular value 2 open enable and a value of 32' h0 closed enable.

In this embodiment, the select register PJ represents a channel occupation representation of JTAG debug and other host debug, and the register 2 bits are valid, readable and writable, and the default value of 00 is not 00. This register can be correctly read and written by other hosts only after the debug enable of the PE register is turned on. A value of 00 indicates that the channel is idle, and JTAG and ARM core debugging can be occupied; a value of 01 indicates that other host debugging is in progress, and JTAG debugging cannot issue a debug command; a value of 10 indicates that JTAG debug is in progress, when other debug cannot issue debug commands. The design of the select register PJ is similar to a signal lamp mechanism, so that JTAG and other hosts can compete for access, and before issuing a debug atomic operation command, all the 2 interfaces should first read the value of the register to determine whether to issue their own debug command later, and the debug atomic operation command refers to a complete user-operable debug command, such as reading or writing a register once, reading or writing a memory space once, single-step, setting a breakpoint, etc. Reading the PJ register once causes the debug channel to be occupied by the interface at all times, and thus, after a debug atomic operation command is completed, the channel is released, i.e. 00 is written to the PJ register. 1b:0b is defined as follows: 00: default values, indicating idle state, are available for debugging by both JTAG and other hosts. 10: indicating that JTAG debug is in progress, at which time other hosts cannot issue debug commands. 01: indicating that other host debugging is in progress, JTAG cannot issue debug commands at this time.

The debug instruction register in this embodiment includes a debug instruction register 0 and a debug instruction register 1, the debug instruction register 0 is used for storing the low 32 bits of the debug instruction, and the debug instruction register 1 is used for storing the high 16 bits of the debug instruction; specifically, the debug instruction register 0 in this embodiment is the lower 32 bits 31b:0b of the 48-bit debug instruction register, which is writable and readable. The debug instruction register 1 is the upper 16 bits 15b:0b of the 48-bit debug instruction register, can be written and read, and after the debug instruction register 1 is written, the 48-bit debug instruction register data starts to take effect, and the 31b:16b of the 48-bit debug instruction register is reserved and is read only.

In this embodiment, the debug data register is a 16-bit debug data register 15b:0b, which is writable and readable, and forms a 32-bit debug data register together with the reserved, read-only space of the adjacent 31 b:16b.

In this embodiment, the status register includes a status register 0 and a status register 1, where the status register 0 is used for storing the lower 32 bits of the debug status, and the status register 1 is used for storing the upper 16 bits of the debug status. Status register 0 is the lower 32 bits 31b:0b of the 48-bit status register, read only, typically the data returned by a read command. The state register 1 is the upper 16 bits 15b:0b of the 48-bit state register, and is read-only; 31b, 16b, read only is typically the state returned by the read command.

The state returned by the read command is defined as follows:

15b:12 b-reserved;

11b-Cache dirty marks;

10 b-full chip reset indication;

9 b-reset flag;

8 b-marking the value missing of the pipeline execution station;

7b-L1P value absence indication;

6b-L1D value absence indication;

5 b-writing a data valid mark;

4 b-indicating the valid read data;

3 b-pipeline halt indication;

2 b-software breakpoint indication

1b-Cache data effective marking;

0 b-hardware breakpoint indication.

The definition of each register in this embodiment is summarized in table 1.

Table 1: register definition table.

Offset address of register	Number of bits of register	Meaning of register
			0000	32	First enable register PE1
0004	2	Select register PJ
			0008	32	Second enable register PE2
0010	32	Debug instruction register 0
			0014	32	Debug instruction register 1
0018	32	Debugging data register
			0020	32	Status register 0
0024	32	Status register 1

The selector of the set of registers and selectors in this embodiment includes: a first selector (denoted "select 1" in FIG. 2) for selecting whether debug instructions are written by the on-chip host module through the configuration slave interface or scanned through the JTAG interface; a second selector (denoted "select 2" in fig. 2) for selecting whether to return the collected state to the JTAG interface or to the on-chip host module that generated the debug request; a third selector (denoted "select 3" in fig. 2) for selecting whether to return the collected state to the JTAG interface or to the on-chip host module that generated the debug request; a fourth selector (denoted "select 4" in fig. 2) is used to select whether debug data is written by the on-chip host module through the configuration slave interface or scanned through the JTAG interface.

Referring to fig. 2, the decoding module in this embodiment includes: the simple decoding module is used for decoding the instruction latched in the instruction register under the TCK clock domain in the simulation debugging module to generate access control signals for the enable register PE, the select register PJ and the instruction register under the system clock domain in the simulation debugging module; and the configuration bus slave interface register decoding module is used for decoding the bus request generated by the on-chip host module to generate access control signals for an enable register PE, a selection register PJ and an instruction register and a data register in a system clock domain in the emulation debugging module.

In summary, in the case that the JTAG interface is unavailable or has other uses, the processor of the present embodiment that multiplexes the JTAG debug channel to debug the CPU core provides a debug function for the self-developed CPU core that can be implemented by multiplexing the JTAG debug logic through bus control after other hosts configure a series of registers through programs. When the heterogeneous multi-core SOC chip integrates CPU cores of different architectures, generally, the heterogeneous CPU cores can only access an addressable space on the chip and respective internal private spaces or resources (including private memory, register file, control register, PC pointer, etc.), but cannot access private spaces or resources of other cores (including private memory, register file, control register, PC pointer, etc.), so to speak, the processor controlling the operation of the instruction pipeline in the core, suspending and single-step multiplexing JTAG debug channel debugging CPU core of the present embodiment can utilize the on-chip host module to access the private spaces or resources of the self-developed CPU core through the bus control multiplexing JTAG debug channel after configuring a series of registers through a program. The processor of the CPU core debugged by multiplexing the JTAG debugging channel of the embodiment can debug the chip by configuring the JTAG interface, and can also directly configure a series of registers by programming through other hosts and then multiplex a part of debugging logic of JTAG, and realize the scheme of debugging the self-grinding CPU core by other hosts through bus control, so that under the condition that the JTAG interface is unavailable or has other purposes, other hosts can solve the chip debugging problem by configuring the registers and the like, and simultaneously provide access to the private resources of the chip, such as the access of general registers, control registers and the like in the kernel, and the debugging functions can be realized by: (1) The internal private resources can be accessed, including register files, control registers, PC pointers and the like; (2) Controlling a core pipeline, including run, pause and single step; (3) accessing other addressable spaces.

In addition, the embodiment also provides a computer device, which comprises a microprocessor and a memory which are connected with each other, wherein the microprocessor is a processor for debugging a CPU core by multiplexing JTAG debugging channels.

As shown in fig. 3, this embodiment further provides an application method of the processor for debugging the CPU core by multiplexing the JTAG debug channel, including:

s101, turning on debugging enabling: configuring a first enabling register PE1 to enable to be opened and writing a first set value (a specific value 1) into the first enabling register PE1, configuring a second enabling register PE2 to enable to be opened and writing a second set value (a specific value 2) into the second enabling register PE2, and jumping to the step S102 if the first enabling register PE1 is equal to the first set value and the second enabling register PE2 is equal to the second set value and simultaneously established; in this embodiment, the base address of the debug related register is 0x01EC00000, the PE1 register (0 x01EC 0000) is first configured to be enabled to be turned on, the specific value 1 is written thereto, and then the PE2 register (0 x01EC 0008) is configured to be enabled to be turned on, the specific value 2 is written thereto. At this time, the debug enable of other hosts is turned on, and if the debug enable is not turned off after one operation is completed, the debug enable is not required to be turned on again. The write configuration of other registers cannot be inserted between the configuration of the registers, otherwise, the enabling opening process is interrupted, and the configuration needs to be reconfigured in sequence after the interruption.

s103, turning off debugging enabling: the first enable register PE1 is configured to enable shutdown and write all 0 s thereto, and the second enable register PE2 is configured to enable shutdown and write all 0 s thereto. Specifically, in this embodiment, the PE1 register (0 x01EC 0000) is first configured to enable shutdown, all 0 s are written thereto, and then the PE2 register (0 x01EC 0008) is configured to enable shutdown, all 0 s are written thereto. At this point the processor's debug enable is turned off. The write configuration of other registers cannot be inserted between the configuration of the registers, otherwise, the enabling shutdown process is interrupted, and the configuration needs to be reconfigured in sequence after the interruption.

The designated debug function in step S102 includes controlling the designated CPU core execution pipeline to halt, controlling the designated CPU core pipeline to single step, and controlling some or all of the designated CPU core pipeline operations; the accessing the private space or the resource of the specified CPU core in step S102 includes reading the on-chip general register of the specified CPU core, writing the on-chip general register of the specified CPU core, reading the specified on-chip resources, writing the specified on-chip resources, reading the on-chip storage, writing part or all of the on-chip storage.

Wherein controlling the specified CPU core execution pipeline to halt includes: continuously reading the state of the selection register PJ, waiting for the value of the selection register PJ to be changed into 01, wherein when the value of the selection register PJ is changed into 01, the on-chip host module occupies a JTAG debugging channel, and after the value of the selection register PJ is changed into 01, writing a debugging command into a debugging instruction register 0 and a debugging instruction register 1 and writing debugging data into a debugging data register according to the debugging operation of pipeline suspension required to be executed by the on-chip host module aiming at a designated CPU core; then reading the state register 0 and the state register 1 to obtain debugging states and debugging data so as to judge whether the appointed CPU core passes the debugging, if the appointed CPU core execution pipeline is judged to be paused according to the debugging states and the debugging data and a program counter PC pointer is not moved, judging that the appointed CPU core execution pipeline pauses the debugging to pass, otherwise, judging that the appointed CPU core execution pipeline pauses the debugging to not pass; releasing JTAG debugging channel, writing all 0 to the selection register PJ; specifically, the embodiment includes continuously reading the state of the PJ register (0 x01EC 0004), waiting for its value to become 01, indicating that other hosts occupy the debug channel; writing 0 xffffffffff to debug instruction register 0 (0 x01EC 0010); write 0x00002480 to debug instruction register 1 (0 x01EC 0014) (if the controlling core is self-grinding CPU1, the write value is 0x00002481, the following); writing 000020a8 to the debug data register (0 x01EC 0018); writing 0 xffffffffff to debug instruction register 0 (0 x01EC 0010); write 0x00002880 to debug instruction register 1 (0 x01EC 0014) (if the controlling core is self-grinding CPU1, the write value is 0x00002881, the following); status register 1 (0 x01EC 0024) is read waiting for the pipeline stall flag to be active, indicating that the pipeline has been stalled. The PC pointer of the self-grinding CPU0 can be observed to be stationary. The debug channel is released and all 0 s are written to the PJ register (0 x01EC 0004). (it may not be necessary to release each operation, and it may be released after multiple operations). In read status register 1 (0 x01EC 0024), bit 3 is used as a wait pipeline stall flag, and if bit 3 is valid, it indicates that the pipeline has been stalled. The meaning of the bits in the status register 1 (0 x01EC 0024) is as follows:

Reserved bits, read-only;

reserved bits, read-only;

[11] the dirty mark of the Cache, indicate the data in the Cache is dirty;

[10] a full chip reset mark, which indicates that on-chip resources including CPU cores are reset;

[9] reset indication, which indicates the CPU core reset;

[8] the value missing mark of the pipeline execution station indicates that the missing of operands and the like occurs when the execution station executes the instruction;

[7] L1P value missing marks which indicate that instruction missing occurs in primary program storage;

[6] L1D value missing marks which indicate that data missing occurs in primary data storage;

[5]: the written data valid mark indicates that the data written by the debugging channel is valid;

[4] the effective indication of the read data indicates that the data read by the debugging channel is effective;

[3] a pipeline pause mark, which indicates that the pipeline is paused;

[2] a software breakpoint mark, which indicates that a software breakpoint is set for a program;

[1] the effective mark of the data of the Cache, represent the data in the Cache are valid;

[0] hardware breakpoint indication, which indicates that a hardware breakpoint is set for a program.

Controlling the specified CPU core pipeline single step includes: continuously reading the state of the selection register PJ, waiting for the value of the selection register PJ to be changed into 01, and writing a debugging command into the debugging instruction register 0 and the debugging instruction register 1 and writing debugging data into the debugging data register according to the single step debugging operation of the pipeline required to be executed by the on-chip host module aiming at the appointed CPU core after the value of the selection register PJ is changed into 01; then reading the state register 0 and the state register 1 to obtain debugging states and debugging data so as to judge whether the appointed CPU core passes the debugging, if the appointed CPU core execution pipeline is judged to be paused and the program counter PC pointer walks one beat according to the debugging states and the debugging data, judging that the appointed CPU core execution pipeline single step passes the debugging, otherwise, judging that the appointed CPU core execution pipeline single step does not pass the debugging; releasing JTAG debugging channel, writing all 0 to the selection register PJ; specifically, the embodiment includes continuously reading the state of the PJ register (0 x01EC 0004), waiting for its value to become 01, indicating that other hosts occupy the debug channel; writing 0 xffffffffff to debug instruction register 0 (0 x01EC 0010); write 0x00002480 to debug instruction register 1 (0 x01EC 0014); 000020ea is written to the debug data register (0 x01EC 0018); writing 0 xffffffffff to debug instruction register 0 (0 x01EC 0010); write 0x00002880 to debug instruction register 1 (0 x01EC 0014); status register 1 (0 x01EC 0024) is read waiting for the pipeline stall flag to be active, indicating that the pipeline has been stalled. One beat of the PC pointer from the lapping CPU0 can be observed. The debug channel is released and all 0 s are written to the PJ register (0 x01EC 0004) (it may not be released every operation, it may be released after multiple operations).

Controlling the specified CPU core pipeline operation includes: continuously reading the state of the selection register PJ, waiting for the value of the selection register PJ to be changed into 01, and writing a debugging command into the debugging instruction register 0 and the debugging instruction register 1 and writing debugging data into the debugging data register according to the debugging operation of the on-chip host module aiming at the pipeline operation required to be executed by the appointed CPU core after the value of the selection register PJ is changed into 01; then reading the state register 0 and the state register 1 to obtain debugging states and debugging data so as to judge whether the designated CPU core passes the debugging; releasing JTAG debugging channel, writing all 0 to the selection register PJ; specifically, the embodiment includes continuously reading the state of the PJ register (0 x01EC 0004), waiting for its value to become 01, indicating that other hosts occupy the debug channel; writing 0 xffffffffff to debug instruction register 0 (0 x01EC 0010); write 0x00002480 to debug instruction register 1 (0 x01EC 0014); 000020d0 is written to the debug data register (0 x01EC 0018); writing 0 xffffffffff to debug instruction register 0 (0 x01EC 0010); write 0x00002880 to debug instruction register 1 (0 x01EC 0014); status register 1 (0 x01EC 0024) is read waiting for the pipeline stall flag to be active, indicating that the pipeline has been stalled. One beat of the PC pointer from the lapping CPU0 can be observed. The debug channel is released and all 0 s are written to the PJ register (0 x01EC 0004) (it may not be released every operation, it may be released after multiple operations).

The processor core generally includes a plurality of on-chip general purpose registers, for example, in this embodiment, the processor core includes on-chip A0 to a31 registers, and on-chip B0 to B31 registers, and the on-chip A0 register is taken as an example of the on-chip general purpose registers, and reading the on-chip A0 register of the designated CPU core includes: continuously reading the state of the selection register PJ, waiting for the value of the selection register PJ to be changed into 01, and writing a debug command into a debug instruction register 0 and a debug instruction register 1 and writing debug data into a debug data register according to the debug operation of the on-chip host module for reading the on-chip A0 register of the specified CPU core, which is required to be executed by the specified CPU core, after the value of the selection register PJ is changed into 01; then reading the state register 0 and the state register 1 to obtain debugging states and debugging data so as to judge whether the access to the on-chip A0 register of the CPU core appointed by reading is successful or not; releasing JTAG debugging channel, writing all 0 to the selection register PJ; specifically, the embodiment includes continuously reading the state of the PJ register (0 x01EC 0004), waiting for its value to become 01, indicating that other hosts occupy the debug channel; writing 0x01EC0100 (addressing of A0 register within self-grinding CPU0 chip, if it is an address addressable by self-grinding CPU0, then writing address directly, e.g. 0x70000000 of EMIF) to debug instruction register 0 (0 x01EC 0010); write 0x00008080 (command to read address) to debug instruction register 1 (0 x01EC 0014. If self-grinding CPU1 is operated, the write value is 0x00008081, the following); read status register 1 (0 x01EC 0024), waiting for the read data to be valid indicates valid, indicating that the read data is valid. Read status register 0 (0 x01EC 0020), valid read data is acquired. And a release channel for writing all 0 s to the PJ register (0 x01EC 0004) (release may not be necessary every time operation, and release may be performed after a plurality of operations). The read status register 1 (0 x01EC 0024) uses bit 4 as a read data valid flag, and the 4 th bit is valid, indicating that the read data is valid.

Taking the on-chip A0 register as an example of an on-chip general purpose register, writing the on-chip A0 register of the specified CPU core includes: continuously reading the state of the selection register PJ, waiting for the value of the selection register PJ to be changed into 01, and writing a debug command into a debug instruction register 0 and a debug instruction register 1 and writing debug data into a debug data register according to the debug operation of the on-chip host module for writing the on-chip A0 register of the specified CPU core, which is required to be executed by the specified CPU core, after the value of the selection register PJ is changed into 01; then reading the state register 0 and the state register 1 to obtain debugging states and debugging data so as to judge whether writing of the on-chip A0 register of the appointed CPU core is successful or not; the JTAG debug channel is released, and all 0 s are written to the select register PJ. Specifically, the embodiment includes continuously reading the state of the PJ register (0 x01EC 0004), waiting for its value to become 01, indicating that other hosts occupy the debug channel; write 0x12345678 (indicating that the data written to A0 is 0x 12345678) to debug instruction register 0 (0 x01EC 0010); write 0x00008180 (command to write data, write value 0x00008181 if self-grinding CPU1 is operated) to debug instruction register 1 (0 x01EC 0014), the following is the same; writing 0x01EC0100 (self-grinding CPU0 on-chip A0 register addressing) to debug instruction register 0 (0 x01EC 0010); write 0x00008280 (command to write address, write value 0x00008281 if self-grinding CPU1 is operated) to debug instruction register 1 (0 x01EC 0014), the following is the same; the read status register 1 (0 x01EC 0024) waits for the write data to be valid indicating valid high, indicating that the write data is valid. And a release channel for writing all 0 s to the PJ register (0 x01EC 0004) (release may not be necessary every time operation, and release may be performed after a plurality of operations). The read status register 1 (0 x01EC 0024) uses bit 5 as a write data valid flag, and if bit 5 is valid, it indicates that the write data is valid.

The reading of the specified on-chip and off-chip set resources includes: continuously reading the state of the selection register PJ, waiting for the value of the selection register PJ to be changed into 01, and writing a debugging command into the debugging instruction register 0 and the debugging instruction register 1 and writing debugging data into the debugging data register according to the debugging operation of the on-chip host module for reading the appointed on-chip external resources, which is required to be executed by the appointed CPU core, after the value of the selection register PJ is changed into 01; then reading the state register 0 and the state register 1 to obtain debugging states and debugging data so as to judge whether accessing the on-chip and off-chip resources specified by reading is successful or not; releasing JTAG debugging channel, writing all 0 to the selection register PJ; it is similar to reading the on-chip A0 register of the designated CPU core, except that the debug command and data involved are different; in addition, here and hereinafter, the on-chip and off-chip resources cover the low-speed peripheral and the high-speed peripheral, and since the buses on which the two on-chip and off-chip resources are mounted are different (one is a configuration bus and the other is a data bus, as shown in fig. 1), the debug commands and data related to the two on-chip and off-chip resources are also different, and therefore, the details will not be described here.

Writing the specified on-chip and off-chip set resources includes: continuously reading the state of the selection register PJ, waiting for the value of the selection register PJ to be changed into 01, and writing a debugging command into the debugging instruction register 0 and the debugging instruction register 1 and writing debugging data into the debugging data register according to the debugging operation of the on-chip host module for writing the appointed on-chip internal and external resources required to be executed by the appointed CPU core after the value of the selection register PJ is changed into 01; then reading the state register 0 and the state register 1 to obtain debugging states and debugging data so as to judge whether writing of the specified on-chip and off-chip resources is successful or not; releasing JTAG debugging channel, writing all 0 to the selection register PJ; it is similar to writing to the on-chip A0 register of the designated CPU core, except that the debug commands and data involved are different and will not be described in detail herein.

The on-read-sheet storage includes: continuously reading the state of the selection register PJ, waiting for the value of the selection register PJ to be changed into 01, and writing a debug command into a debug instruction register 0 and a debug instruction register 1 and writing debug data into a debug data register according to the debug operation stored on a read chip required to be executed by the on-chip host module aiming at a specified CPU core after the value of the selection register PJ is changed into 01; then reading the state register 0 and the state register 1 to obtain debugging states and debugging data so as to judge whether the on-chip storage is successful or not; releasing JTAG debugging channel, writing all 0 to the selection register PJ; it is similar to reading the on-chip A0 register of the designated CPU core, except that the debug commands and data involved are different and will not be described in detail herein.

The on-write-chip storage includes: continuously reading the state of the selection register PJ, waiting for the value of the selection register PJ to be changed into 01, and writing a debug command into a debug instruction register 0 and a debug instruction register 1 and writing debug data into a debug data register according to the debug operation stored on a write chip required to be executed by the on-chip host module aiming at a specified CPU core after the value of the selection register PJ is changed into 01; then reading the state register 0 and the state register 1 to obtain debugging states and debugging data so as to judge whether the on-chip storage is successful or not; releasing JTAG debugging channel, writing all 0 to the selection register PJ; it is similar to writing to the on-chip A0 register of the designated CPU core, except that the debug commands and data involved are different and will not be described in detail herein.

The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above examples, and all technical solutions belonging to the concept of the present invention belong to the protection scope of the present invention. It should be noted that modifications and adaptations to the present invention may occur to one skilled in the art without departing from the principles of the present invention and are intended to be within the scope of the present invention.

Claims

1. The processor is characterized in that the configuration bus comprises a host interface used for accessing the simulation debugging module, the simulation debugging module comprises a slave interface connected with the host interface and a corresponding decoding module used for being accessed by the on-chip host module, and the simulation debugging module also comprises a group of registers and selectors used for realizing multiplexing control of the JTAG interface and the on-chip host module on the simulation debugging module.

2. The processor of the multiplexed JTAG debug channel debug CPU core of claim 1, wherein registers in the set of registers and selectors comprise:

the debug instruction register is used for storing debug instructions;

the debugging data register is used for storing debugging data;

and the state register is used for storing the debugging state.

3. The processor of claim 2, wherein the enable register PE comprises a first enable register PE1 and a second enable register PE2, wherein the first enable register PE1 and the second enable register PE2 are each used to represent global enablement of other host debugging, and the on-chip host module is allowed to implement the debugging function of the CPU core and access the private space or resources of the CPU core using the register and the selector multiplexing emulation debug module only if the first enable register PE1 is equal to the first set value and the second enable register PE2 is equal to the second set value.

4. The processor of claim 3, wherein the debug instruction register comprises a debug instruction register 0 and a debug instruction register 1, the debug instruction register 0 is used for storing the low 32 bits of the debug instruction, and the debug instruction register 1 is used for storing the high 16 bits of the debug instruction; the status register comprises a status register 0 and a status register 1, wherein the status register 0 is used for storing the low 32 bits of the debugging state, and the status register 1 is used for storing the high 16 bits of the debugging state.

5. The processor of the multiplexed JTAG debug channel debug CPU core of claim 4, wherein a selector of said set of registers and selectors comprises: a first selector for selecting whether to write the debug instruction through the configuration slave interface or scan the debug instruction through the JTAG interface by the on-chip host module; a second selector for selecting whether to return the collected state to the JTAG interface or to generate the on-chip host module of the debug request; a third selector for selecting whether to return the collected state to the JTAG interface or to generate the on-chip host module of the debug request; and a fourth selector for selecting whether to write or scan debug data through the configuration slave interface or through the JTAG interface by the on-chip host module.

6. The processor of the multiplexed JTAG debug channel debug CPU core of claim 5, wherein said decode module comprises: the simple decoding module is used for decoding the instruction latched in the instruction register under the TCK clock domain in the simulation debugging module to generate access control signals for the enable register PE, the select register PJ and the instruction register under the system clock domain in the simulation debugging module; and the configuration bus slave interface register decoding module is used for decoding the bus request generated by the on-chip host module to generate access control signals for an enable register PE, a selection register PJ and an instruction register and a data register in a system clock domain in the emulation debugging module.

7. A computer device comprising a microprocessor and a memory connected to each other, wherein the microprocessor is a processor of a multiplexed JTAG debug channel debug CPU core as claimed in any one of claims 1 to 6.

8. An application method of the processor for debugging a CPU core by multiplexing JTAG debug channels according to any one of claims 3 to 6, comprising:

9. The method according to claim 8, wherein the step S102 of assigning a debug function includes controlling a part or all of a suspension of an execution pipeline of the assigned CPU core, a single step of a pipeline of the assigned CPU core, and a running of the pipeline of the assigned CPU core;

10. The method according to claim 9, wherein accessing the private space or resource of the designated CPU core in step S102 includes reading an on-chip general register of the designated CPU core, writing an on-chip general register of the designated CPU core, reading the designated on-chip resources, writing the designated on-chip resources, reading on-chip storage, writing on-chip storage;

the read-specified on-chip and off-chip set resources include: continuously reading the state of the selection register PJ, waiting for the value of the selection register PJ to be changed into 01, and writing a debugging command into the debugging instruction register 0 and the debugging instruction register 1 and writing debugging data into the debugging data register according to the debugging operation of the on-chip host module for reading the appointed on-chip internal and external resources required to be executed by the appointed CPU core after the value of the selection register PJ is changed into 01; then reading the state register 0 and the state register 1 to obtain debugging states and debugging data so as to judge whether accessing the on-chip and off-chip resources specified by reading is successful or not; releasing JTAG debugging channel, writing all 0 to the selection register PJ;