CN101382583A - Multi-core microprocessor JTAG debug method - Google Patents

Abstract

The invention discloses a multi-core microprocessor JTAG debug method, aiming at solving the technique problem that a plurality of IP cores are debugged by a single JTAG debug interface. The technical proposal is that: a debug supporting module which consists of a chain-selection instruction order register, an encoder, a first multi-way selector and a second multi-way selector is added in the multi-core microprocessor to serve as the debug interface of the whole multi-core chip; furthermore, a chain-selection order is added in the debug software of the multi-core chip, an enable signal of the chain-selection order of the low level of k TCK clocks is maintained by a JTAG emulator; finally, the debug supporting module is adopted for carrying out debugging to the multi-core microprocessor. In the invention, a plurality of inner cores in the multi-core chip can be debugged by one JTAG debug interface, and the number of the supported inner cores can achieve up to 2<k>, and the original signal-core debug software can be used repeatedly.

Description

Multi-core microprocessor JTAG debug method

Technical field: the present invention relates to the adjustment method based on the JTAG standard of microprocessor chip, especially the multi-core microprocessor chip is carried out the method for JTAG debugging.

Background technology: along with the increase of problem scale and the raising that real-time is required, the processing power of monokaryon microprocessor has been difficult to satisfy the demands.Multi-core technology for the equipment development personnel have brought unprecedented advantage experience, comprise higher processor performance, higher power utilization efficient and at the littler physical memory volume of embedded device.Yet coenocytism has significantly increased the complexity of system, and along with popularizing of coenocytism in the single-chip, the debugging problem of multicomputer system is apparent more outstanding.

At present, most of IP (Intellectual Property, intellecture property) module all adopt the IEEE1149.1 standard jtag interface as its debugging interface, this has just brought a problem: a plurality of TAP (Test Access Port, test access port) controller is arranged on this chip.Some IP providers have utilized the chip-scale passage support of oneself developing to debug single IP module.In order to debug a plurality of kernels, the chip-scale passage of addressable all TAP controllers of a standard is very necessary.On the System on Chip/SoC of another one complexity, a plurality of different kernels can use different debugging acids, and how allowing the debugging acid of these single IP modules continue to play a role also is a major issue.Just needing the new debugging software of exploitation iff integrated a plurality of IP that need debug on the multi-core microprocessor chip obviously be a kind of waste.Best bet is to reuse those debugging acids at single IP, does not make an amendment on the software or only makes a spot of modification.

In multi-core processor, the developer wishes just can debug these kernels by a plurality of kernels that the outer single jtag interface visit chip integration of sheet becomes.At present, the most frequently used method of polycaryon processor JTAG debugging is that daisy chain connects (Daisy-chain) method, TDI of all IP kernels (Test DataInput, test data input) and TDO (Test Data Output, test data output) connect into the chain of a serial, IP _iTDO be connected to

The TDI of (1≤i≤n-1, n are the number of IP kernel).Control signal TCK (Test Clock, test clock), TMS (Test Mode Select, test pattern is selected) and TRST (Test Reset, test reset) are connected on the TAP controller of all IP kernels.When instruction scan operation, instruction is moved into the order register of each IP kernel TAP by serial, so just can conduct interviews to a plurality of TAP controllers simultaneously, catch the borderline input and output signal of each IP kernel of synchronization, very valuable for interconnected test.Yet there are two shortcomings in daisy chain connected mode on this single-chip: at first, it and IEEE 1149.1 agreements are incompatible; Secondly, its feasible test access to the single TAP controller in n the IP kernel becomes complicated.

For reaching the compatibility with IEEE 1149.1 agreements, someone proposes the scheme of a kind of increase TAP link block TLM (TAP Linking Module), on the multi-core microprocessor chip, only provide one fully and the TAP interface of IEEE 1149.1 protocol-compliants, TDI externally is provided, TMS, TCK, a TRST and TD05 pin, the JTAG debugging interface of emulator is connected to each TAP by TLM, TLM is responsible for the signal of JTAG debugging interface is connected on the TAP of the IP kernel that will test of some appointments, and the TAP of chip internal IP kernel and TLM interconnect, each TAP is except 5 signal wires of the JTAG debugging interface of binding, also increased selection signal SEL and enable signal ENA, determined that by SEL and ENA the TAP of which or which IP kernel is connected on the JTAG debugging interface of emulator.TLM is sent to the corresponding TDI of certain TAP, TMS, TCK and TRST port in the sheet according to SEL and ENA with test signal TDI, TMS, TCK, the TRST of emulator, the data that the TDO port of this TAP is exported are sent to debug host by the TDO pin through the JTAG emulator, to realize JTAG debugging to certain IP kernel in the multi core chip.Increase extra selection and enable signal but this method is necessary for the TAP of IP kernel inside, this just must revise the TAP of IP kernel inside, and ENA and SEL signal are added in the design of TAP.The ENA that the TAP controller of each TAP obtains from TLM enables as input or forbids this TAP, order register among the TAP increases the SEL signal and outputs to TLM sweeps its order register with response instruction, this makes hardware design become complicated, if IP kernel is a stone, this modification is impossible.Because TLM can connect the TAP of a plurality of IP kernels, and on the hardware modification of TAP is made the debugging software that also amended monokaryon debugging software will be integrated into multi core chip except will making amendment the debugging software of original single IP kernel, this also makes the design of debugging software become complicated, and reusability is bad.

Therefore, polycaryon processor debugging field need badly a kind of can compatible IEEE 1149.1 agreements, the adjustment method of reusable each kernel is debugged each kernel of polycaryon processor.

Summary of the invention:

The technical problem to be solved in the present invention is exactly how based on IEEE 1149.1 standards, makes it possible to by single JTAG debugging interface a plurality of IP kernels integrated in the polycaryon processor be carried out the JTAG debugging.

Technical scheme of the present invention may further comprise the steps:

The first step, the TAP controller of a chip-scale of increase in multi-core microprocessor---debugging support module DSM (Debug Support Module) with n IP kernel.The method for designing of debugging support module is:

The debugging support module is the debugging interface of whole multi core chip, it has the jtag interface with IEEE 1149.1 protocol-compliants, except that having TDI, TMS, TCK, TRST, these five pins of TDO and the JTAG debugging interface of emulator links to each other, also adding a multinuclear debugging and select pin to accept the enable signal MDS (Mutil-core Debug Select) of chain choosing order; MDS is produced by emulator, and ((Emulation 1, artificial foot 1) pin is as the output pin of MDS signal for the EMU0 (Emulation 0, artificial foot 0) of selection JTAG emulator or EMU1.All IP kernels all link to each other in debugging support module and the sheet, it will be sent to the corresponding TDI of certain TAP, TMS, TCK and TRST port in the sheet from test signal TDI, TMS, TCK and the TRST signal of emulator input, the data that the TDO port of this TAP is exported are sent to debug host by the TDO pin through the JTAG emulator, to realize JTAG debugging to certain IP kernel in the multi core chip.

The debugging support module selects order register, code translator, first MUX and second MUX to form by chain.The TCK of JTAG emulator directly links to each other with the TAP controller of each IP kernel with TRST.Chain select the length of order register be k ( $k=\left\{\begin{array}{c}\left[{\log }_{2}n\right]+1(k\&NotEqual;2^n)\\ {\log }_{2}n(k=2^n)\end{array}\right.,$ N is the number of IP kernel integrated in the multi core chip) position, its input end links to each other with EMU0 (or EMU1) pin with the TDI of JTAG emulator, obtain TDI and MDS from the JTAG emulator, its output terminal links to each other with code translator, when MDS is low level and k tck clock of maintenance, the TDI of serial input moves into chain by turn and selects order register, MDS becomes high level at the rising edge of k+1 tck clock by low level, and this moment, chain selected order register to select order code to send code translator to as chain from the k position binary code that TDI obtains; The input end of code translator selects order register to link to each other with EMU0 (or EMU1) pin with chain, output terminal links to each other with second MUX with first MUX, when MDS is high level, code translator will select the chain of order register input select order code to be decoded into the identification number (being the sequence number of IP kernel) of certain IP kernel from chain, and send decode results to first MUX and second MUX; The input end of first MUX both linked to each other with TDI, the TMS of JTAG emulator, link to each other with the output terminal of code translator again, output terminal links to each other with TMS with the TDI of the TAP of all IP kernels, it obtains TDI and TMS from the JTAG emulator, obtain decode results from code translator, TDI and TMS are given TDI and the TMS of certain IP kernel TAP according to decode results; The input end of second MUX both linked to each other with the TDO of all IP kernel TAP, linked to each other with the output terminal of code translator again, and its output terminal links to each other with the TDO of JTAG emulator, and the TDO that certain IP kernel is transmitted according to decode results delivers to the TDO pin of JTAG emulator.

Second step, the debugging software of original single IP kernel is integrated into the multi core chip debugging software, an and chain choosing of increase order in the debugging software of multi core chip, chain selects command format to be: intSelectIP (int IpNum), function is that IpNum is sent to emulator, parameter I pNum is the identification number of each IP kernel, and when IpNum was j, j is selected in expression, and (1≤j≤n) individual IP kernel was debugged.

In the 3rd step, keep k the low level MDS signal of tck clock by the JTAG emulator.Method is: length of definition is p in the FPGA (Field Programmable Gate Array) of JTAG emulator

Position, digit are the counter Counter of k, the Counter initial value is changed to k, after the JTAG emulator receives the chain choosing order of debug host transmission, Counter begins counting under tck clock control, the output of EMU0 (or EMU1) pin is changed to low level, will exports from the serial of emulator TDI pin from the IpNum that debug host transmits simultaneously; The value of Counter reduces at 0 o'clock, and the output of EMU0 (or EMU1) pin is changed to high level.In the FPGA (Field Programmable Gate Array) of JTAG emulator, just generated k low level MDS signal of TCK cycle like this.

The 4th step, adopt the debugging support module that multi-core microprocessor is debugged, method is:

Step 1, debug host are carried out chain choosing order, give JTAG emulator with parameter I pNum.

Step 2, after the JTAG emulator is received IpNum, generate to keep k the low level MDS signal of tck clock, output to the multinuclear debugging selection pin of debugging support module, simultaneously IpNum is outputed to by turn the TDI pin of JTAG debugging interface by EMU0 (or EMU1) pin of emulator.

Step 3, when MDS is low level (a preceding k tck clock), the chain that the TDI serial moves into the debugging support module selects order register, and when MDS becomes high level by low level (k+1 tck clock), code translator begins decoding.

Step 4, according to the difference of IpNum, code translator selects order code to be decoded as the identification number of j IP kernel on chain, and first MUX is received the TDI that will be sent to the TAP of j IP kernel from the TDI and the TMS of JTAG emulator acquisition after the decode results _jAnd TMS _j, second MUX is received after the decode results output TDO with this IP kernel TAP _jThe TDO that is sent to chip debugging interface sends to debug host through emulator then, and debug host is called the IP that is integrated in the multi core chip debugging software _jOriginal single IP kernel debugging software is to IP _jDebug.

Adopt the present invention can obtain following technique effect:

1. adopt developer of the present invention can debug the kernel of a plurality of discrete states in the multi core chip via a JTAG debugging interface, the problem that the bit displacement that it has avoided being run in the daisy chain method changes along with the number of integrated kernel, thereby in the multi core chip structure, have higher performance.

2. only need in the debugging software of multi core chip, to increase simple chain choosing order, execute after the chain choosing order, call the original debugging software of the IP kernel that is integrated in the multi core chip debugging software and just can debug any one IP kernel of multi core chip, therefore the debugging software of original IP kernel is reusable.In host side, no matter be debug hardware or debugging software can obtain good reusability on the sheet of original IP kernel.In multi core chip, no matter integrated in the chip is the IP kernel of which kind of structure, only needs original debugging interface of these IP kernels and debugging support module are interconnected, just can be in multi core chip debug hardware and original debug function on the sheet of multiplexing these IP kernels.

3. being a kind of solution that can highly expand, is the k position because chain selects order register, can support to reach 2 ^kTherefore bar chain choosing order can be supported to reach 2 ^kThe debugging of individual kernel.

Description of drawings

Fig. 1 is the connection diagram of background technology a plurality of TAP when adopting daisy chain method that multi-core microprocessor is debugged;

Fig. 2 is the connection diagram of a plurality of TAP when adopting increase TLM method that multi-core microprocessor is debugged;

Fig. 3 is the interconnection structure figure that the present invention debugs each kernel TAP in support module and the sheet;

Fig. 4 is that the present invention debugs support module internal logic structure figure;

Fig. 5 is the present invention's desired MDS signal timing diagram when debugging support module and carrying out chain choosing order.

Embodiment

Fig. 1 is the connection layout of n TAP when adopting the daisy chain method of attachment that multi-core microprocessor is debugged: IP ₁The TDI of TAP be connected to the TDI of the outer JTAG debugging interface of sheet, IP _iThe TDO of TAP be connected to IP _I+1(TDI of TAP of 1≤i≤n-1), IP _nThe TDO of TAP is connected to the TDO of the outer JTAG debugging interface of sheet.The TDI signal of each IP kernel TAP and TDO signal connect into the chain of a serial, and control signal TMS, TCK and TRST then are that all TAP share, and promptly TMS, the TCK of the outer JTAG debugging interface of sheet link to each other with TRST with TMS, the TCK of all TAP with TRST.This method is used very general in the test of the chip interconnect of pcb board level, also can use in single-chip, realizes that visit to the TAP of all embeddings is to realize the debugging to each IP kernel of multi-core microprocessor.But it and IEEE 1149.1 agreements are incompatible, and the connected mode of daisy chain makes test access to the single TAP in n the IP kernel complexity that becomes.

Fig. 2 is the connection diagram of a plurality of TAP when adopting increase TLM method that multi-core microprocessor is debugged.TLM is as the unique debugging interface of chip, and its input is TDI, TMS, TCK and TRST, and output is TDO.5 pin signal TDI, TMS, TCK, TRST and the TDO of each IP kernel TAP interconnect with TLM, and TLM is responsible for the signal of JTAG debugging interface is connected on the TAP of the IP kernel that will test of some appointments.This method need select signal SEL to link to each other with TLM with enable signal ENA for each TAP increases, and determines that by SEL and ENA the TAP of selection which or which IP kernel is connected on the TAP interface of chip.Therefore this method must be revised the TAP of IP kernel inside, and SEL and ENA are added in the design of TAP, makes hardware design become complicated.Because TLM can connect the TAP of a plurality of IP kernels, and just can be integrated in the debugging software of multi core chip after making the debugging software of original IP kernel to make amendment to the modification of TAP on the hardware, this makes the design of debugging software become complicated, and reusability is bad.

Fig. 3 is the interconnection structure figure that the present invention debugs each kernel TAP in support module and the sheet.

The debugging support module is except that having TDI, TMS, TCK, TRST, these five input pins of TDO and the JTAG debugging interface of emulator links to each other, also have a multinuclear debugging to select pin to accept the enable signal MDS of chain choosing order, MDS is produced by emulator, and the EMU0 of JTAG emulator (or EMU1) pin is the input pin of MDS signal.The output TDI of debugging support module ₁～TDI _n, TMS ₁～TMS _n, TCK_N, TRST_N respectively with IP ₁～IP _nTDI, TMS, TCK, the TRST of TAP to link to each other (be IP _jTDI, TMS, TCK, the TRST of TAP be respectively input signal TDI _j, TMS _j, TCK_N, TRST_N), the debugging support module is sent to test signal TDI, TMS, TCK and the TRST signal of emulator the corresponding TDI of TAP, TMS, TCK and the TRST port of certain IP kernel that will debug in the sheet; The debugging support module has TDO in addition ₁～TDO _nThis n the input respectively with IP ₁～IP _nThe output signal TDO of TAP link to each other, the data of the TAP output of debugged IP kernel are sent to debug host by the TDO pin through the JTAG emulator.It is outer as the unified jtag interface of entire chip that input TDI, TMS, TCK, TRST, MDS and the output TDO of debugging support module is connected to sheet, by the such chip-scale TAP controller channel of debugging support module each IP kernel on the multi core chip carried out the JTAG debugging.

Fig. 4 is that the present invention debugs the support module building-block of logic.The debugging support module selects order register, code translator, first MUX and second MUX to form by chain.Chain selects the input end of order register to link to each other with EMU0 (or EMU1) with the TDI of JTAG emulator, obtains TDI and MDS from emulator, and output terminal links to each other with code translator, selects order code to deliver to code translator on chain; The input end of code translator selects order register to link to each other with EMU0 (or EMU1) with chain, and output terminal links to each other with second MUX with first MUX; The input end of second MUX links to each other with the TDO of the TAP of all IP kernels and the output terminal of code translator respectively, and its output terminal links to each other with the TDO of JTAG emulator, and it selects the TDO of certain IP kernel TAP to deliver to the TDO pin of emulator under the control of decode results.When the MDS signal was low level, the chain that enables to debug in the support module selected order register, and the TDI serial moves into chain and selects in the order register.The MDS signal is kept and is become high level by low level after k tck clock cycle, this moment chain to select what deposit in the order register be that chain selects order code.When chain choosing order is to select IP _j(during 1≤j≤n), first MUX is with TDI and IP _jTest input signal TDI _jConnect TMS and IP _jTest input signal TMS _jConnect, second MUX is with IP _jTest output signal TDO _jBe connected on the outer test output signal TDO of sheet.At this moment, at the debugging interface (TDI of chip JTAG debugging interface (TDI, TMS, TCK, TRST, TDO) and IPj _j, TMS _j, TCK_N, TRST_N, TDO _j) between formed a path, the just IP that can become chip integration by the outer unique JTAG debugging interface of sheet _jCarry out the JTAG debugging.

Fig. 5 is that the debugging support module is carried out the sequential chart that chain selects MDS signal required when ordering: the JTAG emulator receives and produces k the low level MDS signal of tck clock after chain selects command request, EMU0 (or EMU1) pin by the JTAG emulator outputs to the multinuclear debugging selection pin of debugging support module, and parameter I pNum is outputed to the TDI of debugging support module by the TDI pin of JTAG emulator simultaneously.

Claims (1)

1. multi-core microprocessor JTAG debug method is characterized in that may further comprise the steps:

The first step, in multi-core microprocessor, increasing the TAP controller of a chip-scale with n IP kernel---debugging support module DSM is as the debugging interface of whole multi core chip, method is: the debugging support module has the jtag interface with the IEEE1149.1 protocol-compliant, remove and have TDI, TMS, TCK, TRST, these five pins of TDO are with outside the JTAG debugging interface of emulator links to each other, also adding a multinuclear debugging selects pin to accept the enable signal MDS of chain choosing order, MDS is produced by emulator, and selecting the artificial foot 0 of JTAG emulator is that EMU0 or artificial foot 1 are the output pin of EMU1 pin as the MDS signal; All IP kernels all link to each other in debugging support module and the sheet, it will be sent to the corresponding TDI of certain TAP, TMS, TCK and TRST port in the sheet from test signal TDI, TMS, TCK and the TRST signal of emulator input, and the data that the TDO port of this TAP is exported are sent to debug host by the TDO pin through the JTAG emulator; The debugging support module selects order register, code translator, first MUX and second MUX to form by chain; The TCK of JTAG emulator directly links to each other with the TAP controller of each IP kernel with TRST; It is the k position that chain selects the length of order register, $k=\left\{\begin{array}{c}\left[{\log }_{2}n\right]+1(k\&NotEqual;2^n)\\ {\log }_{2}n(k=2^n)\end{array}\right.,$ Its input end links to each other with EMU0 or EMU1 pin with the TDI of JTAG emulator, obtain TDI and MDS from the JTAG emulator, its output terminal links to each other with code translator, when MDS is low level and k tck clock of maintenance, the TDI of serial input moves into chain by turn and selects order register, MDS becomes high level at the rising edge of k+1 tck clock by low level, and this moment, chain selected order register to select order code to send code translator to as chain from the k position binary code that TDI obtains; The input end of code translator selects order register to link to each other with EMU0 or EMU1 pin with chain, output terminal links to each other with second MUX with first MUX, when MDS is high level, code translator will select the chain of order register input select order code to be decoded into the identification number of certain IP kernel from chain, and send decode results to first MUX and second MUX; The input end of first MUX both linked to each other with TDI, the TMS of JTAG emulator, link to each other with the output terminal of code translator again, output terminal links to each other with TMS with the TDI of the TAP of all IP kernels, it obtains TDI and TMS from the JTAG emulator, obtain decode results from code translator, TDI and TMS are given TDI and the TMS of certain IP kernel TAP according to decode results; The input end of second MUX both linked to each other with the TDO of all IP kernel TAP, linked to each other with the output terminal of code translator again, and its output terminal links to each other with the TDO of JTAG emulator, and the TDO that certain IP kernel is transmitted according to decode results delivers to the TDO pin of JTAG emulator;

Second step, the debugging software of original single IP kernel is integrated into the multi core chip debugging software, an and chain choosing of increase order in the debugging software of multi core chip, chain selects command format to be: int SelectIP (intIpNum), function is that IpNum is sent to emulator, and parameter I pNum is the identification number of each IP kernel, when IpNum is j, expression selects j IP kernel to debug 1≤j≤n;

The 3rd step kept k the low level MDS signal of tck clock by the JTAG emulator, and method is: length of definition is that p position, digit are the counter Counter of k in the FPGA (Field Programmable Gate Array) of JTAG emulator,

The Counter initial value is changed to k, after the JTAG emulator receives the chain choosing order of debug host transmission, Counter begins counting under tck clock control, the output of EMU0 or EMU1 pin is changed to low level, will export from the serial of emulator TDI pin from the IpNum that debug host transmits simultaneously; The value of Counter reduces at 0 o'clock, and the output of EMU0 or EMU1 pin is changed to high level, has just generated k low level MDS signal of TCK cycle like this in the FPGA (Field Programmable Gate Array) of JTAG emulator;

The 4th step, adopt the debugging support module that multi-core microprocessor is debugged, method is:

Step 1, debug host are carried out chain choosing order, give JTAG emulator with parameter I pNum;

Step 2, after the JTAG emulator is received IpNum, generate to keep k the low level MDS signal of tck clock,, simultaneously IpNum is outputed to by turn the TDI pin of JTAG debugging interface by the multinuclear debugging selection pin that the EMU0 or the EMU1 pin of emulator outputs to the debugging support module;

Step 3, when MDS was low level, the chain that the TDI serial moves into the debugging support module selected order register, and when MDS became high level by low level, code translator began decoding;

Step 4, according to the difference of IpNum, code translator selects order code to be decoded as the identification number of j IP kernel on chain, and first MUX is received the TDI that will be sent to the TAP of j IP kernel from the TDI and the TMS of JTAG emulator acquisition after the decode results _jAnd TMS _j, second MUX is received after the decode results output TDO with this IP kernel TAP _jThe TDO that is sent to chip debugging interface sends to debug host through emulator then, and debug host is called the IP that is integrated in the multi core chip debugging software _jOriginal single IP kernel debugging software is to IP _jDebug.

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