CN105550119B - A kind of simulator based on JTAG protocol - Google Patents
A kind of simulator based on JTAG protocol Download PDFInfo
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- CN105550119B CN105550119B CN201610063492.8A CN201610063492A CN105550119B CN 105550119 B CN105550119 B CN 105550119B CN 201610063492 A CN201610063492 A CN 201610063492A CN 105550119 B CN105550119 B CN 105550119B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3648—Software debugging using additional hardware
- G06F11/3652—Software debugging using additional hardware in-circuit-emulation [ICE] arrangements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3648—Software debugging using additional hardware
- G06F11/3656—Software debugging using additional hardware using a specific debug interface
Abstract
The present invention discloses a kind of simulator based on JTAG protocol, including parallel bus interface, jtag interface, JTAG simulation process IP kernel and interface conversion unit, one end of JTAG simulation process IP kernels passes through parallel bus interface, interface conversion unit connection debugging host, the other end passes through jtag interface linking objective chip, JTAG simulation process IP kernels pass through parallel bus interface, interface conversion unit receives the tune-up data of debugging host, it is exported after being converted to JTAG data by jtag interface to objective chip, and JTAG simulation process IP kernel receives the JTAG data of objective chip by jtag interface, be converted to the data for meeting parallel bus protocol, through parallel bus interface, communication interface converting unit is exported to debugging host.The present invention have the advantages that it is simple in structure, can be based on that IP kernel realizes JTAG copyings, simulation velocity soon and versatility and Scalable Performance are strong.
Description
Technical field
The present invention relates to JTAG simulation technical fields more particularly to a kind of simulators based on JTAG protocol.
Background technology
Chip is likely in design, manufacture and encapsulation process there are problem, and the mistake thus brought can not only influence
The performance of entire chip or the failure for causing chip can also influence the development efficiency and application quality of chip, thus in order to ensure
The correctness of chip functions necessarily also needs to debug chip, correctness and Usefulness Pair the production high quality of debugging
Chip is most important.The debud mode of mainstream is using sheet sand covered at present, i.e., additional control mould is internally embedded in processor
Block, when meeting certain trigger condition into special state, application program is out of service under the special state, host
Then pass through the various resources inside emulator access chip.
The emulator used at present mainly has 2 kinds：One kind is in-circuit emulator（In Circuit Emulator, ICE）,
The in-circuit emulator needs to configure the connector for being exclusively used in certain chip, so that can both be used for as dedicated commissioning device
Monitor chip pin activity and chip external environment, and can with the operation of emulation chip, but each CPU emulate when all
A kind of corresponding ICE is needed, thus development cost is very high；Another is JTAG emulators（JTAG Emulator）,
It is also a kind of emulator that application is most at present, JTAG is a kind of international standard test protocol（IEEE-1149.1 standards）, JTAG
Emulator is debugged, therefore can save hardware i.e. using jtag interface by the jtag interface of chip offer
Expense.When JTAG emulators perform emulation, debugging host and objective chip are connected by JTAG emulators, tune is provided by objective chip
Interface logic is tried, which uses two-stage pattern, respectively operational mode and debugging mode, wherein in the operating mode, debugging
Structure does not control the operation of chip, chip system normal work；Under debugging mode, chip stops normal work, turns
And receiving the order that debugging interface is sent out, emulator can read and write the memory of objective chip and register, control program at this time
Operation etc..
When wanting through JTAG control targe chips, then have to realize, but JTAG is imitated by connecting an emulator
True device there is problems in application：JTAG emulators are in the processing mode of data flow, a kind of mode is direct at present
The parallel port data of host are converted into JTAG data by FPGA or CPLD, then by being controlled in host side software programming
It realizes, this mode speed is slow, and host is needed to support and jaws equipment；Also a kind of mode be by USB serial ports or
The emulator of network interface communication although this mode speed is fast, is typically to use molded application-specific entity circuit board, that is, adopts
With the form of integrated circuit plate, and due to emulating at present when is typically only capable to use and mounts emulator again outside debugging host
Method communicates, and the interface protocol of different emulators and debugging host is also what is be not quite similar, thus use is upper not
Facility, universal performance are poor, and user is difficult again other devices of Integration of Extended and function.
Invention content
The technical problem to be solved in the present invention is that：For technical problem of the existing technology, the present invention provides one
It is kind simple in structure, fast JTAG copyings, simulation velocity can be realized based on IP kernel and versatility and the strong base of Scalable Performance
In the simulator of JTAG protocol.
In order to solve the above technical problems, technical solution proposed by the present invention is：
A kind of simulator based on JTAG protocol, including parallel bus interface, jtag interface, JTAG processing IP kernel and
For the interface conversion unit of interface logic conversion, one end of JTAG processing IP kernel by the parallel bus interface, connect
Mouth converting unit connection debugging host, the other end are led to by the jtag interface linking objective chip, the JTAG processing IP kernel
The tune-up data that the parallel bus interface receives debugging host is crossed, is converted to after JTAG control data through the jtag interface
It exports to objective chip and JTAG processing IP kernels and the JTAG data of objective chip is received by the jtag interface, turn
It is exported after being changed to the data for meeting parallel bus protocol by the parallel bus interface, interface conversion unit to debugging host.
As a further improvement on the present invention：The JTAG processing IP kernel includes accessing parallel debugging data, output
The data interface module of parallel artificial data, for perform JTAG protocol conversion JTAG modular converters, for performing serial data
And the data conversion module converted and the storage buffer module for being cached to data, the data interface module lead to
The JTAG modular converters are crossed to connect with the data conversion module, it is described storage buffer module respectively with the data-interface mould
Block, data conversion module connection.
As a further improvement on the present invention：The JTAG modular converters include the processing unit being connected with each other and state
JTAG protocol signal is configured according to the tune-up data in control unit, the processing unit, and the status control unit is according to institute
The configuration for stating processing unit generates corresponding JTAG protocol signal as JTAG control data.
As a further improvement on the present invention：The processing unit include for be configured JTAG protocol signal state control
Register processed, for serial data shift count in JTAG protocol is configured shift count register, for specifying serial data
Link attribute and control log-on data transmission command register and for cache read, write-in data read-write buffering
Register, by the way that above-mentioned each register configuration JTAG protocol signal is configured.
As a further improvement on the present invention：During the processing unit configuration, pass through configuration control register or order
Register be configured to JTAG protocol signal Static output state or according to read-write operation type by be respectively configured control deposit
Device, shift count register, command register and read-write buffer register are to be configured to JTAG protocol signal dynamics data shape
State.
As a further improvement on the present invention：The status control unit includes TMS state machines, and the TMS state machines are pressed
JTAG protocol signal is generated according to the sequential of TAP controller state machine in JTAG protocol.
As a further improvement on the present invention：When starting a data manipulation, the status control unit, which receives, to be started
TMS state machines inside order startup, the TMS state machines carry out shape according to the configuration of the processing unit according to JTAG protocol
State is converted, and when state is in displaced condition, and the status signal for generating data displacement is sent to data conversion module.
As a further improvement on the present invention：The data conversion module include read-write shift register, counter and
For controlling the transmission control unit of the data transmission between the storage buffer module, the read-write shift register is by described
Counter controls perform the serial shift transmission of read-write data.
As a further improvement on the present invention：The displacement letter that the read-write shift register reception state control unit is sent
Number when, sampling input data carry out shifting function simultaneously export enabling signal to the counter；The counter receives read-write and moves
The enabling signal of bit register starts counting up, and output count completion signal transmits control function unit to described after the completion of counting；
After the transmission control function unit receives count completion signal, control and data in read-write shift register are read or are written
Buffer module is stored, and startup is controlled to shift next time, until shift signal is invalid.
As a further improvement on the present invention：The storage buffer module includes single port RAM bodies and storage control.
Compared with prior art, the advantage of the invention is that：
1）The present invention is based on the simulators of JTAG protocol, and the function of JTAG emulators is realized in the form of IP kernel, will
JTAG emulator IPization can just complete the function of emulator thereby using the IP kernel, realize the replacement to JTAG emulators, make
It obtains JTAG emulators and is no longer limited to the form of circuit board, but can be integrated into as IP kernel on SOC or in the FPGA of user,
Effectively increase the integrated level of emulator；General parallel interface and jtag interface are additionally provided simultaneously, thus based on this implementation
The IP kernel of example simulator can easily carry out various application extensions, substantially increase the versatility and facility of simulator
Property；
2）The present invention is based on the simulators of JTAG protocol, can will meet parallel bus protocol with reference to JTAG processing IP kernels
Data conversion into standard compliant JTAG protocol data, output control targe chip JTAG control data；Meanwhile JTAG
Processing IP kernel also is able to JTAG data conversions that objective chip export realizing that debugging is led into exporting by bus after parallel data
Order and data exchange between machine and objective chip, complete the function of JTAG emulators, and transmission structure is simple, can be effective
Raising JTAG serial datas transmission rate；
3）The present invention is based on the simulator of JTAG protocol, JTAG handles IP kernel especially by a set of Digital Logical Circuits reality
Existing, the entire logic of IP kernel is realized using hardware description language, and emulator function, Neng Goufang are realized without relying on entity circuit board
Being integrated into the design of the chips such as FPGA, ASIC just, is easy to use and is configured；
4）The present invention is based on the simulator of JTAG protocol, on the basis of parallel bus protocol, it is only necessary to add one end
Meet parallel bus protocol, the other end meets any communication interface of host communication protocol（As traditional parallel port, USB interface and
Ethernet interface etc.）, it is possible to it is extended to support and debugs the communication of arbitrary interface mode between host；
5）The present invention is based on the simulator of JTAG protocol, processing unit further sets a variety of registers, by a variety of
The configuration of register can flexibly be configured different JTAG protocol signals and carry out control targe chip, increase the flexible of artificial debugging
Property and controllability, while the setting of register also complies with the use habit of embedded system, thus is easy to implement integrated and extension.
Description of the drawings
Fig. 1 is the principle schematic that simulator of the present embodiment based on JTAG protocol performs emulation.
Fig. 2 is the structure diagram of simulator of the present embodiment based on JTAG protocol.
The realization flow diagram of processing unit configuration register when Fig. 3 is the present embodiment read-write operation.
Fig. 4 is the principle schematic of the present embodiment data conversion module and state control.
Marginal data：1st, JTAG handles IP kernel；11st, data interface module；12nd, JTAG modular converters；121st, processing unit；
122nd, status control unit；13rd, data conversion module；14th, buffer module is stored.
Specific embodiment
Below in conjunction with Figure of description and specific preferred embodiment, the invention will be further described, but not therefore and
It limits the scope of the invention.
As shown in Figure 1, 2, simulator of the present embodiment based on JTAG protocol include parallel bus interface, jtag interface,
JTAG handle IP kernel 1 and for interface logic conversion interface conversion unit, JTAG processing IP kernel 1 one end pass through it is parallel
Bus interface, interface conversion unit connection debugging host, the other end pass through jtag interface linking objective chip, JTAG processing IP
Core 1 receives the tune-up data of debugging host by parallel bus interface, is connect after being converted to JTAG control data by the JTAG
Mouth output receives the JTAG data of objective chip to objective chip and JTAG processing IP kernels 1 by jtag interface, is converted to symbol
It is exported after the data of merging rows bus protocol by the parallel bus interface, interface conversion unit to debugging host.
IP kernel（Intellectual property core, IP core）It is form for logic unit, it is repeatable to make
IC design module can carry out application-specific integrated circuit or the logical design of FPGA, so as to subtract based on IP kernel
Few design cycle.As shown in Figure 1, the present embodiment simulator is realized in the form of IP kernel between debugging host and objective chip
By JTAG emulator IPization, the function of emulator can be just completed thereby using the IP kernel for the function of JTAG emulators, realized
Replacement to JTAG emulators so that JTAG emulators are no longer limited to the form of circuit board, but can be integrated as IP kernel
Onto SOC or FPGA, the integrated level of emulator is effectively increased, while the present embodiment simulator provides general parallel connect
Mouth and jtag interface, thus the IP kernel based on the present embodiment simulator can easily carry out various application extensions, carry significantly
The high versatility and convenience of simulator.
The present embodiment parallel bus interface is the interface based on parallel bus protocol, can be incited somebody to action with reference to JTAG processing IP kernel 1
Meet the data conversion of parallel bus protocol into the data for the JTAG protocol for meeting IEEE1149.1 standards, export control targe core
The JTAG control data of piece, objective chip can be the chip of all kinds of support JTAG protocols；Meanwhile JTAG processing IP kernels 1 can also
It is enough by JTAG data conversions that objective chip export into being exported by bus after parallel data, realize and debug host and objective chip
Between order and data exchange, complete the function of JTAG emulators, and transmission structure is simple, can effectively improve JTAG strings
The transmission rate of row data, transmission rate specifically can be configured and adjust according to demand.
The present embodiment interface conversion unit is the interface conversion logic based on parallel bus protocol, passes through translation interface logic
It can realize the communication connection of user-defined any communication interface.The present embodiment JTAG processing IP kernels 1 pass through parallel bus
Interface is connected to interface conversion unit, and interface conversion unit is connected to debugging master by user-defined any communication interface again
Machine, so that JTAG processing IP kernels 1 can support one end to meet any communication interface of parallel bus protocol.Therefore this implementation
Example on the basis of parallel bus protocol, it is only necessary to add one end meet parallel bus protocol, the other end meet main-machine communication association
Any communication interface of view（Such as traditional parallel port, USB interface and Ethernet interface）, it is possible to it is extended to support and is led with debugging
The communication of arbitrary interface mode between machine.
During emulation testing, by parallel after debugging interface conversion logic of the tune-up data of host by interface conversion unit
Bus interface exports to JTAG and handles IP kernel 1, and the data that JTAG processing IP kernels 1 export are sent to interface by parallel bus interface and turn
Unit is changed, interface conversion unit is supplied to debugging host after carrying out interface conversion logic.
As shown in Fig. 2, JTAG processing IP kernel 1 is included for accessing parallel debugging data in the present embodiment, output is imitated parallel
The data interface module 11 of true data（Interface modules）, for perform JTAG protocol conversion JTAG modular converters 12,
For performing the data conversion module 13 of data serioparallel exchange（Trans modules）And the storage for being cached to data
Buffer module 14（Fifo module）, data interface module 11 connect with data conversion module 13 by JTAG modular converters 12, deposited
Storage buffer module 14 is connect respectively with data interface module 11, data conversion module 13.At above-mentioned each module composition JTAG
IP kernel 1 is managed, can realize the functions of JTAG emulators, while as IP kernel in use, operability is strong and flexibly configurable.
In the present embodiment, data interface module 11 specifically handles the access of parallel bus, sample bus is passed to and line number
According to, while parallel data is returned to by bus.The flexibility used to improve IP kernel, the present embodiment data interface module 11 include
2 clocks, one is user clock, the other is jtag test clock（TCK）, wherein user clock is supplied to user interface to make
With tck clock is then the work clock inside entire IP kernel.Above-mentioned 2 clock domains letter in the present embodiment data interface module 11
Asynchronous docking processing has also been carried out between number.
As shown in Fig. 2, when data interface module 11 handles the access of parallel bus, under CLK clock domains, according to writing data
Enable signal WE and address signal Addr（The present embodiment width takes 4 bit）, capture the data-signal Data of write-in（This implementation
Example width takes 16 bit）；Or according to data enable signal RE and address signal Addr is read, data-signal Data is exported；
Busy signal（Busy）Represent that data interface module 11 is in other modules in asynchronous docking operation or IP kernel and just locates when effectively
In working condition, therefore read-write operation is sent out in Busy invalidating signals.
In the present embodiment, JTAG modular converters 12 specifically include the processing unit 121 of interconnection（Processor units）
And status control unit 122（StateCtrl units）, processing unit 121 according to tune-up data be configured JTAG protocol signal,
Status control unit 122 generates corresponding JTAG protocol signal according to the configuration of processing unit 121 and controls data as JTAG.Processing
Unit 121 be specifically handle from data interface module 11 synchronize after address date, carry out address decoding after configuration JTAG association
Discuss signal.
In the present embodiment, processing unit 121 include for be configured JTAG protocol signal state control register, be used for
The shift count register of serial data shift count in configuration JTAG protocol, for specifying the link attribute of serial data and control
The command register of log-on data transmission processed and the read-write buffer register for caching reading, write-in data, pass through and are configured
Above-mentioned each register configuration JTAG protocol signal.The present embodiment processing unit 121 specifically sets control register（Control is posted
Storage）, shift count register（Count registers）, read buffer register（ReadBuffer registers）, Write post deposit
Device（WriteBuffer registers）And command register（Command registers）Totally 5 registers, the width of each register
It spends for 16 bit, according to each register of address decoding data configuration of data interface module 11, by above-mentioned 5 registers
Difference configuration, can control and generate different JTAG signals.Each register is specially：
Control register（Control registers）：Clock in JTAG protocol can be controlled by the way that the register is configured
（TCK）The stable low level of unlatching, closing or output or high level；State of a control signal（TMS）Opening and closing；Control
Serial data output signal processed（TDO）Unlatching, the stable low level of closing, output or high level, output valid data；
Shift count register（Count registers）：Serial number in JTAG protocol can be specified by the way that the register is configured
According to the number of displacement, wherein the present embodiment is set as maximum and supports 65536 displacements；
Read buffer register（ReadBuffer registers）：The register is used to cache the 16 bit data once read,
And it is read-only register；According to the difference of address configuration, the source for reading data can be other registers in processing unit 121
Data in value or storage buffer module 14；
Write post register（WriteBuffer registers）：The register is used to cache 16 bit data of write-once,
And it is read-only register；According to the difference of address configuration, the target for writing data can be other registers in processing unit 121,
It can also be storage buffer module 14；
Command register（Command registers）：JTAG can be controlled to handle institute in IP kernel 1 by the way that the register is configured
When having the warm reset of module, and controlling reset, the JTAG reset signals of output（TRST）Also it can be in and reset effective status；Pass through
The data that the register also is able in control selections JTAG protocol are configured（DR）Link or instruction（IR）Link can be controlled and be opened
The transmission of a dynamic JTAG serial data and the frequency that tck clock can be configured.
Different JTAG protocol signals can be flexibly configured come control targe chip by the configuration of above-mentioned a variety of registers,
Flexibility and the controllability of artificial debugging are increased, while the setting of register also complies with the use habit of embedded system, because
And it is easy to implement integrated.
When the present embodiment processing unit 121 is configured, by configuration control register or command register to be configured to
JTAG protocol signal Static output state or according to read-write operation type by the way that control register is respectively configured, shift count is posted
Storage, command register and read-write buffer register are to be configured to JTAG protocol signal dynamics data mode.It is quiet that signal is configured
When state exports, by the way that Control registers or Command registers is configured so that TMS, TDO and TRST signal of JTAG is defeated
Go out the dead level for keeping stable or maintain high-impedance state, which is applied to particular demands pattern；When dynamic data is configured, lead to
Cross be configured above-mentioned each register jtag interface is correctly effectively exported, input data, the configuration be applied to normal work
Operation mode.
Dynamic data is configured as shown in figure 3, Control registers are configured according to demand first in the present embodiment, specifies JTAG
Data output source be data or steady state value from write-in；Then be configured Count registers, specify serial date transfer or
The number of output；Restart Command registers, specify the link attribute of serial data, and start a data manipulation, specifically
Including：
When using read operation, first configuration starts a data manipulation so that JTAG processing IP kernels 1 enter data transmission shape
State, and the data transmitted can keep in storage buffer module 14；After Busy invalidating signals, ReadBuffer registers are configured,
Data from storage buffer module 14 are read, when multiple data are read, then need that ReadBuffer registers repeatedly are configured；
When using write operation, WriteBuffer registers are first configured to write data into, the data of write-in can be kept in
It stores in buffer module 14；Then after configuration starts a data manipulation so that JTAG processing IP kernels 1 enter data transmission shape
State exports the data stored in buffer module 14；After Busy invalidating signals, restart write operation next time, multiple data
During write-in, then need that WriteBuffer registers repeatedly are configured.
In the present embodiment, status control unit 122 includes TMS state machines, and TMS state machines are controlled according to TAP in JTAG protocol
The sequential of device state machine processed generates JTAG protocol signal, i.e., TMS state machines are with reference to the TAP in JTAG protocol（Test Access
Port, test access port）The sequential of controller state machine performs, it is thus possible to be deposited according to Control in processing unit 121
The different configurations of device and Count registers, generate a variety of different TMS, TRST and TDO signal（JTAG protocol signal）, and
It is exported in the form of meeting 1149.1 standard agreements of IEEE under tck clock domain.
In the present embodiment, after a data manipulation is started, status control unit 122, which receives, starts order, starts internal
TMS state machines, TMS state machines can be selected according to the configuration in Command registers through IR command links or DR data
Link completes the conversion of entire state according to JTAG protocol, i.e. state conversion meets the requirement of JTAG standard agreement；Work as state
In displacement（Shift-State）During state, the status signal of data displacement can be generated（Data_Shift）And it is sent to data
Modular converter 13 notifies it to start data displacement.
Data are write in the present embodiment storage buffer module 14 specific data cache interface module 11 output, to be transferred to data
Modular converter 13 handled and data cached modular converter 13 export data, be transferred to data interface module 11 into
Row processing, writes data so as to what data cache interface module 11 was sent, and be transferred to data conversion module 13 and handle, also can
It reaches the data that data cached modular converter 13 is sent and is transferred to data interface module 11 and handle.Storage buffer module 14 works as data
After writing completely, then signal notice follow-up data pause write-in is sent out.The present embodiment is based on parallel bus, thus can be believed by Busy
Number come perceive storage buffer module 14 state.
In the present embodiment, storage buffer module 14 specifically includes a single port RAM body and storage control, wherein
The data width of RAM bodies specifically takes 16 bit, depth to take 2K, and sets the maximum storage for supporting 32Kb data.
In the present embodiment, data conversion module 13 includes read-write shift register, counter and for controlling and storing
Buffer module（14）Between data transmission transmission control unit, read-write shift register by counter controls perform read-write data
Serial shift transmit to complete data serioparallel exchange.As shown in figure 4, the present embodiment specifically includes 2 shift registers
（ShiftReg）, the counter of 1 16（Counter16）And 2 transmission control function units（Transfer
Function）, by the serial shift that 2 shift registers are each responsible for processing reading data and write data transmits, counter is used for
Serioparallel exchange, the transmission control function unit of control read-write data control shift register and store the number between buffer module 14
According to interaction.
In the present embodiment, the shift signal of the transmission of read-write shift register reception state control unit 122, sampling input number
Shifting function is carried out according to TDI and exports enabling signal to counter；Counter receives the enabling signal of read-write shift register
It starts counting up, output count completion signal extremely transmits control function unit after the completion of counting；It transmits control function unit and receives meter
Signal is counted up into, control will write data in shift register and read or be written storage buffer module 14, and control startup next time
Displacement, until shift signal is invalid.
The serial shift of the execution reading and writing data of data conversion module 13, which transmits, is specially：
When data are read, after the reading useful signal that processing unit 121 is sent is received, according to status control unit 122
The Data_Shift shift signals sent read shift unit Read ShiftReg and start to work, and sampled data TDI is simultaneously shifted
Operation；Start counter Counter16 simultaneously to start counting up, after the completion of counting 16 times, send out count completion signal.Transmission control
It is after functional unit Transfer Function receive count completion signal, the data write-in storage in shift register is slow
In die block 14, and control and start again at displacement；After the above process is continued until Data_Shift invalidating signals, counter stops
It only counts, displacement stops therewith；
When writing data, after writing useful signal receive that processing unit 121 sends, according to status control unit 122
The Data_Shift shift signals sent write shift unit Write ShiftReg start-up operations, carry out shifting function and by data
TDO is exported；Start counter Counter16 simultaneously to start counting up, after the completion of counting 16 times, send out count completion signal；Transmission
After control function unit Transfer Function receive count completion signal, read from storage buffer module 14 next
A parallel data is put into shift register, and is controlled and started again at displacement；The above process is continued until that Data_Shift believes
Number invalid, counter stops counting, and displacement stops therewith.
Entire shifting process is controlled by Data_Shift shift signals in the present embodiment data conversion module 13, therefore is shifted
Data TDI and TMS work in coordination, thus meet JTAG protocol.
The present embodiment JTAG handles IP kernel 1 and is realized especially by a set of Digital Logical Circuits, the above-mentioned entire logic of IP kernel
Realized using hardware description language, without rely on entity circuit board realize emulator function, can easily be integrated into FPGA,
In the design of the chips such as ASIC, it is easy to use and is configured.
Above-mentioned only presently preferred embodiments of the present invention not makees the present invention limitation in any form.It is although of the invention
It is disclosed above with preferred embodiment, however it is not limited to the present invention.Therefore, it is every without departing from technical solution of the present invention
Content, technical spirit any simple modifications, equivalents, and modifications made to the above embodiment, should all fall according to the present invention
In the range of technical solution of the present invention protection.
Claims (9)
1. a kind of simulator based on JTAG protocol, it is characterised in that：At parallel bus interface, jtag interface, JTAG
Manage IP kernel（1）And the interface conversion unit for interface logic conversion, the JTAG handle IP kernel（1）One end pass through it is described
Parallel bus interface, interface conversion unit connection debugging host, the other end are described by the jtag interface linking objective chip
JTAG handles IP kernel（1）The tune-up data of debugging host is received by the parallel bus interface, interface conversion unit, is converted to
It is exported after JTAG control data by the jtag interface to objective chip and the JTAG and handles IP kernel（1）By described
Jtag interface receives the JTAG data of objective chip, is converted to after the data for meeting parallel bus protocol through the parallel bus
Interface, interface conversion unit are exported to debugging host；
The JTAG handles IP kernel（1）Including the data-interface mould for being used to receive parallel debugging data, export parallel artificial data
Block（11）, for perform JTAG protocol conversion JTAG modular converters（12）, data conversion for performing data serioparallel exchange
Module（13）And the storage buffer module for being cached to data（14）, the data interface module（11）Pass through institute
State JTAG modular converters（12）With the data conversion module（13）Connection, the storage buffer module（14）Respectively with the number
According to interface module（11）, data conversion module（13）Connection.
2. the simulator according to claim 1 based on JTAG protocol, it is characterised in that：The JTAG modular converters
（12）Processing unit including interconnection（121）And status control unit（122）, the processing unit（121）According to institute
State tune-up data configuration JTAG protocol signal, the status control unit（122）According to the processing unit（121）Configuration production
Raw corresponding JTAG protocol signal controls data as JTAG.
3. the simulator according to claim 2 based on JTAG protocol, it is characterised in that：The processing unit（121）
Including being used for the control register for the state for being configured JTAG protocol signal, for serial data shift count in JTAG protocol to be configured
Shift count register, for specify the link attribute of serial data and control log-on data transmission command register, with
And for caching the read-write buffer register for reading, being written data, by the way that above-mentioned each register configuration JTAG protocol signal is configured.
4. the simulator according to claim 3 based on JTAG protocol, it is characterised in that：The processing unit（121）
During configuration, by configuration control register or command register to be configured to JTAG protocol signal Static output state or root
It is posted according to read-write operation type by the way that control register, shift count register, command register and read-write buffering is respectively configured
Storage is to be configured to JTAG protocol signal dynamics data mode.
5. the simulator based on JTAG protocol according to Claims 2 or 3 or 4, which is characterized in that the state control
Unit（122）Including TMS state machines, the TMS state machines are generated according to the sequential of TAP controller state machine in JTAG protocol
JTAG protocol signal.
6. the simulator according to claim 5 based on JTAG protocol, it is characterised in that：When data manipulation of startup
When, the status control unit（122）The TMS state machines started inside order startup are received, the TMS state machines are according to
Processing unit（121）Configuration carry out state conversion according to JTAG protocol, and when state be in displaced condition, generate data shifting
The status signal of position is sent to data conversion module（13）.
7. the simulator based on JTAG protocol according to any one in Claims 1 to 4, it is characterised in that：It is described
Data conversion module（13）Including read-write shift register, counter and for controlling and the storage buffer module（14）It
Between data transmission transmission control unit, the read-write shift register by the counter controls perform read-write data it is serial
Shift transport.
8. the simulator according to claim 7 based on JTAG protocol, it is characterised in that：The read-write shift register
Reception state control unit（122）During the shift signal of transmission, sampling input data carries out shifting function and exports enabling signal
To the counter；The enabling signal that the counter receives read-write shift register starts counting up, output meter after the completion of counting
Signal is counted up into the transmission control function unit；After the transmission control function unit receives count completion signal, control
System reads data in read-write shift register or write-in stores buffer module（14）, and startup is controlled to shift next time, until
Shift signal is invalid.
9. the simulator based on JTAG protocol according to any one in Claims 1 to 4, it is characterised in that：It is described
Store buffer module（14）Including single port RAM bodies and storage control.
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| CN107688528A (en) * | 2016-12-23 | 2018-02-13 | 北京国睿中数科技股份有限公司 | The debugging system and method for processor under simulation model |
| CN107122304B (en) * | 2017-05-03 | 2021-03-23 | 成都定为电子技术有限公司 | JTAG remote debugging method |
| CN109426594A (en) * | 2017-08-25 | 2019-03-05 | 深圳市中兴微电子技术有限公司 | A kind of chip debugging apparatus, method and computer readable storage medium |
| CN107608846B (en) * | 2017-08-30 | 2020-09-29 | 西安微电子技术研究所 | Debugging link and debugging method for embedded TAP interface of FPGA |
| CN108519953A (en) * | 2018-04-17 | 2018-09-11 | 长沙景美集成电路设计有限公司 | A kind of GPGPU debugging techniques realization based on JTAG |
| CN110659037B (en) * | 2019-09-25 | 2021-03-09 | 苏州浪潮智能科技有限公司 | JTAG-based burning device |
| CN111858415B (en) * | 2020-07-30 | 2024-03-15 | 超越科技股份有限公司 | Multi-channel multi-protocol hardware acceleration method for data receiving and storing |
| CN114035472A (en) * | 2021-11-09 | 2022-02-11 | 阳光学院 | Method and terminal for on-line programming of embedded programmable controller by CAN bus |
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