TW410300B - Detection method for the storage capacity of high speed cache - Google Patents

Abstract

The present invention relates to a detection method for the storage capacity of high speed cache, which can detect the storage capacity of the high speed cache including the L1 cache embedded in processor and the L2 cache in computer systems. The method provides more than one data with different size of data bytes ranging from possibly the minimum storage capacity to the maximum storage capacity of high speed cache. By means of the apparently distinct nature of reading speeds of processor in reading the data located in the high speed cache and main memory respectively, the average reading time (or reading speed) per unit data is recorded and the data bytes read during each read cycle are further calculated when the processor is reading a data with known size. The data bytes can be represented as the storage capacity in compliance with the reading speed of the cache (L1 cache or L2 cache).

Description

41030C V. Description of the invention (1) [Scope of application of the invention] The present invention relates to a method for detecting the capacity of a cache memory, especially a computer system command for detecting the speed of a computer system. The buffer memory) includes a first-level buffer cache (LI Cache) and a second-level buffer cache (L2 Cache). [Technical background of the invention] A current cache structure (Cach ^) is installed in the current computer structure between the Processor and the main meinory to improve the data access speed of the processor. It has long been known, and this type of cache memory (Cache) also includes: built-in processor

Cache),. ^ #, (L2 Cache), the hardware block diagram of which is shown in "Figure 2"; the secondary cache in the basin, a2 Cache) 3, is larger than the first-level cache storage 1. CacheWO Much more, and under normal operating conditions, the u cache access speed is usually 1 times faster than the L2 Cache 30, and the u 30 access speed is usually 4 times faster than the main memory (main memory). 3 ~ 5 times, so it has obvious help in improving the access speed of processor 10. So ’’s Cache working? What is the actual available storage capacity? For computer makers or users, it is not important now, especially for computer makers, which is more important. For OEM computer makers, we mainly assemble parts provided by computer peripheral chip makers. -Complete computer products. Only by holding the specifications and quality of Cache can we produce high-quality computer products.

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41030C V. Description of the invention (2) Otherwise, it will not only affect the goodwill, but also damage the rights and interests of unsuspecting consumers. The known methods for detecting the capacity of the cache are mostly obtained from the address space of the peripheral component connection interface PCI (Peripheral Component Interconnect), and the value on the PCI is the basic round-in / round-out system BIOS The (Basic Input / Output System) program is set according to the detection and has not passed the cache performance test. Although in Intel Pentium II and above computers, Intel provides a command (CPUID) to obtain the cache size. However, this method still uses the value set by BI 0S. If the value set by B 10S is incorrect, then use The cache capacity obtained by this method is incorrect. For example: In a practical situation, the L2 Cache in a computer is not completely installed, and only the L2 Cache tag module is installed (in general, the L2 Cache should include a tag module and a data module), However, through the method of description, BI 0 S will still think that there is a certain size of Cache, which will cause a broken error. Therefore, there are the following disadvantages in the way to obtain the cache capacity: 1. Poor applicability: because it must be obtained by reading the address space where PC I is located, but because the read address of the chip that controls the L2 cache will vary depending on the manufacturer And there are different read ends (Pin), so the method of obtaining the address space will be different. Unless the application is well aware of the technical content of this chip, it will cause difficulties in obtaining, so this method is usually only applicable to some Manufacturer-specific products. 2. Inaccurate: This method cannot be used to judge the correct cache capacity when L2 cache is lacking.

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3. Cannot detect the capacity of the LI Cache: Since the current cache control chip can only control the L2 Cache ', and the address space on the PCI only sets the capacity value of the L2 Cache', the capacity of the L1 cache cannot be detected . [Objective and Summary of the Invention] The object of the present invention is to provide a predicate measuring method that can correctly detect the storage capacity of buffer caches (including LI Cache and L2 Cache) at all levels in the cache. The method disclosed in the present invention mainly reads L1 according to the processor

Cache, L2 Cache and main memory (Memory) data ’have significantly different read speed characteristics, track the length of time it takes the processor to read data of different sizes, and further determine the size of the cache capacity. Another object of the present invention is to provide a method for detecting the storage capacity of the L1 Cache. According to the technology disclosed in the present invention, the reading speed of the data read by the processor is recorded as a graph, and the reading speed can be: reading time / unit size (time / Kbytes) and unit size (Kbytes) The graph is composed of two coordinate axes (such as "Figure 2-1"), or it can be composed of the read data size / time (Kbytes / time) and time (time) respectively. (Such as "Figures 2-4"); find out where the reading speed has changed significantly, and use the method of calculating the graph area of the curve 'to calculate the reading during each reading speed The size of the data, and this data size represents the speed that meets this read speed

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The capacity of Che (may be U Cache or L2 Cache). [Illustration of the diagram] The picture of kinky 1 is a hardware block diagram between the computer, L1 C a c h e, L 2 C a c h e and the main memory in the computer system. 2 1 'is a record of the processor, L1 C a c h e, L 2 in the computer system.

A graph of the cache and main memory data access speeds. Figures 2 to 2 are graphs that record the data access speed of the computer system's processor, u cache, and main memory. Figures 2 to 3 are graphs that record the data access speed of the processor, [2 Cache, and main memory in the computer system. Figures 2 to 4 show the processor, l 1 in another recording computer system.

Curve of data access speed of Cache, L2 Cache and main memory "^ 3" is a flowchart of the method steps of the present invention β ^ 4 "is a flowchart of the execution procedure of the embodiment of the present invention. Fig. 5 'is a detailed flowchart of the partial execution procedure of Fig. 4. Figure 6 'shows the data structure stored in LI Cache, L2 Cache, and main memory. Regarding the technical content and embodiments of the present invention, the description with reference to the content of the drawings is as follows. [Detailed description of the invention] Please refer to "Figure 2-1", as mentioned above, due to the difference in hardware design of LI Cache 20 'L2 Cache 30 and main memory 40, the processor 10 (CPU, Central Processing Unit)

41030C V. Description of the invention (5) The time taken for beer to store data of the same size in LI Cache 20, L2 Cache 30, and main memory 40, respectively; for example, in a Pentium II computer with a frequency of 266MHZ, The processor reads [I Cache 20 at approximately 2.9 MB / s, the L2 Cache 30 is approximately 240 MB / s', and the main memory 40 is approximately 120 MB / s . Now assume that the storage capacity of L1 Cache 2 in a computer system is 16K (including 8K Data Cache and 8K Instruction Cache), and the capacity of L2 Cache 30 is 1 2 8 1 2 8 K ° If the size of the read data gradually increases with the increase of the operating time, and when the size of a certain data read just exceeds 8K and 128K, the processor 10 sees that it needs to read each Kbytes of data There will be a sudden increase in time (that is, the reading speed will drop suddenly) 'and as shown in "Figure 2-1", under the normal conditions of LI Cache 20 and L2 Cache 30, read The speed change will inevitably have a jumping curve where the size of the read data reaches 8 K and 1 2 8 K. When the size of the read data exceeds 8K (the capacity of the LI Data Cache), the processor 10 will read from the L2 Cache 30 again, so the read speed when reading the LI Cache 20 (line 201) ' It will be different from the speed when reading L2 Cache 30 (line 301). Similarly, in the above example, if the size of the read data exceeds 1 28K (that is, exceeds the storage capacity of L2 Cache 30), the reading speed of the processor 10 will be due to reading the data of the main memory 40 , And there is another change (line segment 40 1). Therefore, according to this characteristic, the reading speed of the recording processor 10 at different times is determined. Then, the size of the data read at each reading speed is found.

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41030G V. Invention description (6) means the storage capacity of the cache (may be LI Cache or L2 Cache) that meets this read speed. On the other hand, "If the L2 Cache 30 is abnormal, the recording curve chart at this time" may be as shown in "Figure 2-2". There will be no line segments that conform to the read speed of the L2 Cache 30. Only the representative Recording line segments of the read speed of U Cache 20 and main memory 40, so we can judge that L2 Cache 30 may be faulty; otherwise, if LI Cache 20 is abnormal, the record curve chart at this time may be like " As shown in Figure 2—3, there will be no line segments that conform to the read speed of LI Cache 20, but only the record line segments that represent the read speed of L2 Cache 30 and main memory 40, so we can judge L2 Cache 30 may be malfunctioning. Please refer to "Figure 3", which is a flowchart of the steps of the method of the present invention. The disclosed steps include: 1 _ establishing a database containing a number of data sizes (DataBy, tes) are different from each other Data ', and the size of these data covers the possible values of the general cache from the minimum storage capacity to the maximum storage capacity; 2 makes the processor 10 read each piece of data in the database (or according to the size of each piece of data, from small And big or arrogant and small read each piece of data in the database in sequence) 3. The reading speed of the record processor to read each piece of data becomes a reading speed record table; 4. Get in each kind The data size (Date Bytes) read during the read speed becomes a read speed-capacity comparison

410300 V. Description of the invention (7) table, as shown in "Table 4"); [It can also be regarded as recording content according to the chart of "Figures 2-1 to 2-4", to find out where the reading speed occurred The size of the data corresponding to the obvious change] 5. Set the storage capacity of the cache that meets the read speed to the size of the data read during the read speed (you can also find the capacity according to the read speed-capacity comparison table Capacity corresponding to the read speed), and this data size is the storage capacity of the cache (may be LI Cache 20 or L2 Cache 30) that meets this read speed. The implementation method of step 1 can be as shown in "Table 1", and a data-size (Data-By tes) comparison table is created. Each data of different size is assigned a data serial number (SN, Serial Number). And a data size value (DS, Daΐa S ze) corresponding to this data serial number SN is used to specify the data size (Data Bytes) of each piece of data. The implementation of step 2 can be achieved by causing the processor 10 to read the data in an actual address according to the data size value DS specified in the aforementioned "Table 1"; for example, to read 64 Kbytes data, you can Just let the processor 10 read the data in the addresses 00000 ~ FFFFH, see "Figure 6". The reading speed record table referred to in step 3, if it is expressed in the form of a chart, can be as "Figure 2-1 to Figure 2-4", if it is expressed in the form of data, it is as "table "2, 3", in which "Table 2" records the data size (K, Kbytes) that the processor 10 has read (system

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41030C V. Description of the invention (8) ^ is the cumulative value) and the corresponding reading speed value (Time / K, representing the time required to read each K data); "Table III J records the reading speed value ( K / T ime, which represents the size of the data read per unit time) 'and the read time corresponding to the value of the reading speed. The size of the data to be obtained in step 4 can be calculated according to the values of Table 2 and 2. Take the value of "Table 2" (both hypothetical values) as an example. 'For example, in several records with a reading speed = 0.5 sec / K (Kbytes)', the cumulative read data size is 8K. The amount of data. Similarly, if the calculation is based on the curve recorded in "Figure 2-1", it can be more easily found that the read speed is almost the same before the accumulated data size is 8 K, which represents the read of LI cache 20. Take the speed curve, and the cumulative value of 8K is the capacity of LI Cache 20. If it is obtained from the recording curve of "Figures 2-4", the cumulative reading time at the first reading speed changes significantly is time 1 (that is, the maximum reading time value at this reading speed) ), Multiply timel by the corresponding reading speed value Kl / Time, and the resulting graphic area K1 is the storage capacity of U Cache 20. [Explanation of the embodiment] The method of the present invention can be understood through the following example descriptions. 'Assume that the error storage capacity of a computer system L1 C ache 2 0 is 32 feet (including ΠK Date Cache, 16K Code Cache), For the data storage, please refer to "Figure 4". According to the technology disclosed in the present invention, the implementation process is implemented in a level 1 buffer memory 20 (L1 Cache) including the processor 10 and the internal processor. ), Secondary buffer storage g

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41030C Description of the Invention (9) The computer system of the device 30 (L2 Cache) and the main memory 40 is implemented by performing the following steps, including: 1 Detecting the current computer system operating mode; [Generally, in There is a control register named CR〇 for processors 8 0486 and above, which controls the current state of the computer system. A processor state is set in processors 10 for processors below 8 0 8 8 Word Register (MSW, Machine Status Word). By detecting the logic level of the PE (Protect Enable) terminal in CR0 or MSW, the current state of the processor 1 can be judged. If PE = 1, it means that it is in protection mode, otherwise if PE = 0, Represents the real address mode (Reai Address Mode). ] 2 · Initialize the detection environment; 3 · Detect the cache capacity; 4 · Output the detection results; and 5 · End the detection process. Step 1 also includes: 1 -1 ‘Check out the current operating mode of the computer system; and 2. 2. Determine whether it is the real address mode? If not, it prompts the user to reset to the correct operating system of the computer system. Then skip to step 5 'If yes, continue to step 2 Q. Step 2 of this step also includes: 2 -1 · Store the current interruption status of the computer system To disable all interrupt operations; and

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41030C V. Description of the Invention (I0) 2- 2 * Save the current working state of the Cache, Enable (Enable) [1

Cache 20 and L2 Cache 30 a Step 3 includes: 3- 1 'Create a data-size (Data-Bytes) comparison table (such as "Table 1"); 3 -2 · Let the processor 1 〇 read Take the data of the size specified in "Table 1" and calculate the reading time required to read each piece of data; 3- 3 · Calculate the time required to read each K (Kbytes) of data in each piece of data (Calculated based on the records in step 3-2); and 3-4 · Time taken by the analysis computer system to read each K (K bytes) of data (ie, the analysis read speed) 'Find L1 C ache and L 2

The size of the cache. Step 4 also includes: 4- 1, clearly shows the size of the cache (including LI Cache and L2

Cache capacity); 4-2 _Restore the initial state of the Cache; and 4-3 · Restore the original interrupted state of the computer system. Please refer to "Figure 5" again, which is another detailed execution process disclosed according to the execution procedure shown in "Figure 4", which includes: A. Initializing the detection environment; B. Detection processor 1 0 type; C * Judge if it is a Pent ium or higher processor? If yes, continue to the next step, otherwise, use the 8523 system timer flag.

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41030C V. Description of the invention (u) Time, then skip to step E; D · Use TSC register as timer to mark time; E · Set timer use flag; F · Load a data-size (D ata-B ytes) comparison table (such as "Table 1"); G · instruct processor 10 to read a certain piece of data specified in "Table 1"; (the purpose of this step is to make the data first be filled into the cache and the main memory In the body 40, in this way, the next time the same data is read, the processor will first read from the L1 Cache, or sequentially from the LI Cache, L2 Cache, or sequentially from the LI Cache, depending on the size of the data. Read data from the L2 Cache and main memory.) Η, use the timer to mark the start time; I · Make the processor 10 once again read the first data of the size specified in "Table 1"; J · Use the timer Marking the end time of the device; κ · Counting the time to buy the tribute from the t (time spent = end time-start time); L · instruct the processor 10 to read the next data specified in "Table 1"; Μ · Determine whether all the data specified in Table 1 have been readIf yes, continue to the next step; if no, skip to step F; NR • Calculate the time it takes to read each K (Kbytes) of data; and 0 • Calculate the storage capacity of the cache.

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41030C V. Description of the invention (12) As the rapid development of the computer, the access speed of the processor 10 is getting faster and faster, so in order to reflect the difference in read speed between the LI Cache 20 and L2 Cache 30, 8253 The system timer is not accurate enough for high-performance processors, so for the processors above the Pentium level, the present invention uses a temporary register (Register) called TSC (Time Stamp Counter) to record the read time. However, this kind of tsc register does not appear until the Pentium-class processor is released. Therefore, the preferred implementation is to use a TSC register as a timer for the processor above the Pentium class, and vice versa. Device, it uses the 8253 system timer. The embodiment disclosed above is only for exposing the technology of the present invention, and modifications and changes made by those who are familiar with this technology after understanding the technical means of the present invention should not depart from the technical scope of the present invention. [Effect of the invention] It can correctly detect the storage capacity of each level of buffer storage (including l 1 Cache and L2 Cache) in C a c h e. Good applicability 'According to the storage capacity detection method disclosed in the present invention, it is no longer necessary to be familiar with the performance of the L2 Cache control chip, and the storage capacity of the Cache (including the LI Cache and the L2 Cache) can be easily detected.

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41030C V. Description of the invention (13) The number i! 2 4 1 5 6 7 8 1 9 1 10 1 " Data size 2K 4K 8K 12K ΙΤβΚ 'Ρκκ Γ2 4K 28K 32K 48K Τ54K- (Bytes) Γ1 Γ1 Γ Γ1 Γ1 number i π ±: 15 18 19 (20 ^ 21 1 22 data size 80Κ 96Κ 112 128 160 192 224 256 3 20 3 84 1448 (Bytes) Κ Κ Κ Κ Κ κ κ κ number i 23 24. 25 26 29 30 ρτ ~ Data size 5 12 576 640 768 896 1M 2M 3M 4M (Bytes) LL Li_ L_J ___ L1 ___ J____ [Table 1]

[Table 4] ΙΜΜΜΪ C: \ Program Files \ Patent \ p-0177tw. Ptd page 16

41030C V. Description of the Invention (14) [Illustration of Symbols] 10 ............ * · Processor 20 ........ Level Cache (LI Cache) 3 0 ....... L2 Cache 40 ............. Main memory 201 ... Li Cache read speed record line segment 3 0 1 ... L2 Cache read speed record line segment 401 ... Main memory read speed record line segment

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Claims (1)

41030C VI. Application for patents -------- 1 · —A method for detecting the storage capacity of cache memory, using the cache memory in the system (including built-in — 1. The storage capacity of the processor—the level 1 cache (L1 Cache) and the level 2 cache (L2 Cache)), including: 1. Establish a database, the first of which contains several data sizes ( Data Bytes) are different from each other. The size of the majority of the data covers the possible value of the cache memory from the minimum storage capacity to the ^ large robust storage capacity; take 2 · make the processor read each data in the database A piece of data; 3 · Record the reading speed of each piece of data read by the processor to become a reading speed record table; 4 _ Get the size of the data (Date Bytes) read during each of the foregoing reading speeds' Become a reading speed-capacity table; and ~ 5 'Let the capacity of the local cache buffer that matches the reading speed be the size of the data read during the reading speed. ^ 2. The method for detecting the storage capacity of the buffer memory as described in item 1 of the scope of the patent application, wherein the database is a data-size comparison & table, which records: a data serial number (SN, Serial Numbe;), and a data size value (ds D ata S ize) corresponding to this data serial number M, is used to refer to the mother— 'Data Bytes of the data] (Data Bytes). 3. The storage office of the cache memory as described in item 1 of the scope of patent application In the patent application, the amount of data in the patent scope is the same as the amount of the application, such as the amount of the application has been read, the response should be the amount of the application, and the cache of the application. Read? 8 If the application volume is stored in the cache) If the application volume is detected in the 41030G method, where the step 2 is based on the small value of the data, the processor reads and stores the cache data in the cache. Data from the international address. The cache measurement method described in the third item of the patent scope 'wherein the processor is based on each of the data: read from small to large or big and small in order s The high-speed cache described in the first item of the patent scope Storage test method, where the reading speed record table is; record here: the size of the data (K, Kbytes) (accumulated value) and reading speed value (Time / K). The storage capacity measurement method of the cache memory described in item 5 of the patent scope, which allows the read speed value to represent at least one of the first-level cache (LI Cache) and the second-level cache (L2). Reading speed. The storage capacity test method of the cache memory described in item 1 of the patent scope 'its 1f7 the reading speed record table records the processing taking speed value (K / Ti me)' and the time corresponding to the reading speed value ( ti me). The storage capacity testing method of the cache memory according to item 7 of the patent scope, wherein the read speed value represents at least one of the first level cache (LI Cache) and the second level cache (L2). Speed ° The storage capacity measurement method of the cache memory described in the first item of the patent range, wherein the reading speed of the hybrid 4 41030 () 〇. C reading speed record ί recorded value calculated. Measurement method, wherein the cache storage is based on the reading speed-capacity pair: storage :: storage capacity value: the capacity value corresponding to the reading speed is the two-speed buffer memory Of the remaining storage capacity C: \ Program Files \ Fatent \ p-0177tw.ptd page 20