GB2345163A - Detecting capacity of cache memories - Google Patents
Detecting capacity of cache memories Download PDFInfo
- Publication number
- GB2345163A GB2345163A GB9828691A GB9828691A GB2345163A GB 2345163 A GB2345163 A GB 2345163A GB 9828691 A GB9828691 A GB 9828691A GB 9828691 A GB9828691 A GB 9828691A GB 2345163 A GB2345163 A GB 2345163A
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- Prior art keywords
- cache
- data
- reading
- capacity
- caches
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0646—Configuration or reconfiguration
- G06F12/0684—Configuration or reconfiguration with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3409—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
- G06F2201/805—Real-time
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
- G06F2201/88—Monitoring involving counting
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
- G06F2201/885—Monitoring specific for caches
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
A method of detecting the capacity of caches, including the L1 cache built into the CPU and any second level cache (L2) outside the CPU. The method uses a database with varying sizes of data files, and monitors the reading time of the CPU for each size of data file when reading the data from the L1 cache, the L2 cache or the main memory respectively. Because the reading speeds relating to the L1 cache, L2 cache and main memory are different, the capacity of the L1 and L2 cache can be determined by matching the change in reading speed to corresponding sizes of data files.
Description
METHOD FOR DETECTING STORAGE CAPACITY OF CACHE
The present invention relates to a method for detecting the storage capacity of a cache, and especially to a method utilized in a computer system for detecting the capacitv of caches, including the L I cache built in the CPU and any L2 cache outside the CPU.
In the current computer structure, a cache located between the CPU and the main memory is known as buffer means for fast data access of the CPU (central processing unit). As shown in FIG. 1, the cache generally includes a first leve ! (LI) cache 20 built inside the CPU 10 and a second level (L2) cache 30 mounted outside the CPU. The L2 cache 30 is much larger than the Ll cache 20. The access speed of Ll cache 20 is generally twice of the L2 cache 30 under normal operation. And, the access speed of the
L2 cache is 3 to 5 times of the main memory 40. So the caches are obviously useful for increasing the data access speed of the CPU 10.
Therefore, it is very important for computer manufacturers or users to make sure the cache can normally function and to verify the real data storage capacity of the cache.
Especially for those OEM (original engineering manufacturing) factories of computer who use processor components of third party to assembly the computers, the quality of the computer products relies on the quality and specifications of the caches. Unqualified cache not only ruins the reputation of the maker, but also harms the customer.
A prior method for detecting the capacity of cache is to read the space of address from the PCI (peripheral component interconnect). But the value on PCI is detected and set by the system software of BIOS (basic input/output system) instead of checking the performance of the cache. Though an instruction code CPUID is provided by Intel for
Pentium II or higher computer, it still uses the value from BIOS. If the BIOS value is not correct, the obtained cache value will still be wTong. For example, when an L2 cache of a computer is not well installed. but the tag module of the L2 cache exists (Note: Generally the L2 cache includes a tag module and a data module), then according to the aforesaid method, the BIOS will incorrectly interpret that there is the cache. The aforesaid method for obtaining the capacity of cache has the following drawbacks:
a) Low compatibility: Since the address space is read from PCI which will be at different pins for different cache chip products, the reading method will be different accordingly. Therefore, except for users who know the chip well, it is hard to obtain the information. And, the method is suitable only for some specific products.
b) Inaccuracy: The capacity of cache cannot be correctly checked, especially when the L2 cache is not well installed.
c) Cannot detect the LI cache: Since the current cache chip can only control the L2 cache, and the address space on PCI has only the capacity of L2 cache, the capacity of LI cache cannot be detected.
The object of the present invention is therefore to provide a method for detecting the storage capacity of cache, including the LI cache and the L2 cache.
The method according to the present invention is to monitor the reading time of the
CPU for specific size of data when the CPU reads data from the LI cache, the L2 cache or the main memory respectively.
Another object of the present invention is to provide a method for detecting the capacity of the LI cache.
According to the present invention, the computer will monitor the speed of the CPU during reading data. The reading speed can be illustrated as a line chart. The line chart is established by the speed (time/Kbytes; the time needed for reading per kilobytes) vs. the size of data (Kbytes) as shown in FIG. 2-1 ; or by the speed (time/Kbytes) vs. the time as shown in FIG. 2-4. By parting the line portions with their apparent different speed levels. and calculating the area under a line portion, the size of data read during that speed can be obtained. And, the reading size of data is the capacity of the cache (the LI or the L2 cache) under that reading speed.
The objectives and avantages of the present invention will become apparent from a detailed description provided below, with reference to the accompanying drainas.
FIG. I is a block diagram showing the hardware structure of CPU, L I cache, L2 cache and main memory of a computer system;
FIG. 2-1 is a line chart showing the reading speed (time per kilobytes) of the CPU of a computer during reading the L I cache, L2 cache and the main memory;
FIG. 2-2 is a line chart showing the reading speed of the CPU of a computer during reading the L 1 cache and the main memory;
FIG. 2-3 is a line chart showing the reading speed of the CPU of a computer during reading the L2 cache and the main memory;
FIG. 2-4 is a line chart showing the reading speed (kilobytes per time interval) of the CPU of a computer during reading the LI cache, L2 cache and the main memory ;
FIG. 3 is flowchart of the method according to the present invention;
FIG. 4 is a flowchart showing an embodiment of the present invention;
FIG. 5 is a detailed flowchart showing a partial process of FIG. 4; and
FIG. 6 a data structure diagram of data stored in the LI cache, L2 cache and main memory.
The structure of a computer in which the LI cache 20. L2 cache 30 and the main memory 40 incorporated with the CPU 10 is described above with FIG. 1.
Referring now to FIG. 2-1 or FIG. 2-4, since the hardware difference among the LI cache 20, L2 cache 30 and the main memory 40, when the CPU 10 reads data from the LI cache 20, L2 cache 30 and the main memory 40. the reading time will be relativelv different. For example, in a Pentium II, 266 MHz computer, the CPU 10 reads the LI cache 20 at a speed about 299 megabyte per second; reads the L2 30 cache at about 240 megabyte per second, and reads the main memory 40 at about 120 megabyte per second.
Now, supposing the capacity of the LI cache in a computer is 16 kilobytes (8 kilobytes of data cache and 8 kilobytes of instruction cache), the capacity of the L2 cache is 128 kilobytes. When the data size becomes larger, then at the size just over 8 kilobytes or 128 kilobytes, the reading time suddenly increases as shown in FIG. 2-1, i. e. the reading speed suddenly lowers as shown in FIG. 2-4. This is under the normal condition of the LI and
L2 cache that the reading speed obviously changes according to the capacities of the LI and L2 cache. Because when the data size exceeds 8 kilobytes of the capacity of LI cache, the CPU turns to read data from the L2 cache, so the reading time per kilobytes for data under 8 kilobytes (line 201) is different from the reading time per kilobytes for data over 8 kilobytes (line 301). In the same way, when the data size exceeds 128 kilobytes of the capacity of L2 cache, the CPU turns to read data from the main memory, the reading time per kilobytes for data under 128 kilobytes (line 301) is different from the reading time per kilobytes for data over 128 kilobytes (line 401). The CPU 10 always monitors the reading speed and records the vales, then it can figure out the data size, i. e. the capacity of the LI or L2 cache afterwards. The capacity Kl of Ll cache, for example in FIG. 2-4, is calculated by multiplying the speed S (Kbytes/time) with the time t3.
As shown in FIG. 2-2, if the L2 cache is abnormal or not installed, the L2 cache portion (line 301) will not appear in the line chart, i. e. only the line 201 of the L 1 cache, and the line 401 of the main memory exist. So, the abnormality of L2 cache can be detected.
On the contrary, if the LI cache is normal, as shown in FIG. 2-3, the LI cache portion (line 201) will not appear in the line chart. i. e. only the line 301 of the L2 cache. and the line 401 of the main memory exist. So, the abnormality of LI cache can be detected.
FIG. 3 is a flowchart showing the process of the present invention. The steps includes: 1) Establishing a database in which several data files with different size are included. The sizes of data cover the range of the capacity of common caches from their minimum to their maximum capacities;
2) Controlling the CPU to read every data files according to the database, for example, in a sequence of order from the smallest to the largest, or from the largest to the smallest one; 3) Recording the reading speed of the CPU when reading each data file;
4) Comparing the data sizes (bytes) and their corresponding reading speeds to form a matching table as shown in TABLE 4, i. e. finding out the data sizes where the reading speeds are obviously changed as shown in the Figs 2-1 to 2-4;
5) Obtaining the size of data read under a speed level as the capacity of the cache (the L I or the L2 cache), i. e. taking the corresponding data size of a specific reading speed in the TABLE 4.
An embodiment of step 1 is shown in TABLE 1. The table includes data serial numbers and their corresponding data sizes.
The implement of step 2 is to let the CPU read the data according to the real addresses corresponding to the L I cache 20. L2 cache 30 or the main memory 40 as shown in FIG. 6. For example, for a data file of 64 kilobytes. the CPU is assigne to read addresses from 00000 to FFFFH. During the reading, the 64k data are also filled in a part of the L2 cache (supposed it is of 256k capacity), and 16k of them are fulfill in the 16k data cache of the L I cache.
In step 3, the record of reading speed can be illustrated as shown in Fit, 2-1 to 2-4. or formed into a table as shown in TABLE 2 or TABLE 3. The TABLE 2 records the data sizes already read in corresponding time intervals. The TABLE 3 records the reading speeds (kilobytes per time interval) and the corresponding time they used.
In step 4, the speed levels as shown in TABLE 4 are obtained by checking the record of TABLE 2 or TABLE 3. For example, from TABLE 2, if the data size proportionally increase with the reading time till a size of 8 kilobytes, as shown in FIG. 2 1. then the capacity of the cache is 8 kilobytes. Or, from TABLE 3 or FIG. 2-4, if the reading speed remains at a fixed value S (kilobytes per time interval) till a certain time t3. then the capacity K1 of the cache is the speed S multiplied with the time t3.
TABLE 1. Index of data files
File 1 2 4 5 6 7 8 9 10 11
number
Size of data 2k 4k 8k 12k 16k 20k 24k 28k 32k 48k 54k (Kbytes)
File 12 13 14 154 16 17 18 19 20 21 22
number
Size of data 80k 96k 112 128 160 192 224 256 320 384 448
(Kbytes) k k k k k k k k k
File 23 24 25 26 27 28 29 30 31 number
Size of data 512 576 640 768 896 1M 2M 3M 4M
(Kbytes) k k k k k
TABLE 2: Data size and reading time Data size (Kbytes)1k 2k 3k 4k nk
Reading time t1 t2 t3 t4 tn TABLES 3: Reading speed and reading time Speed s S S S4 Sn (Kbytes/tim e)
Reading time t I t2 t3 t4 tn TABLE 4: Detection Result
Reading speed (bytes/sec) 299 MB/sec 240 MB/sec 120 MBlsec Reading capacity Reading capacity 8k 128k 32M
FIG. 4 is a flowchart showing an embodiment of the present invention. In a computer system, a CPU 10, an LI cache 20, an L2 cache and a main memory 40 are incorporated. A method for detecting the capacity of the LI and the L2 cache comprises the following steps:
1) Detecting the current operation mode of the computer. Generally in a 80486 or higher CPU 10, there is a"CRO"register for controlling the current status of the computer. In a CPU lower than 80486. there is a register for storing a machine status word (MSW). By detecting the logical level of the PE (protect enable) end of the CRO or MSW register, the current status of the CPU 10 can be obtained. If PE=I. it is in a"protect mode", otherwise PE=0, it is in a real address mode" ; 2) Initializing the detection environment ;
3) Detecting the capacity of the cache;
4) Outputting the detection result; and
5) Finishing the detection procedure.
The step 1 further includes the following steps: 1-1) detecting the current operation mode;
1-2) Checking if it is in real address mode, if not, instructing the user to reset the computer to a correct mode, then jumping to step 5; if yes, proceeding to step 2.
The step 2 includes the following steps:
2-1) Storing the interruption status of the current system, and forbidding any
interruption ; and
2-2) Storing the current operation status of the cache and enabling the L 1 cache 20
and the L2 cache 30.
The step 3 includes the following steps: 3-1) Establishing an index table (TABLE 1) of data files with different sizes : 3-2) Controlling the CPU to read every data file in the index table and recording the reading time of each data file;
3-3) Calculating the reading speed (time needed for per kilobytes) for each file according to the record of step 3-2 ; and 3-4) Analyzing the reading speed for different size files and obtaining the capacity of the LI and the L2 cache.
The step 4 includes the following steps:
4-1) Showing the capacity of the caches (LI cache and L2 cache);
4-2) Retrieving the initial status of the cache; and 4-3) Retrieving the original interruption status of the computer.
Further referring to FIG. 5, a detailed procedure according to FIG. 4 includes the following steps:
a) Initializing the detection environment ;
b) Checking the type of the CPU 10;
c) Judging if it is a Pentium or higher CPU, if yes, proceeding to the next step, or utilizing the 8523 system timer for time tag, and jumping to step e);
d) Using the TSC (time stamp counter) register for time tag of timer;
e) Setting the time tag of timer;
f) Loading an index table (TABLE 1) of files; g) Controlling the CPU to read a certain file in the table. This is to load the data into the cache and the main memory so that, upon reading the same data next time. the CPU can fast read the data directly from the LI cache. L2 cache and main memory according to the size of the data ; h) Getting timer tag when starting the timer;
i) Controlling the CPU to read the data file of the designated size agais : j) Getting the timer tag when stopping the timer;
k) Calculating the reading time of data, the time equals to difference of the ending tag and the starting tag; 1) Controlling the CPU to read the next data file in the table;
m) Checking if all the files are read. If yes, proceeding to next step, or jumping to step f) ; n) Calculating the reading time for per kilobytes; and
o) Calculating the capacity of the cache.
Since the fast development of computers, the access speed of CPU is getting faster and faster. For responding to the different reading speeds of the LI cache and the L2 cache, the 8253 system timer is not precise enough for higher CPU. Therefore, the present invention utilizes a TSC (time stamp counter) register for recording the reading time for a
Pentium and higher CPU. The TSC register is developed after the Pentium processor, so the 8235 system timer is still needed for the CPU lower than Pentium.
The advantages of the method according to the present invention are as follows :
a) Correct detection of the capacity of LI and 12 cache;
b) Easy procedure for detecting capacity of the L 1 and L2 cache without the need of being familiar to the performance of the control chip of L2 cache.
Although the invention has been described in connection with preferred embodiments, it will be understood by those skilled in the art that various changes may be made without departing from its scope.
Claims (10)
- CLAIMS I. A method utilized in a computer system for detecting capacity of caches. including an LI cache built in a CPU of said computer and an L2 cache outside said CPU. comprising steps of : 1) Establishing a database in which several data files with different size are included, said size of data covers a range from a minimum to a maximum capacity of a common cache;2) Controlling said CPU to read every data files according to said database; 3) Recording reading speed of said CPU when reading said data files ;4) Comparing data sizes and corresponding reading speeds to form a matching table of data sizes to reading speeds ; 5) Obtaining a size of data read under a specific reading speed as capacity of one of said caches.
- 2. A method for detecting capacity of caches according to claim 1 wherein said database comprises records of data serial numbers and data sizes corresponding to said numbers.
- 3. A method for detecting capacity of caches according to claim 1 wherein said reading procedure in step 2 is to let said CPU reading one by one a specific size of data in real addresses of said caches according to said database.
- 4. A method for detecting capacity of caches according to claim 3 wherein said reading procedure for reading each specific size of data is in a sequence taking from one of the following two manners: from minimum to maximum size. and from maximum to minimum size.
- 5. A method for detecting capacity of caches according to claim 1 wherein said recording procedure is to record data sizes already read and corresponding reading speeds of time needed for per kilobytes of data.
- 6. A method for detecting capacity of caches according to claim 5 wherein said corresponding reading speeds at least includes a reading speed of one of said LI and L2 caches.
- 7. A method for detecting capacity of caches according to claim I wherein said recording procedure is to record specific reading speeds of time needed for per kilobytes of data and corresponding reading time already used.
- 8. A method for detecting capacity of caches according to claim 7 wherein said corresponding reading speeds at least includes a reading speed of one of said Ll and L2 caches.
- 9. A method for detecting capacity of caches according to claim 1 wherein said matching table of data sizes to reading speeds in step 4 is calculated from said records of data sizes and corresponding reading speeds.
- 10. A method for detecting capacity of caches according to claim 1 wherein said capacity of a cache is obtained by finding out a size of data read under a specific reading speed according to said matching table of data sizes to reading speeds, said data size is then the capacity of said cache.11 A method for detecting capacity of caches, substantially as hereinbefore described with reference to and/or substantially as illustrated in any on of or any combination of the accompanying drawings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9828691A GB2345163A (en) | 1998-12-24 | 1998-12-24 | Detecting capacity of cache memories |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9828691A GB2345163A (en) | 1998-12-24 | 1998-12-24 | Detecting capacity of cache memories |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB9828691D0 GB9828691D0 (en) | 1999-02-17 |
| GB2345163A true GB2345163A (en) | 2000-06-28 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9828691A Withdrawn GB2345163A (en) | 1998-12-24 | 1998-12-24 | Detecting capacity of cache memories |
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| CN107851456B (en) * | 2015-08-10 | 2021-02-09 | 华为技术有限公司 | Memory card authentication method, mobile terminal and terminal equipment |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5511180A (en) * | 1993-04-06 | 1996-04-23 | Dell Usa, L.P. | Method and circuit for determining the size of a cache memory |
| US5513344A (en) * | 1993-11-10 | 1996-04-30 | Nec Corporation | Method of testing cache memories used for an information processing apparatus |
| US5831987A (en) * | 1996-06-17 | 1998-11-03 | Network Associates, Inc. | Method for testing cache memory systems |
-
1998
- 1998-12-24 GB GB9828691A patent/GB2345163A/en not_active Withdrawn
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5511180A (en) * | 1993-04-06 | 1996-04-23 | Dell Usa, L.P. | Method and circuit for determining the size of a cache memory |
| US5513344A (en) * | 1993-11-10 | 1996-04-30 | Nec Corporation | Method of testing cache memories used for an information processing apparatus |
| US5831987A (en) * | 1996-06-17 | 1998-11-03 | Network Associates, Inc. | Method for testing cache memory systems |
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| Publication number | Publication date |
|---|---|
| GB9828691D0 (en) | 1999-02-17 |
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| Date | Code | Title | Description |
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| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |