JP2004240783A - Simulator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a simulator capable of saving the system resources of a host to be simulated. <P>SOLUTION: A cache hit determination means 8 determines a cache hit when an access request address coincides with tag information stored in a tag information storage means 10 and a status bit in a status information storage means 11 is valid. When the cache hit determination means 8 determines the cache hit, an access time calculation means 9 counts the operation time of the access as access time to a cache memory model 2. Even when the cache is hit, an access means 12 accesses the information whose cache is hit with respect to a main memory model 1. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a simulator that reproduces the operation of an apparatus using a CPU for controlling hardware on a host such as a workstation.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, there has been a simulator that models the hardware of a target on a host such as a workstation, simulates (simulates) the operation of the CPU model, and integrates the time required for the operation of the target.
Such a simulator fetches instructions one by one from an instruction memory, executes the instructions one by one based on a result of analysis, and proceeds with a process of calculating a required time (for example, see Patent Document 1).
[0003]
FIG. 9 is a configuration diagram of a conventional simulator.
As shown in the figure, the simulator executes a main memory model 101 composed of a ROM model and a RAM model, a cache memory model 102 composed of a cache controller model and a RAM model, and an instruction stored in the main memory model 101. It comprises a CPU model 103 for interpretation and execution, and a counting unit 104 for measuring a simulation time required by the CPU model 103 and the like. The cache memory model 102 includes a first level (L1) cache memory model 105 (a first level (L1) cache memory model 105a for instructions and a first level (L1) cache memory model 105b for data) and a second level (L1) cache memory model 105b. (L2) The cache memory model 106 is used.
[0004]
In such a cache memory model 102, a cache information storage model 107 for simulating the operation of the cache memory is provided on the memory of the host. The cache information storage model 107 includes a tag 108 storing an address of the main memory model 101 corresponding to information (instruction / data) stored in the cache memory model 102, a state bit 109 indicating a cache state, It comprises a memory area 110 for storing information.
[0005]
The cache memory is managed in a unit called a line, and one line stores a plurality of bytes of information having a continuous address (here, a unit of 16 bytes). For example, when the values of the addresses 0x12345670 to 0x123456F are cached in the cache memory, the value of the tag 108 is 0x1234567, and the values from 0x12345670 to 0x123456F are cached in that line. The number of bytes per line can be set to an appropriate size in the initialization of the simulator. The line of the L2 cache memory is larger than that of the L1 cache memory.
The status bit 109 is set for each line, and indicates the status of the cache of the line such as valid, changed, or invalid.
[0006]
FIG. 10 is a flowchart showing the entire processing of the conventional simulator.
First, the CPU model 103 acquires an address of an instruction to be executed (step S101). Next, the cache memory model 102 is checked, an instruction acquisition time (penalty) is calculated, and the instruction is read (step S102). Thereafter, the command is interpreted and executed (step S103). At the time of execution, if data reading / writing is necessary, the cache memory model 102 is checked, a data acquisition time (penalty) is calculated, and data reading / writing is performed (steps S104, S105). Next, the time required for execution is calculated, and the cycle (simulation time) of the CPU model 103 is updated (step S106). Finally, the simulation end is determined (step S107).
[0007]
FIG. 11 is a flowchart showing a cache check process in a conventional simulator.
First, the tag 108 of the corresponding instruction or data L1 cache memory model 105a, 105b is searched (step S201), and it is checked whether there is a corresponding tag (step S202). If there is no corresponding tag in this step S202, the tag 108 of the L2 cache memory model 106 is searched (step S202). If there is no corresponding tag, a cache miss occurs. On the other hand, in step S202, if there is a tag in the cache memory model 102, that is, if there is a cache hit, the status bit 109 is checked (step S203). If a cache hit occurs, a penalty is calculated (step S204), instructions and data are read from and written to the memory area 110 of the corresponding cache memory model 102, and the status bit 109 is changed as necessary (step S205). If a cache miss has occurred, a penalty is calculated (step S206), instructions and data are read and written from the main memory model 101, and the contents, tags and status bits of the corresponding cached memory are updated (step S207). .
[0008]
[Patent Document 1]
JP 2001-249829 A
[0009]
[Problems to be solved by the invention]
However, in the above-described conventional simulator, the memory of the host to be simulated is used by the amount of the cache memory model, and there is a possibility that the system resources of the host may be squeezed.
Further, since the cache memory is checked every time, there is a problem that the operation speed as a simulator is reduced, and in particular, it takes much time to search for a tag.
[0010]
[Means for Solving the Problems]
The present invention employs the following configuration to solve the above-described problem.
A simulator according to the present invention is a simulator that simulates a program execution operation of an information processing device including a main memory, a cache memory, and an arithmetic processing device, and counts the operation time. Tag information storage means for storing, as tag information, address information of a main memory model that simulates the operation of a main memory corresponding to information stored in the model; information stored in a cache memory model; State information storage means for storing state information indicating a state of coincidence with information stored in the main memory model corresponding to the main memory model, and when an access request to the cache memory model is detected, the address of the access request is stored in the tag information storage means. And the status information in the status information storage means matches A cache hit judging means for judging a cache hit in the state, and an access time calculating means for counting an operation time of the access as an access time for the cache memory model when the cache hit judging means judges a cache hit And an access unit for accessing information in the main memory model when the cache hit determination unit determines that the cache hit has occurred.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail using specific examples.
<< Specific Example 1 >>
<Constitution>
FIG. 1 is a configuration diagram showing a specific example 1 of the simulator of the present invention.
The illustrated simulator includes a main memory model 1, a cache memory model 2, and a CPU model 3, and the cache memory model 2 includes an L1 cache memory model 4 (an instruction L1 cache memory model 4a, a data L1 cache memory model 4b), L2 cache memory model 5 is included.
[0012]
The main memory model 1 is a model that simulates the operation of a main memory including a ROM model and a RAM model. The instruction L1 cache memory model 4a and the data L1 cache memory model 4b simulate the operation of the L1 cache memory composed of a cache controller and a RAM. The L2 cache memory model 5 is a model that simulates the operation of the L2 cache memory. The CPU model 3 is a model that simulates the operation of an arithmetic unit that interprets and executes instructions stored in the main memory. Although the counting section is also provided in this specific example, the description is omitted here because it has the same configuration as the conventional one.
[0013]
The cache memory model 2 includes a cache controller model 6 and a cache information storage model 7. The cache controller model 6 is a model that simulates the operation of the cache controller, and includes a cache hit determination unit 8 and an access time calculation unit 9. The cache information storage model 7 is for simulating cache information such as a tag and a state bit of a cache memory, and includes a tag information storage unit 10 and a state information storage unit 11.
[0014]
The tag information storage means 10 has a function of storing, as tag information, address information of the main memory model 1 corresponding to information (instruction / data) assumed to be stored in the cache memory model 2. The state information storage means 11 stores state information (state bits) indicating a matching state between the information stored in the cache memory model 2 and the information stored in the main memory model 1 corresponding to this information. Has a function. That is, in this specific example, the cached memory is not mounted, but the tag and the status bit are set as mounted. For example, if the length of the line is 16 and the value of the tag is 0x1234567, it is considered that the values of the addresses 0x12345670 to 0x1234567F are cached in the line. The number of bytes per line can be set to an appropriate size in the initialization of the simulator. The status bit is set for each line, and indicates a status such as a valid / changed / invalid state of the cache of the line. The "changed" status bit indicates that the data held in the cache memory has been changed, and is a status bit for the CPU to determine whether or not to write back to the main memory. It is.
[0015]
When the cache hit determination means 8 detects an access request from the CPU model 3 to the cache memory model 2, the address of the access request matches the tag information stored in the tag information storage means 10 and the state information storage When the status information of the means 11 is in a coincidence state, it has a function of determining a cache hit. The access time calculation means 9 has a function of counting the operation time of the access as the access time to the cache memory when the cache hit determination means 8 determines that the cache hit has occurred.
[0016]
Further, the simulator of this specific example includes an access unit 12. The access unit 12 has a function of accessing the main memory model 1 with information on the cache hit when the cache hit determination unit 8 determines that the cache hit has occurred.
[0017]
<motion>
Next, the operation of the specific example 1 will be described.
Since the basic flow of the entire process in the specific example 1 is the same as the conventional operation shown in FIG. 10, the description is omitted here and the cache check process will be described.
FIG. 2 is a flowchart of a cache check in the first specific example.
First, the tag in the tag information storage unit 10 of the corresponding L1 cache memory model 4 is searched (step S1), and it is checked whether there is a corresponding tag (step S2). If not, the tag of the L2 cache memory model 5 is searched. Otherwise, a cache miss will occur. If there is a tag in the cache memory, that is, if there is a cache hit, the status bit in the status information storage means 11 is checked (step S3). If not, the cache hit determination means 8 determines that there is a cache hit. If a cache hit has occurred, the access time calculation means 9 calculates the information acquisition time (penalty), and changes the tag and the status bit as necessary (step S4). If a cache miss has occurred, the information acquisition time (penalty) is calculated, and the tag and the status bit are changed as necessary (step S5).
[0018]
Next, regardless of a cache hit or a cache miss, the access unit 12 reads or writes an instruction or data from the main memory model 1 (step S6). Here, in the case of a cache hit, since the data in the main memory model 1 and the data in the cache memory model 2 are matched in the case of writing, reading of an instruction or reading / writing of data from the main memory model 1 is performed. Assume that only a penalty is hit in the cache memory. That is, the access time calculation means 9 notifies the CPU model 3 of the access time in the case of a cache hit, and does not calculate the time actually accessed by the access means 12 as the access time. These access times are determined in advance by the access time calculation means 9 based on whether a cache hit occurs in the L1 cache memory model 4 or a cache hit occurs in the L2 cache memory model 5.
[0019]
In the case of such an operation, in the case of the simulator, since the cache memory model is actually developed on the main memory similarly to the main memory model 1, the data access operation itself is almost the same between the cache memory and the main memory. This is because they can be regarded as similar.
If a cache hit occurs during data writing, the data is written to the main memory model 1, but its status bit is "changed". As a result, a simulation similar to that of an actual cache memory can be performed.
[0020]
On the other hand, in the case of a cache miss, data access from the L1 cache memory model 4 or L2 cache memory model 5 and the CPU model 3 to the main memory model 1 occurs, so that a penalty can be calculated in the same manner as in the related art. Thus, even if the memory cached in the cache memory is omitted, the penalty can be calculated by simulating the tag and the status bit of the cache memory.
Also, since the simulator is used, the time for reading from the main memory and the cache memory does not change on the host. However, the time on the host may be reduced because the required resources are reduced.
[0021]
<effect>
As described above, according to the specific example 1, the penalty is calculated based on the tag and the status bit of the cache memory model 2, and the access time to the instruction or data of the cache memory model is used. Since the process is performed for the memory model 1, the memory of the simulated host can be saved.
[0022]
<< Specific Example 2 >>
The simulator of the specific example 2 is provided with a previous access tag of the instruction, and when the address of the access request instruction matches the previous access tag, determines that the cache hit occurs without searching the tag and checking the status bit. It was done.
[0023]
<Constitution>
FIG. 3 is a configuration diagram of the specific example 2.
The simulator of the specific example 3 includes, as the cache information storage model 7, a previous access tag information storage unit 13 for the instruction L1 cache memory model 4a.
The previous access tag information storage means 13 has a function of storing tag information of a previous instruction access to the instruction L1 cache memory model 4a.
[0024]
The cache hit judging means 8a of the specific example 2 has the same function as the cache hit judging means 8 of the specific example 1, and the access request to the cache memory is the instruction access, and the address of the access request is the last access tag information. If it matches the previous access tag in the storage unit 13, it has a function of determining a cache hit at that time. The access time calculation means 9 has the same function as the access time calculation means 9 of the first embodiment.
[0025]
The access unit 12 has a function similar to that of the first embodiment. That is, when the cache hit determination unit 8a determines that a cache hit has occurred due to a match with the previous access tag in the instruction access, the cache hit determination unit 8a has a function of reading the instruction from the main memory model 1.
The other configuration is the same as that of the first embodiment, and the corresponding portions are denoted by the same reference numerals and description thereof will be omitted.
[0026]
<motion>
Also in the specific example 2, the flow of the entire process as the simulator is the same as that of the specific example 1, so that the description here is omitted, and the cache check processing will be described.
FIG. 4 is a flowchart of the cache check in the specific example 2.
First, if the access request is for reading an instruction, the cache hit determination means 8a calculates a tag from the address of the instruction, and the tag is stored in the previous access tag information storage means 13 corresponding to the instruction L1 cache memory model 4a. It is checked whether it matches the previous access tag (step S11). If they match, the cache hit determining means 8a regards that a cache hit has occurred, the access time calculating means 9 calculates a penalty, and the access means 12 reads the instruction from the main memory model 1 (steps S15 and S17). .
[0027]
Here, the cache hit is determined only by the match between the previous access tag and the tag of the instruction address. This is because no writing from the CPU occurs in the instruction L1 cache memory (the state bit is not changed). Therefore, a cache hit always occurs for the line that has hit the previous cache (the tag that has hit the last cache), and a cache hit always occurs for the line that has missed the cache because the instruction L1 cache memory has been updated. is there.
[0028]
In addition, since it is not necessary to search for tags in all instructions, the speed of the simulator as viewed from the host can be improved. In particular, this becomes remarkable when the size of the cache memory is increased, the size of one line is increased, or instructions of consecutive addresses are executed.
[0029]
On the other hand, if it is determined in step S11 that the access tag does not match the previous access tag, the processes in and after step S12 are performed. The processing of steps S12 to S17 is the same as the processing of steps S1 to S6 in the first specific example. Further, in step S18, if the access is for reading the instruction, the tag calculated from the address of the accessed instruction is stored in the previous access tag of the previous access tag information storage unit 13, and the process ends.
[0030]
<effect>
As described above, according to the specific example 2, in addition to the configuration of the specific example 1, the previous access tag information storage unit 13 for accessing the instruction is provided, and the tag of the access request of the instruction matches the previous access tag. Is immediately determined to be a cache hit, so that the speed as a simulator can be improved.
[0031]
<< Specific Example 3 >>
Specific example 3 is to provide a previous access tag and a previous access status bit for data, and to search for a tag when the address of the access request data matches the previous access tag and the status bit is valid. Instead, it is determined to be a cache hit.
[0032]
<Constitution>
FIG. 5 is a configuration diagram of the third example.
The simulator of the specific example 3 includes, as the cache information storage model 7, a previous access tag information storage unit 14 and a previous state information storage unit 15 for the data L1 cache memory model 4b.
The previous access tag information storage unit 14 has a function of storing tag information of previous data access to the data L1 cache memory model 4b, and includes a read last access tag 14a and a write previous access tag 14b. These are for storing previous access tags corresponding to data read and write.
[0033]
The previous state information storage means 15 indicates the state bits corresponding to the previous access tag 14a for read and the previous access tag 14b for write, and the last access state bit 15a for read and It has a previous access status bit for write 15b.
[0034]
The cache hit determination unit 8b of the specific example 3 determines that the access request to the cache memory is data and the address of the data is the last access tag 14a for reading or the last access tag 14b for writing of the last access tag information storage unit 14. When the status bit of the read last access status bit 15a or write last access status bit 15b corresponding to the tag and matching the previous read access tag 14a or the previous access tag 14b for writing is valid. Has a function of determining a cache hit at that time. Since the read / write access tag and the status bit are provided in this manner, the probability that the read / write access tag matches the previous access tag becomes higher than when the read / write is not distinguished.
The other components in FIG. 5 are the same as those in the first and second embodiments. Therefore, corresponding portions are denoted by the same reference numerals and description thereof is omitted.
[0035]
<motion>
Also in the specific example 3, since the flow of the entire process as the simulator is the same as that of the specific examples 1 and 2, the description here will be omitted and the cache check processing will be described.
FIG. 6 is a flowchart of the cache check in the third example.
First, for reading (writing) data, a tag is calculated from the address, and it is checked whether the tag matches the previous access tag 14a for reading or the previous access tag 14b for writing (step S21). If they match, the previous access status bit 15a for read or the previous access status bit 15b for write is checked (step S22). If the status bit is not invalid, the cache hit determination means 8b considers that a cache hit has occurred. If the cache hit determination means 8b determines that the cache hit, the access time calculation means 9 calculates a penalty, and the access means 12 reads or writes data from the main memory model 1 (steps S26 and S28). .
[0036]
Here, if the previous access tag 14a for reading or the previous access tag 14b for writing and the tag of the address of the access request data match, and the previous access status bit 15a for reading or the previous access status bit 15b for writing is invalid, the cache This is a hit, but this is the last cache hit line (the last cache hit tag). If the last access status bit is not invalid, a cache hit will always occur. This is because the cache hit occurs unless the L1 cache memory model 4b is updated and the previous access state bit 15a for read or the previous access state bit 15b for write is invalid.
Note that the status bit is always checked because the status bit may be invalidated when writing to the cache.
[0037]
Further, since it is not necessary to search for tags in all data, the speed of the simulator viewed from the host can be improved. In particular, this becomes remarkable when the size of the cache memory is increased, the size of one line is increased, or data access occurs at consecutive addresses.
[0038]
On the other hand, if the previous access tag for reading 14a or the previous access tag for writing 14b does not match in step S21, and if the previous access status bit 15a for reading or the previous access status bit 15b for writing is invalid in step S22, , And performs the processing after step S23. The processing of steps S23 to S28 is the same as the processing of steps S1 to S6 in the first specific example. In step S29, the tag calculated from the address of the accessed data is stored in the read last access tag 14a or the write last access tag 14b, and the read last access state bit 15a or the write last access state bit 15a is stored. 15b is updated.
[0039]
<effect>
As described above, according to the specific example 3, the previous access tag information storage unit 14 and the previous access tag information storage unit 14 corresponding to the data L1 cache memory model 4b are provided, and the tag of the access request data and the previous access tag information are stored. If the access tag matches and the previous status bit is not invalid, it is immediately determined that a cache hit has occurred, so that the speed of the simulator as viewed from the host can be improved.
[0040]
<< Specific Example 4 >>
Example 4 relates to a simulation when data is accessed to the L2 cache memory model 5.
[0041]
<Constitution>
FIG. 7 is a configuration diagram of the specific example 4.
The simulator of the specific example 4 includes, as the cache information storage model 7, a previous access tag information storage unit 16 and a previous state information storage unit 17 for the L2 cache memory model 5.
The previous access tag information storage means 16 has a function of storing tag information of previous instruction access and data access to the L2 cache memory model 5, and includes an instruction previous access tag 16a and a data previous access tag 16b. . These are for storing the previous access tag corresponding to the command and the data.
The previous state information storage means 17 has a previous access state bit 17a for data. The previous access status bit for data 17a indicates a status bit corresponding to data corresponding to the previous access tag for data 16b.
[0042]
The cache hit determination means 8c of the specific example 4 determines that the access request to the cache memory is an instruction and the address of the access request matches the previous access tag 16a for the instruction, and that the access request to the cache memory is data. If the address of the access request matches the previous access tag 16b for data and the previous access status bit 17a for data is valid, a function is provided to determine a cache hit at that time. .
The other components in FIG. 7 are the same as those of the first to third examples, and the corresponding portions are denoted by the same reference numerals and description thereof will be omitted.
[0043]
<motion>
Also in the specific example 4, the flow of the entire process as the simulator is the same as that of the specific examples 1 to 3, and the description here is omitted, and the cache check processing will be described.
FIG. 8 is a flowchart of the cache check in the specific example 4.
When an access from the L1 cache memory model 4 to the L2 cache memory model 5 occurs, a tag is calculated from the address, and it is checked whether the tag matches the previous access tag for instruction 16a or the previous access tag for data 16b (step). S31). If either tag matches, it is determined whether the access is a data access (step S32). If it is not a data access in step S32, that is, if it is an instruction access, it is regarded as a cache hit of the L2 cache memory model 5 at that time.
[0044]
In step S32, if it is a data access, the previous access status bit for data 17a is checked (step S33). If the status bit is not invalid, it is regarded as a cache hit of the L2 cache memory model 5. If it is determined that the cache hit has occurred in the L2 cache memory model 5, the access time calculation means 9 calculates a penalty, and the access means 12 reads an instruction from the main memory model 1 or reads / writes data. Perform (Step S37, Step S39).
[0045]
Here, the previous access tag 16a for instruction or the previous access tag 16b for data matches, and in the case of data, unless the previous access status bit 17a for data is invalid, a cache hit is determined. This is because, in the case of an instruction, writing from the CPU does not occur in the L2 cache memory (the state bit does not change), so that the line that has hit the cache previously (the tag that has hit the previous cache) always hits the cache. This is because the L2 cache memory is updated even if the line has a cache miss last time, so that a cache hit always occurs.
In the case of data, the status bit is always checked because the status bit may be invalidated when writing to the cache.
[0046]
Further, since it is not necessary to search for tags in all data, the speed of the simulator viewed from the host can be improved. In particular, this becomes remarkable when the size of the cache memory is increased, the size of one line is increased, or data access occurs at consecutive addresses.
[0047]
On the other hand, if the previous access tag for instruction 16a or the previous access tag for data 16b does not match in step S31, and if the previous access status bit for data 17a is invalid in step S33, the processing after step S34 is performed. . Steps S34 to S39 are the same as steps S1 to S6 in the first specific example.
In step S40, the tag and the status bit calculated from the address of the accessed instruction or data are stored in the previous access tag for instruction 16a, the previous access tag for data 16b, and the previous access status bit for data 17a, and the process ends.
[0048]
<effect>
As described above, according to the specific example 4, in the L2 cache memory model 5, when the tag at the time of reading an instruction matches the previous access tag, or when reading and writing data, If the access tag matches and the previous status bit is not invalid, it is immediately determined that a cache hit has occurred, so that the speed of the simulator viewed from the host can be improved.
[0049]
《Usage form》
In the specific example 2, the configuration related to the instruction L1 cache memory model 4a is used, and in the specific example 3, the configuration is related to the data L1 cache memory model 4b. However, these configurations may be combined.
In the specific example 3, the previous access tag and the previous access state bit are separately provided for read / write, but the previous access tag and the previous access state bit which do not distinguish between read / write may be used. Further, in the specific example 4, as in the specific example 3, a previous access tag and a previous access state bit may be separately provided for read / write for the previous data access.
[0050]
【The invention's effect】
As described above, according to the present invention, when a cache hit occurs in the cache memory model, the operation time of this access is counted as the access time to the cache memory model, and the information of the cache hit is separately transmitted to the main memory model. Since access is made, execution time can be accurately simulated, and a memory area for a cache memory model on the host can be made unnecessary, thereby saving system resources of the simulated host. Can be. Further, the speed of the simulator can be improved.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a simulator according to a first embodiment of the present invention.
FIG. 2 is a flowchart of a cache check in a specific example 1.
FIG. 3 is a configuration diagram of a simulator according to Embodiment 2 of the present invention.
FIG. 4 is a flowchart of a cache check in a specific example 2;
FIG. 5 is a configuration diagram of a simulator according to a third embodiment of the present invention.
FIG. 6 is a flowchart of a cache check in a specific example 3;
FIG. 7 is a configuration diagram of a simulator according to Embodiment 4 of the present invention.
FIG. 8 is a flowchart of a cache check in a specific example 4.
FIG. 9 is a configuration diagram of a conventional simulator.
FIG. 10 is a flowchart showing an entire process in a conventional simulator.
FIG. 11 is a flowchart of a cache check in a conventional simulator.
[Explanation of symbols]
1 Main memory model
2 Cache memory model
3 CPU model
4 L1 cache memory model
5 L2 cache memory model
8, 8a, 8b, 8c Cache hit determination means
9 Access time calculation means
10 Tag information storage means
11 State information storage means
12 access means
13, 14, 16 Last access tag information storage means
15, 17 Last state information storage means

Claims (4)

In a simulator that simulates a program execution operation of an information processing device including a main memory, a cache memory, and an arithmetic processing device and counts the operation time,
Tag information storage means for storing, as tag information, address information of a main memory model simulating the operation of the main memory, corresponding to information stored in a cache memory model simulating the operation of the cache memory;
State information storage means for storing state information indicating a matching state between information stored in the cache memory model and information stored in the main memory model corresponding to the information;
When an access request to the cache memory model is detected, the address of the access request matches the tag information stored in the tag information storage unit, and the status information of the status information storage unit is in a matching state A cache hit determining means for determining a cache hit;
An access time calculation unit that counts an operation time of the access as an access time to the cache memory model when the cache hit determination unit determines a cache hit;
An access means for accessing the information to the main memory model when the cache hit determination means determines that the cache hit has occurred. In a simulator that simulates a program execution operation of an information processing device including a main memory, a cache memory, and an arithmetic processing device and counts the operation time,
Tag information storage means for storing, as tag information, address information of a main memory model simulating the operation of the main memory, corresponding to instructions stored in a cache memory model simulating the operation of the cache memory;
Last access tag information storage means for storing tag information of the last instruction access;
A cache hit determination unit that determines a cache hit when an access request to the cache memory model is an instruction access and an address of the access request matches the previous access tag information;
An access time calculation unit that counts an operation time of the access as an access time to the cache memory model when the cache hit determination unit determines a cache hit;
An access unit that reads the instruction from the main memory model when the cache hit determination unit determines that the cache hit has occurred. In a simulator that simulates a program execution operation of an information processing device including a main memory, a cache memory, and an arithmetic processing device and counts the operation time,
Tag information storage means for storing, as tag information, address information of a main memory model simulating the operation of the main memory, corresponding to data stored in a cache memory model simulating the operation of the cache memory;
State information storage means for storing state information indicating a matching state between data stored in the cache memory model and data stored in the main memory model corresponding to the data;
Last access tag information storage means for storing tag information of previous data access to the cache memory model;
For the data of the previous data access, the previous state information for storing the state information indicating the matching state between the information stored in the cache memory model and the information stored in the main memory model corresponding to the information. Storage means;
If the access request for the cache memory model is a data access, the cache that determines a cache hit if the address of the request matches the previous access tag information and the previous state information matches. Hit determination means,
An access time calculation unit that counts an operation time of the access as an access time to the cache memory model when the cache hit determination unit determines a cache hit;
An access unit for performing the data access to the main memory model when the cache hit determination unit determines that a cache hit has occurred. In a simulator that simulates a program execution operation of an information processing device including a main memory, a cache memory, and an arithmetic processing device and counts the operation time,
Tag information storage means for storing, as tag information, address information of a main memory model simulating the operation of the main memory corresponding to an instruction or data stored in a cache memory model simulating the operation of the cache memory;
State information storage means for storing state information indicating a matching state between data stored in the cache memory model and data stored in the main memory model corresponding to the data;
Last access tag information storage means for storing tag information of the last instruction or data access to the cache memory model;
Status information indicating the matching status between the data stored in the cache memory model and the data stored in the main memory model corresponding to the data with respect to the data of the previous data access to the cache memory model Last state information storage means for storing
When the access request to the cache memory model is an instruction access, and the address of the access request matches the previous instruction access tag information of the access tag information storage means, and the access request to the cache memory model is a data access. And if the address of the access request matches the previous access tag information of the previous access tag information storage means and the status information of the previous status information storage means is in a matching state, it is determined that a cache hit has occurred. A cache hit determination means to perform
An access time calculation unit that counts an operation time of the access as an access time to the cache memory model when the cache hit determination unit determines a cache hit;
An access unit for accessing the instruction or data to the main memory model when the cache hit determination unit determines that the cache hit has occurred.

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