JP2002334128A - Method for simulating power consumption of semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for estimating power consumption of a semiconductor integrated circuit of a processor on which an MMU(memory managing unit) and a cache memory are mounted and to convert a logical address into a physical address at an architecture level at high speed in the processor. SOLUTION: This method is preliminarily provided with pieces of power consumption information by every MMU operation of an MMU part 1302, write-back and right-through modes are distinguished, power consumption information by every cache operation including start of write of dirty data is provided, power consumption information of a CPU part 1301 by every instruction for a cache part 1303. Power to be consumed in the entire object circuit of simulation is calculated from the pieces of power consumption information during execution or after completion of simulation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for simulating power consumption of a semiconductor integrated circuit using a computer, and more particularly to performing task processing using logical addresses when estimating power consumption by instruction-level simulation. The present invention also relates to a technique for simulating the circuit operation of a semiconductor integrated circuit and estimating the power consumption of the processor core at high speed.

[0002]

2. Description of the Related Art Conventionally, as a method of simulating power consumption of a semiconductor integrated circuit using a computer, a simulation method at an instruction level has been used particularly in a design called core-based design or IP-based design.

As a simulation of power consumption at an instruction level, Japanese Patent Application Laid-Open No. 09-218731 and
No. 0-254944. The methods shown in these methods prepare a power consumption library for a simulation target operation such as a cache access or a bus access in advance, and execute a simulation.As a result, the number of occurrences of each simulation target operation is counted, and the executed program is executed. That is, the power consumed by the entire circuit to be simulated is calculated.

[0004]

However, in recent years,
In the field in which semiconductor integrated circuits are used, software is required to have complicated and advanced processing and reusability of the software itself. To realize this, an MMU (Memory Management Unit) is also required in hardware. It is indispensable to mount it and implement a logical address and access protection function.

In a system equipped with an MMU, a page table which is an address conversion table is accessed as necessary, and a TLB (Tr) which is an address conversion table in the MMU is accessed.
Anslation Lookaside Buffers: address translation buffers) are stored. The cache operation mode is also defined in the page table at the same time, and a write-back mode or a write-through mode, a cache operation prohibition, or the like is defined as a cache operation for each address area.

The write-back mode (WB) is a cache operation mode for updating only data in the cache memory when a cache hit occurs during data write processing to the memory. The write-through mode (WT) is a cache operation mode for updating data in a cache memory and updating data at a corresponding address in a main memory when a cache hit occurs during a process of writing data to the memory. It is.

[0007] Since the cache operation in the write-back mode and the cache operation in the write-through mode in the cache memory are different from each other, it is necessary to distinguish power consumption estimates.

Furthermore, data in the address area defined in the write-back mode is inconsistent with data in the main memory at the corresponding address in comparison with data in the cache. Therefore, when only the contents of the cache are updated, data for which consistency cannot be guaranteed must be treated as dirty data and distinguished. Therefore, when the contents of the cache are renewed or stored cache data is overwritten with data of another address, a hardware process of writing dirty data occurs.

A typical example of the above-mentioned software is a real-time operating system, which has been used in recent years. When such software is used, a method of switching tasks by switching an address conversion table is employed.If data is stored in a cache at a logical address, even when the task is switched, the Writing occurs as hardware processing, and accurate power consumption cannot be estimated by the conventional power consumption simulation method that does not assume an MMU as described above.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances. In a processor equipped with an MMU and distinguishing between a logical address and a physical address, a simulation of power consumption at an instruction level is performed so that power consumption can be accurately calculated. It is an object of the present invention to provide a power consumption simulation method for a semiconductor integrated circuit that can be estimated.

[0011]

In order to achieve the above object, a method for simulating power consumption of a semiconductor integrated circuit according to the present invention includes a CPU (Central Processing Unit), a cache memory, and an MMU (Memory Management Mechanism). In the processor, power consumption information for each instruction is provided in advance for each instruction at the processor instruction level, power consumption information for each MMU operation is provided for the MMU, and power consumption information for each cache operation is provided for the cache memory. During the execution or after the execution of the simulation, the power consumed by the processor to be simulated is calculated based on the power consumption information.

The present invention is directed to a method of simulating the instruction operation of a processor having a cache memory and an MMU in a computer, and is consumed when each instruction is executed beforehand for the instruction set of the processor before the simulation. The power is obtained and stored as power consumption information for each instruction, and the power consumed for each operation of the plurality of operations of the MMU is obtained and stored as power consumption information for each MMU operation. The power consumed for each operation is obtained by distinguishing the write-back mode and the write-through mode for a plurality of operations of the cache memory, and power consumption information for each cache operation is stored. Then, when a simulation is performed for a program code using a given logical address, an instruction operation, an MMU operation, and a cache operation are simulated for each instruction and executed based on the power consumption information for each instruction. The power consumption of the CPU unit for the instruction in the middle is obtained, the power consumption of the MMU unit corresponding to the MMU operation generated by the address conversion is obtained based on the power consumption information for each MMU operation, and the power consumption of the MMU unit is further calculated. Determining a corresponding power consumption of the cache unit, and calculating a total power consumption of the processor when executing the program code from the power consumption of the CPU unit, the power consumption of the MMU unit, and the power consumption of the cache unit. I do.

According to the present invention, in a processor including a cache memory and an MMU, it is possible to relatively quickly determine the power consumption during execution of a program code.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be generally described.

A power consumption simulation method for a semiconductor integrated circuit according to a first aspect of the present invention provides a circuit-level or gate-level simulation for each instruction of an instruction set of a processor and a plurality of operations of a cache memory and an MMU before executing a simulation. The power consumed when each instruction is executed is obtained from the simulation of the above or the evaluation result of the actual chip actually produced, and stored as power consumption information for each instruction, and the power consumed when each cache operation is executed. The power consumed is calculated and stored as power consumption information for each cache operation. The power consumed when each MMU operation is executed is determined and stored as power consumption information for each MMU operation. This processing may be performed for the number of instructions in the instruction set and for the number of cache operation types, and for the number of MMU operation types. It is possible to calculate within a short time.

Then, while simulating the instruction operation for the program code given during the execution of the simulation, the value of the power consumption corresponding to the executed instruction is searched from the power consumption for each instruction. With respect to the cache, the cache operation of fetching an instruction to be executed and, for some instructions, writing or reading data is simulated, and the value of power consumption corresponding to the executed cache operation is cached. The power consumption information is searched from each power consumption information, and for the MMU, the MMU operation for the address of the instruction fetch and the data write / read access for some instructions is simulated, and the power consumption corresponding to the executed MMU operation is simulated. A value is retrieved from the power consumption information for each MMU operation.

By summing up these power consumption values at regular intervals, a time transition of the power consumed by the CPU unit, the cache unit, and the MMU unit when operating with the given program code is obtained. .

As described above, according to the present invention, in a processor including a cache memory and an MMU, it is possible to obtain the power consumption during execution of a program code at a relatively high speed.

According to a second aspect of the present invention, there is provided a power consumption simulation method for a semiconductor integrated circuit according to the first aspect, wherein
The power consumption information for each MMU operation is at least M
This is power consumption information that distinguishes between an operation performed when a hit occurs in a TLB (address translation buffer) incorporated in the MU and an operation performed when a miss occurs. For the logical address output from the CPU unit, the T
When the LB hits, the MM based on the power consumption information for the MMU operation when the TLB hits
The power consumption of the U unit is obtained, and when the TLB misses, the power consumption of the MMU unit is obtained based on power consumption information when the TLB misses. Therefore, the power consumption of the processor including the cache memory and the MMU can be estimated.

According to a third aspect of the present invention, there is provided the power consumption simulation method for a semiconductor integrated circuit according to the first and second aspects, wherein the power consumption information for each cache operation is at least for a write-back mode and a write-through mode. When a simulation is performed for a given program code, the logical address output from the CPU unit at the time of execution of each instruction is converted by the MMU into an address. As a result, the address is used to use the cache in the write-back mode. In this case, the power consumption of the cache unit is obtained based on the power consumption information for each cache operation for the write-back mode, and the output logical address is converted by the MMU into an address.
When the address is used for the cache in the write-through mode, the power consumption of the cache unit is obtained based on the power consumption information for each cache operation for the write-through mode. Therefore, it is possible to accurately estimate the power consumption of the processor including the cache memory and the MMU and having the write-back mode and the write-through mode.

According to a fourth aspect of the present invention, there is provided a power consumption simulation method for a semiconductor integrated circuit according to the first to third aspects, wherein the power consumption information for each cache operation includes at least a write operation of dirty data of the cache. When a simulation is performed on a given program code, a cache read error, a dirty data write processing instruction, and a page table referred to by the MMU are changed to a page table different from the previous one. When an operation of writing dirty data occurs, the power consumption of the cache unit is obtained from the power consumption information on the dirty data writing operation. Therefore, even in a program including a cache memory and an MMU and in which dirty data is written out, accurate estimation of the power consumption of the processor can be realized.

According to a fifth aspect of the present invention, there is provided a power consumption simulation method for a semiconductor integrated circuit according to the first to fourth aspects, wherein information necessary for power consumption calculation is stored in a storage device during execution of the simulation. After the simulation is executed, the power consumption of the circuit at the time of the circuit operation obtained by the simulation is obtained based on information necessary for the power consumption calculation stored in the storage device.

(Specific Embodiment) Hereinafter, a specific embodiment of a method for simulating power consumption of a semiconductor integrated circuit according to the present invention will be described with reference to the drawings.

FIG. 1 is a flowchart showing the flow of processing when a simulation is performed in a method for simulating power consumption of a semiconductor integrated circuit according to an embodiment of the present invention. Reference numeral 101 denotes an initialization process for initializing each unit in a circuit to be simulated. Here, the CPU unit of the processor model, the cache unit, and various registers of the MMU unit are set. Reference numeral 102 denotes a program code reading process for reading the program code given to the processor model to be simulated, and setting the position of the instruction to start the simulation and the position of the instruction to end the simulation. An instruction reading process 103 reads an instruction to be executed in the current execution cycle from a given program code. Instruction is CPU
The unit outputs a logical address where the instruction is stored, is read via the cache memory, and the MMU unit converts the logical address into a physical address to read the instruction from outside the cache. A simulation of the operation of the MMU unit is performed. Reference numeral 104 denotes an MMU unit power consumption calculation process for obtaining power consumed by the MMU unit from power consumption information for each operation of the MMU unit in accordance with the operation of the MMU unit simulated in the instruction reading process 103. 105 is an instruction reading process 1
This is a cache unit power consumption calculation process for calculating the power consumption of the cache unit from the power consumption information for each cache operation according to the operation of the cache unit simulated in 03. An instruction execution process 106 simulates a processor operation of the instruction read in the instruction reading process 103. Reference numeral 107 denotes CPU unit power consumption calculation processing for obtaining power consumption corresponding to the instruction simulated in the instruction execution processing 106 from the power consumption information for each instruction.

Reference numeral 108 denotes a case where a data access occurs by an instruction simulated in the instruction execution processing 106.
MMU according to the operation of the simulated MMU unit
This is an MMU unit power consumption calculation process for calculating the power consumption consumed by the MMU unit from the power consumption information for each operation. Reference numeral 109 denotes a cache unit power consumption for calculating the power consumption of the cache unit from the power consumption information for each cache operation according to the simulated operation of the cache unit when data access occurs by the instruction simulated in the instruction execution processing 106. This is a calculation process.

Reference numeral 110 denotes a program code reading process 1
This is a program code end determination process for determining whether or not the program code to be simulated has ended based on the end instruction position set in 02. 11
2 is an execution cycle update process for advancing the execution cycle for performing the simulation by one when it is determined in the program code end determination process 110 that the simulation of the program code is not completed. And the processing of the next execution cycle is continued. Reference numeral 111 denotes a power consumption output process for outputting the power consumption information calculated in the power consumption calculation process up to now when the program code to be simulated by the program code end determination process 110 has been completed.

FIG. 2 is an example of a simulated processor instruction set. 201 is an instruction table showing a list of instruction sets. LDR is a data load instruction for transferring data from data in a memory area specified by an address to a register. STR is a data store instruction for transferring data from a register to a memory area specified by an address. CMP compares the value of a register specified by the source or a constant value with the value of the register specified by the destination (data destination), resets the comparison result flag if they are equal, and resets the comparison result flag if they are not equal. This is a comparison instruction to be set.
ADD is an addition instruction for adding the value of the register specified by the source and the value of the register specified by the destination, and assigning the result to the register specified by the destination. SUB is a subtraction instruction for subtracting the value of the register specified by the destination from the value of the register specified by the source, and assigning the result to the register specified by the destination. BNQ is
If the comparison result flag is set, this is a conditional branch instruction that causes the processing to jump to the instruction position specified by the label. The NOP is an instruction that advances the instruction cycle by one without performing any calculation. The MCR is an MMU unit control instruction that stores the value of the register indicated by the source in the register incorporated in the MMU indicated by the destination. Where MM
The value of the U-unit built-in register is an address serving as a reference of the address where the table used by the MMU is placed.

FIG. 3 shows power consumption information for each instruction of a processor to be simulated. Reference numeral 301 denotes a power consumption table for each instruction, which stores a power consumption value when the instruction is executed once for each instruction defined in the instruction table 201.

FIG. 4 shows an example of power consumption information for each MMU operation. Reference numeral 401 denotes a power consumption table for each MMU operation.
02, TLB Hit as the case where the TLB hits as the MMU operation, and TLB as the case where the TLB misses
Miss is defined, and power consumption is determined in advance by a circuit simulator or the like when the MMU operation hits and misses, and stored in the power consumption table 401 for each MMU operation. Here, a value of 5 [μW / MHz] is stored at the time of TLB Hit, and a value of 40 [μW / MHz] is stored at the time of a mistake.

FIG. 5 shows an example of power consumption information for each cache operation. Reference numeral 501 denotes a power consumption table for each cache operation. Reference numeral 502 denotes “Read Hit” as a cache hit during a read operation as a cache operation, and “Read M” as a cache miss during a read operation.
iss ”and“ Write Hi ”during the write operation.
t "and" Write Miss "during the write operation.
Is defined, and “Clean” is defined as an operation at the time of writing data classified as dirty data to the memory area, and the power consumption information is obtained when the cache operation operates in the write-through mode. , Respectively, when operating in the write-back mode. For each of these operations, a case where a cache operation occurs is obtained in advance by a circuit simulator or the like, and stored in the power consumption table 501 for each cache operation.

Here, the power consumption in the write-through mode is 20 [μW / MHz] at the time of Read Hit,
100 [μW / MHz] at Miss, 80 [μW / MHz] at Write Hit, 40 [μW / M] at Write Miss
Hz] are stored, and as power consumption in the write-back mode, 20 [μW / MHz] and Re
100 [μW / MHz] at the time of ad Miss, Write Hi
70 [μW / MHz] at t, 35 at Write Miss
The value of [μW / MHz] is stored, and at the time of Clean, the power consumption per word of data to be written is 10 [μW / MHz].
Is stored.

FIG. 6 shows an example of the contents of the memory stored in the memory area in the initialization processing 101. Numeral 601 is a table of each physical address and data stored therein, and indicates that [8] is stored in [50] and “200” is stored in [80].

FIG. 7 shows an example of the contents of the data stored as the page table 1 in the contents of the data stored in the memory area in the initialization processing 101. According to the contents 601 of the memory at the time of the initialization processing, the page table 1 is a page table having [300] as a reference of the address where the table table is placed, and the contents 701 of the page table 1 are the contents. The content 701 of the page table 1 includes a logical address value,
The physical address after the conversion and the cache mode of the memory area of the address are shown. Part 702 of the page table is a page table for logical addresses [0] to [49], and is stored at address [300]. Part 703 of the page table is a page table for logical addresses [50] to [99], and is stored at address [301]. MM
The U section stores, in the control register of the MMU section, the address where a part of the page table corresponding to the logical address [0] is stored in the control register of the MMU in the instruction MCR indicated by the instruction set 201 as a reference of the page table 1. MM according to the size of
The page table 1 is accessed based on the value of the internal control register of the U section. The physical addresses are prohibited in the part 706 of the page table 1 because these logical addresses [2
00] to [249] indicate that the access is prohibited.

FIG. 8 shows an example of the contents of the data stored as the page table 2 among the contents of the data stored in the memory area in the initialization processing 101. According to the contents 601 of the memory at the time of the initialization processing, the page table 2 is a page table having [400] as a reference of the address where the table table is placed, and the contents 801 of the page table 2 are the contents. The content 801 of the page table 2 includes a logical address value,
The physical address after the conversion and the cache mode of the memory area of the address are shown. Part 802 of page table 2 is a page table for logical addresses [0] to [49], and is stored at address [400]. Part 803 of page table 2 is a page table for logical addresses [50] to [99], and is stored at address [401].
The MMU unit stores, in the control register of the MMU unit, an address at which a part of the page table corresponding to the logical address [0] is stored in the instruction MCR indicated by the instruction set 201 as a basis of the page table 2 in the control register of the MMU unit. The page table 2 is accessed based on the value of the internal control register of the MMU unit in accordance with the size of. The prohibition of the physical address in the part 806 of the page table 2 indicates that these logical addresses [200] to [249] are access-prohibited areas.

FIG. 9 shows an example of a program executed by a processor to be simulated. Reference numeral 901 denotes the entire program, each row representing one instruction, and each row indicates a label, an instruction, a destination (data destination), and a source from the left column. Reference numeral 902 denotes an address where each line of the program is stored. The instruction 903 at the storage address [0], ie, the source [80] of the LDR
Indicates an address 80 in the logical address space. Similarly, for other instructions from 904 to 921, each row indicates one instruction.

FIG. 12 is an example of a hardware configuration of a computer that executes a simulation process according to the present embodiment. Reference numeral 1201 denotes a display device for displaying all processed information; 1202, a keyboard for a designer to input all information and processing instructions;
03 is a central processing unit that performs all kinds of processing, 1204
Is a storage device for storing various information.

FIG. 13 is an example of a conceptual diagram of a processor model in a simulation according to the present embodiment. The model includes a CPU unit 1301, an MMU unit 1302, and a cache unit 1303. A bus interface unit 1304 to be connected is added, and the operation of each of these units is simulated.

Hereinafter, a method for simulating power consumption of a semiconductor integrated circuit according to the present embodiment will be described in detail with reference to the flowchart of FIG.

In an initialization process 101, initialization for executing a program is performed. Here, various registers of the CPU unit 1301, the MMU unit 1302, and the cache unit 1303 of the processor model shown in FIG. 13 are set. It is assumed that the contents of the memory are set according to Table 601.

In the program code reading process 102, the program code 901 is read into the storage device 1204, and the program counter register is set so that the execution of the program is started from the instruction 903. Further, it is set so that the execution of the program is terminated when the instruction 921 is reached. Also, [30] is used as a reference of a page table used for address conversion of the MMU unit 1302.
0] is given.

In the instruction reading process 103, the instruction indicated by the program counter is read. In this case, the address [0] indicated by the program counter is the address used as the reference for page table 1 in the MMU unit 1302 is [300], and the page table 702 is used. Therefore, TLB becomes TLB Miss. The logical address [0] is converted to a physical address [0], is used as an instruction read destination address, and reads the instruction 903 via the cache unit 1303. The cache has access to this address [0]. Since it is the first time, the cache becomes Read Miss. And MM
40 [μ] when TLB Miss is obtained from the power consumption table 401 for each MMU operation in the U unit power consumption calculation processing 104
W / MHz] is calculated, and the cache unit power consumption calculation processing 10
In step 5, 100 [μW / MHz] in the case of Read Miss is obtained from the power consumption table 501 for each cache operation (write back mode).

Here, the calculation of the power consumption is performed in the power consumption table 40.
This is a simple process of subtracting the power consumption value of the corresponding MMU unit operation and cache operation from 1,501, and is easily calculated at high speed.

Next, the operation of the LDR instruction 903 is simulated by the instruction execution processing 106, and the logical address [80] is converted into the physical address [80] by the page table 703.
At this time, since this page table is used for the first time, TLB
The address becomes [Miss], and the address [80] is accessed via the cache unit 1303. However, since this address is not prepared in the cache even by the cache refill operation, a cache miss occurs. Thus, the value 300 of the address [80] is read into the register r5.

Next, in the CPU unit power consumption calculation processing 107, 15 [μW / MHz] corresponding to the LDR instruction is obtained from the power consumption table 301 for each instruction.

Next, in the MMU unit power consumption calculation processing 108, the TLB is obtained from the power consumption table 401 for each MMU operation.
40 [μW / MHz] corresponding to Miss is obtained, and 100 [μW / MHz] in the case of Read Missing is obtained from the power consumption table 501 for each cache operation in the cache unit power consumption calculation processing 109.

Next, program code end determination processing 11
It is determined by 0 whether or not the code of the simulation end condition has been reached. In this case, the code has not been reached. Therefore, the cycle number is set to 2 in the execution cycle update processing 112, the program counter register is advanced by 1, and the next instruction code 904 is set. It is read in the instruction reading process 103.

Hereinafter, the processing from the instruction reading processing 103 to the execution cycle updating processing 112 is repeated until the end condition code is reached. 10 and 11 show the results.

In FIG. 10, 1001 is the number of cycles,
1002 is the executed instruction, 1003 is the operation of the MMU unit 1302 when reading the instruction, 1004 is the operation of the cache unit 1303 when reading the instruction, 1005 is the operation of the MMU unit 1302 when executing the instruction, and 1006 is the instruction. This is the result of the operation of the cache unit 1303 when executed. In operation of the MMU section, Miss is TLB Miss.
s, and Hit is TLB Hit. In the cache operation, R Miss is a cache read miss, R Hit is a read hit, WB Hit is a write hit in the write-back mode, WB Miss is a write miss in the write-back mode, WT Hit is a write hit in the write-through mode, WT Miss indicates a writing error in the write-through mode. Clea
n represents a process of writing dirty data to the memory area, and the number of words indicated by a number in parentheses is written.
A dash indicates that no cache access has occurred.

In particular, as an estimate of the power consumption distinguishing the write-back mode, in the instruction 909 in FIG.
Since this is an R instruction, it is a write process. In this case, since the page table of the logical address [100] is [302] from FIG. 7, the logical address [100] is converted into the physical address [200]. It can be seen that the cache operation is performed in the write-back mode. Since it is in write-back mode,
The power consumption is obtained from the power consumption table 504 in FIG. 5, and a cache miss in the read processing has occurred in the instruction 908, and the data at this address is stored in the cache. 70 [μW / MHz] is calculated as 1006 in FIG. 10, WB Hit is calculated as 1006 in FIG. 10, and 70 [μW / MHz] is calculated as the power consumption of the cache operation in 1106 in FIG.

Similarly, the 17th cycle corresponds to the instruction 914, and the MCR instruction is an MMU section control instruction, and changes the reference address of the address where the page table is placed. Here, the reference value of the address where the page table is placed is [400]
Is stored, and the page table 2 shown in FIG. 8 is used for the address conversion instead of the page table 1 shown in FIG.
Since the address translation table has been changed, all the tables in the TLB are invalidated, and among the cache data stored by the logical address, the data that has become WB Hit in cycle 12 in FIG. 10 is written in the write-back mode. Since it is a cache hit, there is no consistency with the main memory, and when the page table is changed, the data in the cache stored at the logical address becomes invalid, and a write process to the main memory occurs. In cycle 17, the writing of dirty data indicated as Clean has occurred. Cl
"16" of "ean (16)" is the number of words. This indicates that since dirty data in the cache is managed in units of 16 words, 16 words are subjected to the writing process. More power consumption during dirty data write processing is required. As described above, power consumption in a case where the dirty data is written out of the cache due to the change of the page table is required.

In particular, as an estimate of power consumption in the write-through mode, the page table is changed in the instruction 914, and the
Even if a write to the logical address [100] occurs as in the case of 09, the logical address [100] corresponds to the physical address [600] and the cache operation mode is the write-through mode according to FIG. According to FIG. 5, the power consumption during the operation of the cache is obtained from the value of the power consumption in the write-through mode based on the power consumption information in Table 503. Since a cache miss in the read process has occurred in the instruction 916, the data at this address is stored in the cache, and since it is a cache hit, a power consumption value of 80 [μW / MHz] is obtained. WT Hit, and 80 [μW / MHz] in the 20th cycle as the power consumption of the cache operation in 1106 in FIG.

FIG. 11 shows a case where the power consumption table 401 for each MMU operation is applied to the operation of the MMU shown in FIG.
01, the power consumption table 301 for each instruction is applied to the operation of the CPU unit, and the power consumption obtained from the respective power consumption information is shown. 1101 is the number of cycles, 1102 is the executed instruction, 1103 is the power consumption obtained from the power consumption information of the power consumption table 401 for each MMU operation for the operation of the MMU unit at the time of reading the instruction, and 1104 is the time of reading the instruction. Power consumption obtained from the power consumption information of the power consumption table 501 for each cache operation for the operation of the cache unit of
Reference numeral 1105 denotes a power consumption table 4 for each MMU operation with respect to the operation of the MMU unit when data access occurs at the time of instruction execution.
Power consumption obtained from the power consumption information of No. 01 and 1106 are power consumption tables 501 for each cache operation with respect to the operation of the cache unit when data access occurs during instruction execution.
1107 indicates the power consumption obtained from the power consumption table 301 for each instruction at the time of executing the instruction, 1108 indicates 1102, 1103,
This is the power consumption of the entire processor per cycle obtained from 1104, 1105, and 1106.

When the simulation end condition is reached, the power consumption output processing 111 outputs a simulation result of the power consumption to the display device 1201 or the storage device 1204.

As described above, according to the embodiment of the present invention, the MMU is provided by the method for simulating power consumption of a semiconductor integrated circuit according to the first, second, third, and fourth aspects of the present invention. Power consumption information for each instruction with respect to a predetermined instruction and the operating states of the cache unit and the MMU unit before executing the simulation, even for a program code created using a logical address. In addition, the power consumption information is stored in the power consumption information for each of the cache unit operation and the MMU operation, and the power consumption with respect to the given program code can be obtained at high speed only by performing search and aggregation.

In particular, in the invention according to claim 2, the MM
The power consumption information for each operation of the U section is TLB hit and T
Since there is a case of LB miss, the power consumption of the MMU operation in the case where the TLB hits and the address translation is performed only by the TLB access, and in the case where the TLB miss occurs and the page table is accessed at the time of the address translation Can be accurately estimated, and the power consumption of the processor equipped with the MMU can be obtained.

According to the third aspect of the present invention, since the power consumption information for each operation of the cache unit is provided for the write-back mode and the write-through mode, when the cache mode is switched by the MMU, It is possible to accurately provide power consumption in write-back mode and write-through mode in cache operation, and to accurately determine the power consumption of a processor having a cache memory with write-back mode and write-through mode as cache operation. it can.

According to the fourth aspect of the present invention, since the power consumption information for each operation of the cache unit has a write-out item of dirty data, the page table used by the MMU is switched as a process typified by task switching. As in the case, when the writing of dirty data occurs, the power consumption of the cache operation can be accurately estimated.
Even in a program in which writing of dirty data occurs, the power consumption of the processor can be accurately estimated.

In the present embodiment, a simple table format is used as the power consumption information. However, it goes without saying that the same effect can be obtained by defining it as a function instead of a value.

[0059]

As described above, according to the present invention, before the simulation is executed, the individual instructions of the instruction set of the processor, the plurality of operations of the cache, and the operations of the MMU are controlled at the circuit level. , Power consumption information is stored from a simulation result of a gate level or an evaluation result of a real chip, and an instruction operation, a cache operation, and an MMU operation with respect to a program code given during the simulation are simulated, and the power consumption information is stored. The power consumption can be searched to find the power consumption for a given program code. Therefore, according to the present invention, in the processor including the cache memory and the MMU, the power consumption at the time of executing the program code can be obtained at high speed.

In particular, by simulating the MMU operation, in a system using logical addresses, T
It is possible to accurately estimate the power consumption in the case where the address translation is performed only by the TLB access due to the hit of the LB and in the case where the page table is accessed at the time of the address translation due to the TLB miss. Power estimation can be achieved.

Since the power consumption information for each operation of the cache unit includes information for the write-back mode and for the write-through mode, when the cache mode is switched by the MMU, the write-back mode and the write operation in the cache operation are performed. The power consumption in the through mode can be accurately searched for, and the power consumption of a processor equipped with an MMU and having a cache memory having a write-back mode and a write-through mode as a cache operation can be accurately obtained.

Also, since the power consumption information for each operation of the cache unit has a write item of dirty data,
As in the case where the page table used by the MMU is switched as a process typified by the task switching, the power consumption of the cache operation when the writing of dirty data occurs can be accurately estimated. Even in a program in which writing of dirty data occurs in a processor mounted on the processor, the power consumption of the processor can be accurately estimated.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a flow of processing when a simulation is performed in a method for simulating power consumption of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is an example of an instruction set at the time of executing a simulation according to the embodiment of the present invention.

FIG. 3 is an example of power consumption information for each instruction when executing a simulation according to the embodiment of the present invention.

FIG. 4 is an example of power consumption information for each MMU operation at the time of executing a simulation according to the embodiment of the present invention.

FIG. 5 is an example of power consumption information for each cache operation when executing a simulation according to the embodiment of the present invention.

FIG. 6 is an example of the contents of a memory area in initialization processing at the time of executing a simulation according to an embodiment of the present invention.

FIG. 7 is one of page tables for address translation in the embodiment of the present invention.

FIG. 8 is a page table of an address translation in the embodiment of the present invention.

FIG. 9 is an example of a program executed at the time of executing a simulation according to the embodiment of the present invention.

FIG. 10 shows a result at the time of executing a simulation in the embodiment of the present invention.

FIG. 11 is a calculation result of power consumption based on a result at the time of executing a simulation in the embodiment of the present invention.

FIG. 12 is an example of a configuration of a computer that performs a simulation according to the embodiment of the present invention.

FIG. 13 is an example of a simulation model according to the embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 101 Initialization processing 102 Program code reading processing 103 Instruction reading processing 104 Power consumption calculation processing of the MMU unit at the time of instruction reading 105 Power consumption calculation processing of the cache unit at the time of instruction reading 106 Instruction execution processing 107 Consumption of CPU unit at the time of instruction execution Power calculation processing 108 Power consumption calculation processing of the MMU unit at the time of instruction execution 109 Power consumption calculation processing of the cache unit at the time of instruction execution 201 An example of an instruction set 301 Power consumption information of each instruction 401 Example of power consumption information of each MMU operation 501 Example of power consumption information for each cache operation 901 Example of program executed by processor

Claims (5)

[Claims] 1. A method for simulating, in a computer, an instruction operation of a processor provided with a CPU (Central Processing Unit), a cache, and an MMU (Memory Management Mechanism), the method comprising: The power consumed when each instruction is executed for the set is obtained and stored as power consumption information for each instruction. The power consumed for each operation is obtained for a plurality of operations of the cache, and the power consumption for each cache operation is obtained. The power consumption is stored as power information, the power consumed for each operation of the plurality of operations of the MMU is obtained, and stored as power consumption information for each MMU operation. Simulates the instruction operation, cache operation and MMU operation In addition, a cache corresponding to a cache operation generated by a bus access based on the power consumption information for each cache operation is obtained based on the power consumption information for each instruction. The power consumption of the MMU unit corresponding to the MMU operation generated by the address translation and the page table access is obtained based on the power consumption information for each MMU operation. A power consumption simulation method for a semiconductor integrated circuit, wherein power consumption of the processor during execution of the program code is obtained from power consumption of a cache unit and power consumption of the MMU unit. 2. The power consumption information for each MMU operation is at least power consumption information that distinguishes between an operation when a hit occurs in a TLB (address translation buffer) incorporated in the MMU and an operation when a miss occurs. When a simulation is performed for a given program code, for each instruction, if the TLB hits a logical address output from the CPU unit, based on the power consumption information when the TLB hits, 2. The semiconductor according to claim 1, wherein the power consumption of the MMU unit is obtained, and when the TLB misses, the power consumption of the MMU unit is obtained based on power consumption information when the TLB misses. A power consumption simulation method for an integrated circuit. 3. The power consumption information for each cache operation includes information for a write-back mode and an information for a write-through mode. If the result of the address conversion of the output logical address is an address for performing a cache operation in the write-back mode, the power consumption for each cache operation is obtained based on the power-consumption information for the write-back mode. 3. The power consumption for each cache operation is determined based on the power consumption information for the write-through mode when the result of the operation is an address for performing a cache operation in the write-through mode. 3. A method for simulating power consumption of a semiconductor integrated circuit according to item 1. 4. The power consumption information for each cache operation includes, during a cache write operation, data of dirty data that is updated only in data stored in the cache and is inconsistent with data in a main memory at a corresponding address. This is information that distinguishes the write operation to the main memory. When the dirty data is written for each instruction during the simulation of a given program code, the power consumption information for each cache operation is included. 4. The power consumption simulation method for a semiconductor integrated circuit according to claim 1, wherein the power consumption of the cache unit is obtained based on power consumption information for the dirty data write operation. 5. During the execution of the simulation, information necessary for calculating the power consumption is stored in a storage device, and after the simulation, the simulation is performed based on the information required for calculating the power consumption stored in the storage device. 5. The method for simulating power consumption of a semiconductor integrated circuit according to claim 1, wherein the power consumption of the circuit during the circuit operation is obtained.