JP2000148584A - Prefetching method and device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the waiting time of a processor and to make it possible to execute a high speed program without requiring the generation of a prefetching instruction by a compiller and chang-ing data stored in a cache memory. SOLUTION: In the prefetching method, a state that a read request address from a processor 4 to a main storage 2 is a prefetching space is discriminated, and then data are prefetched and stored in a prefetch buffer 30 independently of the operation of the processor 4. When the processor 4 requests data stored in the buffer 30, data are supplied from the buffer 30 to the processor 40.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a prefetch method and apparatus in a processor, and more particularly, to a prefetch technique in which data fetch is performed in advance of data fetch in order to reduce the waiting time of data fetch from a storage device.

[0002]

2. Description of the Related Art In recent years, as the functions and speed of microprocessor-based products have become higher and higher, they have been increasingly used for signal processing represented by media processing. In signal processing, there are many stream filter processes for reading data in a memory, performing an operation, and then writing the data to the memory for a set of data.

[0003] Since individual data of a data set handled in the stream filter processing is rarely reused by a microprocessor (hereinafter simply referred to as a "processor"), it is not expected that a cache hit will occur. This is because data to be handled by the stream filter is generated outside the processor, and is used outside the processor after being processed by the processor.

When loading such data, the processor has to wait for a memory access wait time. One technique used to reduce this waiting time is prefetch. As a conventional prefetch device and a prefetch method, there are a device that is realized by a prefetch instruction and a device that realizes a prefetch function by a cache memory.

A prefetch instruction is disclosed in, for example,
As disclosed in Japanese Patent No. 5025, after functioning as a normal load instruction, a block (for example, 16 bytes) including loaded data is read from a memory and held in a prefetch buffer. At this time, the address of the read block is also held at the same time. After executing the prefetch instruction, when another load instruction is executed and a read request is issued to the memory, if the requested address requests data in a block held in the prefetch buffer, the data requested from the prefetch buffer To the processor. Although the waiting time for the memory access is generated from the time of the prefetch instruction, the waiting time does not occur in the processor because it operates independently of the operation of the processor. When reading data (for example, (A + 4) data) prefetched by a load instruction after the memory access of the prefetch instruction is completed, the memory access waiting time of the processor can be reduced.

FIG. 10 is a diagram for explaining the operation of a conventional prefetch device using a prefetch instruction. “Ldpf
The (A), r0 "instruction is an instruction for reading (loading) the data at the address (A) from the memory and storing the data in the register r0. After executing the loading for the address (A), the data after the address (A + 4) is successively read. Read from the memory and hold it in the prefetch buffer.
The instruction "4), r1" is an instruction for loading the data at the address (A + 4) and holding the data in the register r1.
After the execution of the (A), r0 "instruction, a waiting time has occurred to load the data at the address A, but" ld (A +
4) When the "r1" instruction is executed, the desired data is already held in the prefetch buffer and the data is supplied from the prefetch buffer, so that there is no load waiting time.

When the prefetch function is realized by the cache memory, each entry of the cache memory functions as a prefetch buffer. When reading data at a certain address from memory in the first load instruction,
A cache block, which is a management unit of the cache memory, is fetched to an appropriate entry by a cache miss. Thereby, the same effect as that of the prefetch can be obtained. FIG. 11 is a diagram illustrating the operation of a conventional prefetch device using a cache memory. "Ld (A), r
The 0 "instruction is an instruction for reading data at address (A) from the memory and holding it in the register r0. When this load instruction causes a cache miss, the cache memory reads a cache block including the data at address (A) from the memory. , And hold (refill) in an appropriate entry.The address (A +
Assuming that the data of 4) is also included, when the next load instruction “ld (A + 4), r1” is executed, the data of address (A + 4) is already stored in an appropriate entry of the cache memory. By transferring data from the cache memory without reading from the memory, there is no waiting time for reading the memory for the address (A + 4).

[0008]

However, there is a problem that it is difficult to generate an instruction by a compiler in the above-described conventional prefetch apparatus using a prefetch instruction. That is, the realization by the prefetch instruction requires the use of the prefetch instruction and the normal load instruction in distinction. However, a general high-level language such as the C language uses data (hereinafter, referred to as a stream filter).
(Hereinafter simply referred to as “stream data”), it is difficult to distinguish and generate a prefetch instruction and a normal load instruction. Also, it is similarly difficult for a language processing system to automatically determine the validity of a prefetch instruction because a very wide range of program semantic analysis is required.

On the other hand, in the above-mentioned conventional cache memory prefetch device, since stream data is stored in a cache entry, other data in the entry is evicted from the cache memory. Although the stream data remains in the cache memory, it is not reused, but the data expelled from the cache memory is data that can be reused. If the evicted data is reused, a cache miss occurs and the performance is reduced. In other words, there is a problem that performance may be degraded by replacing data that is originally better stored in the cache memory with stream data.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problem. It is not necessary to generate a prefetch instruction by a compiler, the data held in the cache memory does not change, the waiting time of the processor can be reduced, and the speed of the processor can be reduced. It is an object of the present invention to provide a prefetch method and a device capable of executing the program of (1).

[0011]

According to a first aspect of the present invention, there is provided a prefetch apparatus comprising: a space determination unit configured to determine that a read request address to a storage device of a processor is a prefetch space; and an address generation unit configured to generate a prefetch address. When the data reading means for reading the corresponding data from the storage device using the prefetch address obtained by the address generation means and the read request address to the storage device of the processor are determined to be the prefetch space by the space determination means A prefetch means having a prefetch buffer for reading and holding data by the data reading means irrespective of a read request to the storage device of the processor, and a read request address for the storage device of the processor held in the prefetch buffer. Address match detecting means for detecting a match with the address of the data to be read, and data transfer means for transferring the data held in the prefetch buffer to the processor when a match is detected by the address match detecting means. It is a thing.

According to the first aspect of the present invention, when the processor issues a read request to the prefetch space, the prefetch apparatus reads data from the main memory regardless of the operation of the processor and holds the data in the prefetch buffer. Thereafter, when the processor issues a read request to the prefetch space, if the address is the address of the data held in the prefetch buffer, the data is not read from the main memory, but is stored in the prefetch buffer instead. Transfer data to the processor. That is, when the address of the read request to the prefetch space of the processor matches the prefetch address assumed by the prefetch device, the waiting time for the read request to the prefetch space of the processor does not occur, so that high-speed program execution is performed. Can be performed.

Since the instruction for issuing a read request to the prefetch space is the same instruction as the instruction for issuing a read request to the cache space or the normal space, it is necessary for the compiler to generate an instruction while distinguishing the prefetch space from other spaces. There is an effect that there is no.

Further, the cache memory does not operate by executing an instruction for issuing a read request to the prefetch space, and the data held in the cache memory does not change. Therefore, the hit rate of the cache memory does not decrease due to the prefetch of the stream data or the like.

According to a second aspect of the present invention, there is provided a prefetch apparatus according to the first aspect, further comprising: an iterative prefetch means for repeating data reading by the prefetch means; and a prefetch ending means for terminating the iterative prefetch means.

According to the prefetch device of the second aspect, the same effect as that of the first aspect is obtained.

According to a third aspect of the present invention, there is provided the prefetch device according to the second aspect, wherein the number of times the repetitive prefetch means is performed is counted, and the value set in the control register and the prefetch means counted by the number count means. And a means for terminating the repetitive prefetch means when a match is detected by the number-of-times matching means.

According to the prefetch device of the third aspect, the same effect as that of the first aspect is obtained.

According to a fourth aspect of the present invention, there is provided the prefetch device according to the second aspect, wherein the data size counting means for counting the size of the data held in the prefetch buffer by the iterative prefetch means, and the data size and the data size set in the control register. Terminates the data size match detecting means for detecting that the size of the data held in the prefetch buffer obtained by the counting means matches, and terminates the iterative prefetch means if the data size match detecting means detects a match. It is provided with means for performing.

According to the prefetch device of the fourth aspect, the same effect as that of the first aspect is obtained.

According to a fifth aspect of the present invention, there is provided a prefetch apparatus according to the second aspect, wherein an end address detecting means for detecting that an address generated by the address generating means of the iterative prefetch means matches an address set in the control register; When a match is detected by the end address detecting means, means for terminating the repetitive prefetch means is provided.

According to the prefetch device of the fifth aspect, the same effect as that of the first aspect is obtained.

According to a sixth aspect of the present invention, in the first aspect, the address generating means generates an address by adding a value set in a control register to a read request address to the storage device of the processor. is there.

According to the prefetch device of the sixth aspect, the same effect as that of the first aspect is obtained.

According to a seventh aspect of the present invention, in the prefetch device according to the first aspect, the address generation means performs an operation determined by information set in a control register on a read request address to the storage device of the processor. This is a means for generating an address.

According to the prefetch device of the seventh aspect, the same effect as that of the first aspect is obtained.

An eighth aspect of the present invention provides the prefetch device according to any one of the third to seventh aspects, further comprising means for rewriting the control register by the processor.

According to the prefetch device of the eighth aspect, the same effect as that of the first aspect is obtained.

According to a ninth aspect of the present invention, there is provided the prefetch device according to the first aspect, wherein the first and second iterative prefetch means for repeating data reading by the prefetch means;
The first iterative prefetch means is started by the first read request address to the storage device of the processor, and is held in the prefetch buffer by the second read request address to the storage device of the processor and the first iterative prefetch means. When the address coincidence detecting means detects that the address of the data does not match, the means for terminating the first iterative prefetch means and starting the second iterative prefetch means is provided.

According to the prefetch device of the ninth aspect, the same effect as that of the first aspect is obtained.

According to a tenth aspect of the present invention, in the first aspect, when the data in the prefetch buffer is transferred to the processor by the data transfer means, the data held in the prefetch buffer is invalidated from the prefetch buffer. Means.

According to the prefetch device of the tenth aspect, the same effect as that of the first aspect is obtained.

In the prefetch device according to the present invention, when the address match detection means detects that the address of the read request to the storage device of the processor does not match the address of the data held in the prefetch buffer, , Means for invalidating the data held in the prefetch buffer.

According to the prefetch device of the eleventh aspect, the same effect as that of the first aspect is obtained.

According to a twelfth aspect of the present invention, there is provided a prefetch method, comprising: a space determining step of determining that a read request address to a storage device of a processor is a prefetch space; an address generating step of generating a prefetch address; A data reading step for reading out corresponding data from the storage device using the obtained prefetch address; and a read request address for the storage device of the processor to the storage device of the processor when it is determined in the space determination step that the address is a prefetch space. The data is read in the data read step regardless of the read request of the processor, and the data is read and stored in the prefetch buffer. The read request address to the storage device of the processor is stored in the prefetch buffer. An address match detecting step of detecting that the address matches the address of the data being written, and a data transfer step of transferring the data held in the prefetch buffer to the processor when a match is detected by the address match detecting step. Is included.

According to the prefetch method of the twelfth aspect, the same effect as that of the first aspect can be obtained.

According to a thirteenth aspect of the present invention, there is provided the prefetch method according to the twelfth aspect, wherein an iterative prefetch step of repeating data reading in the prefetch step;
And a prefetch termination step for terminating the repetitive prefetch step.

According to the prefetch method of the thirteenth aspect, the same effect as that of the first aspect can be obtained.

According to a fourteenth aspect of the present invention, there is provided the prefetch method according to the thirteenth aspect, wherein the number of times the repetitive prefetch step is performed is counted, and the prefetch step counted by the value set in the control register and the number of times is counted. And a step of terminating the iterative prefetch step when a match is detected in the number matching step.

According to the prefetch method of the fourteenth aspect, the same effect as that of the first aspect is obtained.

According to a fifteenth aspect of the present invention, in the thirteenth aspect, there is provided a data size counting step for counting the size of data held in the prefetch buffer by the iterative prefetch step, and a data size and a data size set in the control register. A data size match detecting step for detecting that the size of the data held in the prefetch buffer obtained by the counting step matches, and if a match is detected by the data size match detecting step, the iterative prefetch step is terminated. The step includes:

According to the prefetching method of the fifteenth aspect, the same effect as that of the first aspect is obtained.

In the prefetch method according to a sixteenth aspect, in the thirteenth aspect, an end address detection step of detecting that an address generated by the address generation step of the iterative prefetch step matches an address set in the control register, When a match is detected by the end address detecting step, the step includes ending the repetitive prefetch step.

According to the prefetch method of the sixteenth aspect, the same effect as that of the first aspect can be obtained.

According to a seventeenth aspect of the present invention, in the twelfth aspect, the address generating step includes the step of generating an address by adding a value set in a control register to a read request address to the storage device of the processor. is there.

According to the prefetch method of the seventeenth aspect, the same effect as that of the first aspect can be obtained.

In the prefetch method according to the present invention, in the twelfth aspect, the address generating step performs an operation determined by information set in a control register on a read request address to a storage device of the processor. This is the step of generating an address.

According to the prefetch method of the eighteenth aspect, the same effect as that of the first aspect can be obtained.

A prefetch method according to claim 19 includes the step of rewriting a control register by a processor according to any one of claims 14 to 18.

According to the prefetch method of the nineteenth aspect, the same effect as that of the first aspect can be obtained.

According to a twentieth aspect of the present invention, in the twelfth aspect, the first and second iterative prefetch steps of repeating the data reading in the prefetch step and the first read request address to the storage device of the processor. One iterative prefetch step is started, and an address match detection is made that the second read request address to the storage device of the processor does not match the address of the data held in the prefetch buffer by the first iterative prefetch step. If detected by the step, the method includes ending the first iterative prefetch step and starting the second iterative prefetch step.

According to the prefetch method of the twentieth aspect, the same effect as that of the first aspect can be obtained.

According to a twenty-first aspect of the present invention, in the twelfth aspect, when the data of the prefetch buffer is transferred to the processor by the data transfer step,
The method includes an invalidating step of invalidating the data held in the prefetch buffer from the prefetch buffer.

According to the prefetch method of the twenty-first aspect, the same effect as that of the first aspect can be obtained.

According to a twelfth aspect of the present invention, in the twelfth aspect, when the address match detection step detects that the read request address to the storage device of the processor and the address of the data held in the prefetch buffer do not match. , Invalidating the data held in the prefetch buffer.

According to the prefetching method of the twenty-second aspect, the same effect as that of the first aspect is obtained.

[0057]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A prefetch method according to a first embodiment of the present invention will be described below with reference to FIGS. 1 to 6 using a prefetch device. FIG. 1 shows the first embodiment of the present invention.
FIG. 3 is a block diagram showing a hardware configuration diagram of a system including a prefetch device according to the embodiment. 1 is a prefetch device, 2 is a main memory as a storage device, 3
Is an instruction memory in which instructions are stored, and 4 has a function as a normal processor, including a function of performing processing in accordance with the instructions stored in the instruction memory 3 and making a request to read data from the main memory 2 as necessary. The processor 5 is a cache memory having a function of storing a copy of data read from the main memory 2 by the processor 4 and a function as a normal cache memory.

In the prefetch device 1, reference numeral 10 denotes an address space discriminating circuit for discriminating an address space by referring to an address output from the processor 4, and corresponds to a space discriminating means described in claims.

Reference numeral 20 denotes a prefetch address generating circuit for generating a prefetch address based on the address output from the processor 4, and corresponds to an address generating means described in claims. FIG. 6 is a block diagram of the prefetch address generation circuit 20 according to the first embodiment of the present invention. Reference numeral 21 denotes a buffer for holding an address used for generating the next prefetch address. Reference numeral 22 denotes a multiplexer for selecting an address output from the processor 4 and an address output from the prefetch address generation circuit 20 and outputting the selected address to the buffer 21. Is an adder for adding the address held in the buffer 21 and the address of the processor 4.

Returning to FIG. 1, reference numeral 30 denotes a prefetch buffer for holding data read from the main memory 2 by prefetch. The data read means and the prefetch buffer 30 correspond to the prefetch means. .

Reference numeral 40 denotes a prefetch address generation circuit 20
Is a prefetch address buffer for holding the address output from the prefetch control circuit 1 and compares the address output from the processor 4 with the address stored in the prefetch address buffer 40 and outputs a match signal.
The prefetch address buffer 40 and the comparison circuit 50 correspond to the address coincidence detecting means. When a match is detected by the comparison circuit 50, the data held in the prefetch buffer 30 is transferred to the processor 4 by the data transfer means, and when the data in the prefetch buffer 30 is transferred to the processor 4 by the data transfer means, Invalidating means invalidates the data held in the prefetch buffer 30 from the prefetch buffer. The data transfer means corresponds to the multiplexer 102 in FIG. 1, and the invalidating means corresponds to the prefetch address buffer 40 and the prefetch control circuit 100. That is, when the internal state of the prefetch control circuit 100 is in the prefetch state, it is invalid.

Reference numeral 100 denotes a prefetch control circuit for controlling the whole of the prefetch device 1, which has an internal state shown in FIG.
Has three states of “non-prefetch state”, “prefetch state”, and “prefetch wait state” shown in FIG. The “non-prefetch state” is a state in which prefetching is not performed, and the “prefetch state” transits from the “non-prefetch state” when it is determined that the read request address of the processor 4 is in the prefetch space. Prefetch is performed for a while. The “prefetch waiting state” is a state in which data is held in the prefetch buffer 30 and prefetch cannot be performed any more. Since only one data can be held in the prefetch buffer 30, when data is read in the "prefetch state", the state transits to the "prefetch wait state". When the data in the prefetch buffer 30 is transferred to the processor 4, the data in the prefetch buffer 30 is invalidated, so that the state returns to the “prefetch state”.

Returning to FIG. 1, reference numeral 101 denotes a multiplexer that selects an address output from the processor 4 and an address output from the prefetch address generation circuit 20 and outputs the selected address to the main memory 2. A multiplexer that selects data and data output from the prefetch buffer 30 and outputs the selected data to the processor 4.

FIG. 3 shows an address space map in a system provided with the prefetch device 1 of the present invention.
The address in the system according to the present embodiment has a width of 32 bits. The total address space has three spaces,
It is divided into "normal space", "prefetch space", and "cache space", and the normal space has an address of 0x000.
0000 to 0x3FFFFFFF, and the prefetch space has addresses 0x40000000 to 0x
7FFFFFFF, and the cache space is allocated to addresses 0x80000000 to 0xFFFFFFFF. That is, it is possible to determine the space to which the address belongs only by referring to the upper two bits of the address. Note that “0x” is a prefix indicating a hexadecimal number.

In the "prefetch space", data which is continuously accessed by the processor 4 and is used only once by the processor 4 is arranged. This is, for example, data that is generated outside the processor 4 and stored in the main memory 2 such as stream data. When the processor 4 reads the data, the data in the main memory 2 is replaced with new data. I have. In the first embodiment, the prefetch device 1 operates when the processor 4 issues a read request to the “prefetch space”.

In the “cache space”, data reusable by the processor is arranged. Once the data arranged in the “cache space” is read by the processor 4, it is copied to the cache memory 5, the data of the cache memory 5 is supplied to the processor 4 from the next time, and the data of the main memory 2 is not read. Further, the prefetch device 1 does not operate.

When the processor 4 accesses the "normal space", the prefetch device 1 and the cache memory 5 do not operate, and the main memory 2 is accessed directly. Although "normal space" is not used in the description of the operation in the first embodiment, an address space such as "normal space" is required in a system including the actual prefetch device 1.

FIG. 4 shows an example of a program used in the description of the present embodiment. Instructions i0 to i1 in the example program
“0” is stored in the instruction memory 3 and is sequentially read and executed by the processor 4.

Hereinafter, each instruction will be described. Instruction i
0, i1, and i2 are 0x40000100 and 0x, respectively.
80000100, 256 are stored in registers r0, r1, r2.
Are used as a load address of the instruction i3, a load address of the instruction i4, and a loop counter, respectively.

The instruction i3 is an instruction to read 4-byte data from the main memory 2 by using the value of the register r0 as an address and store it in the register r3. The instruction i4 is an instruction i4.
Is an instruction to read 4-byte data from the main memory 2 using the value of the address as an address and store it in the register r4.

The instruction i5 is a product-sum instruction that multiplies the value of the register r3 by the value of the register r4, adds the result to the value of the product-sum register M, and stores the result in the register M. It is assumed that the register M is implicitly specified.

Instructions i6 and i7 are respectively stored in registers r0,
This is an instruction to add 4 to r1. Registers r0 and r1 are used as addresses of 4-byte data in instructions i3 and i4, respectively, and add 4 to update to the address of the next 4-byte data. Since this program example has a loop structure, the instruction i3 and the instruction i4
Will be executed repeatedly. Therefore, 0x4
Subsequent data of 0000100 and 0x800000100 will be continuously accessed in units of 4 bytes.

The instruction i8 is an instruction for adding -1 to the register r2, the instruction i9 is an instruction for comparing the register r2 with 0, and the instruction i10 is a comparison result of the instruction i9.
If 2 is larger, the instruction branches to the label “loop”; otherwise, the instruction does not branch. The register r2 is used as a counter that counts the number of times of the loop configured in the present program example.
Form a loop of 256 times. In this case, the prefetch means is constituted by an iterative prefetch means for repeating data reading and a prefetch ending means for terminating the iterative prefetch means.

FIG. 5 is a diagram showing operation waveforms when the processor 4 executes the example of the program shown in FIG. C
0 to C20 represent each cycle, C0 to C10 represent the first loop of the instructions i3 to i10 of the program example in FIG. 4, and C11 to C18 represent the second loop. .

In FIG. 5, "processor execution instruction"
Represents the instruction executed by the processor 4 in each cycle, and the “processor address” represents the address output by the processor 4. “Read request” of “Prefetch device from processor” is processor 4
Is a read request signal to the prefetch device 1 of
“Acknowledge” is the processor 4 of the prefetch device 1
Represents an acknowledgment signal with respect to. Each signal is assumed to be in an active state when in a high state.

Similarly, "read request" of "prefetch device to main memory" is a read request signal for main memory 2 of prefetch device 1, and "acknowledge" is main memory 2
3 shows an acknowledge signal for the prefetch device 1. Similarly, it is assumed that each signal is in the active state when it is in the high state.

The waveform of “main memory” indicates a read operation of the main memory 2, and the value in the waveform diagram indicates an address at the time of reading. In the first embodiment, the main memory 2
Is completed in four cycles.

The waveform of the “prefetch address buffer” indicates the address held in the prefetch address buffer 40, and the waveform of the “prefetch buffer” indicates the data held in the prefetch buffer 30. The value in the waveform diagram of the prefetch buffer is an address, which indicates that data read at that address is held. Note that a black portion indicates that the stored data is invalid.

The waveform of “internal state of prefetch control circuit” indicates the internal state of prefetch control circuit 100 shown in FIG.

Hereinafter, the operation of the system including the prefetch device of the first embodiment in the example of the program of FIG. 4 will be described.

First, the processor 4 executes the instructions i0 to i2 and stores 0x400 in the registers r0, r1, r2 respectively.
00100, 0x800000100, 256 are stored. This part is not shown in FIG.

Next, the processor 4 executes the instruction i3. The instruction i3 has a value 0x4 stored in the register r0.
This is an instruction to read data from the main memory 2 using 0000100 as an address. The state where the processor 4 is executing the instruction i3 is shown at C0 in FIG. In response to the instruction i3, the processor 4 outputs a read request signal to the prefetch device 1 and at the same time, the address 0x40000100
Is output to the multiplexer 101. In the prefetch device 1, the read request signal output from the processor 4 is input to the prefetch control circuit 100. At this time, the cache memory 5 does not operate because the address space of the read request address is different from the cache space.

The prefetch control circuit 100 selects the address output from the processor 4 by controlling the multiplexer 101 based on the read request signal output from the processor 4 and sends it to the main memory 2. Is output.

On the other hand, the address space discriminating circuit 10 judges that the address is 0x40000100 from the processor 4 as the prefetch space, and outputs a signal to that effect to the prefetch control circuit 100. The prefetch control circuit 100 changes the internal state to the “prefetch state” according to the signal output from the address space determination circuit 10 and the read request signal from the processor 4, controls the prefetch address generation circuit 20, and controls the address output from the processor 4. In the buffer 21 (FIG. 6).

C1 and C2 are cycles waiting for reading of the main memory 2. The reading of the main memory 2 is performed in four cycles, and the instruction i3 cannot proceed to the next instruction until the data reading is completed, so that the instruction i3 is being executed.

In C3, the main memory 2 has the address 0x400
The data of 00100 is output to the read multiplexer 102, and an acknowledge signal is output to the prefetch control circuit 100. Prefetch control circuit 100
Controls the multiplexer 102, outputs the data output from the main memory 2 to the processor 4, and outputs an acknowledge signal to the processor 4. Since the cache memory 5 is not operating, the data output from the main memory 2 is not taken into the cache memory 5.

At C4, the processor 4 executes the instruction i4. The instruction i4 is an ld instruction, but the address is 0x80.
000100, that is, a read request to the cache space, the cache memory 5 operates. Here, since the cache memory 5 hits, the processor 4 does not wait for data, can complete the instruction i4, and can immediately start executing the instruction i5. Since the cache memory 5 is said to hit,
The prefetch device 1 and the main memory 2 are not accessed and do not operate.

On the other hand, since the internal state of the prefetch control circuit 100 is "prefetch state", the prefetch operation for the main memory 2 is started. The prefetch operation is performed independently of the operation of the processor 4. First,
The prefetch control circuit 100 controls the prefetch address generation circuit 20 to generate the first prefetch address. Prefetch address generation circuit 2
0 is the address 0x40000 held in the buffer 21
Value 0x40000 obtained by adding 100 and value 4 by the adder 23
104 is output to the multiplexer 101. Further, it controls the multiplexer 101 to output the address 0x40000104 output from the prefetch address generation circuit 20 to the main memory 2 and outputs a read request signal to the main memory 2 at the same time. Address 0x400 in main memory 2
The data of 00104 is read out over four cycles.

In C5 and C6, the processor 4 executes the instruction i5,
While the instruction i6 is being executed, the main memory 2 is not accessed during this time.

At C7, the main memory 2 completes the prefetch operation and stores the read data in the prefetch buffer 30.
And an acknowledgment signal to the prefetch control circuit 100. The prefetch control circuit 100 causes the prefetch buffer 30 to hold the data of the main memory 2 and the prefetch address buffer 40 to hold the address output from the prefetch address generation circuit 20 in response to the acknowledge signal of the main memory 2. Further, the prefetch control circuit 100 changes the internal state from the “prefetch state” to the “prefetch wait state”. The prefetch address generation circuit 20 outputs the currently output address 0x400001.
0x40000 where 04 was retained inside and 4 was added
108 is output. These operations do not affect the instruction execution of the processor 4.

In C8 to C10, the processor 4 executes the instruction i8
To i10, but does not access the main memory 2 during this time.

According to the instructions i6 to i8, the values of the registers r0, r1, and r2 of the processor 4 are respectively 0x400001.
04, 0x80000100, 255. Instruction i9
Compares the value of the register r2 with the value 0,
2 is "larger", the instruction "i10" causes the label "lo"
The branch to “op” is taken, and the first loop ends.
From the next C11, the instruction i3 is executed.

At C11, the processor 4 executes the instruction i3 again. Since the instruction i3 is an ld instruction, the processor 4
Outputs 0x40000104, which is the value of the register r0, as an address, and outputs a read request signal to the prefetch control circuit 100. Here, the address 0x40000104 is held in the prefetch address buffer 40, and the comparison circuit 50 compares the address with the address output from the processor 4 to detect a match, and outputs a match signal to the prefetch control circuit 100. The prefetch control circuit 100 controls the multiplexer 102 based on the read request signal of the processor 4 and the coincidence signal of the comparison circuit 50, outputs the data of the address 0x40000104 held in the prefetch buffer 30 to the processor 4, and outputs the acknowledgment signal. Output to the processor 4. In this case, the ld instruction of the instruction i3 has one cycle (0
Cycle wait). At this time, the cache memory 5 does not operate because the address space of the read request address is different from the cache space.

On the other hand, the data held in the prefetch buffer 30 is invalidated because the transfer to the processor 4 is completed, and the prefetch control circuit 100 changes the internal state from the “prefetch wait state” to the “prefetch state”.

At C12, the processor 4 executes the instruction i4. The instruction i4 is an ld instruction, but the address is 0x8
0000104, that is, a read request to the cache space, the cache memory 5 operates. Here, since the cache memory 5 hits, the processor 4 does not wait for data, can complete the instruction i4, and can immediately start executing the instruction i5. Since the cache memory 5 is said to hit,
The prefetch device 1 and the main memory 2 are not accessed and do not operate.

On the other hand, since the internal state of the prefetch control circuit 100 is in the "prefetch state", the prefetch operation for the main memory 2 is started regardless of the instruction operation of the processor 4. The prefetch control circuit 100 outputs a read request signal to the main memory 2 and controls the multiplexer 101 to control the address 0x4000010 output from the prefetch address generation circuit 20 at the same time.
8 is output to the main memory 2.

After C13, the first loop, C5
It operates in the same manner as the following. In particular, prefetch buffer 3
The data held at 0 is then transmitted by the processor 4 to the instruction i.
3 is transferred to the processor 4 without reading the main memory 2, and the processor 4 executes the instruction i3
There is no need to wait for completion.

As described above, according to the prefetch device of the embodiment of the present invention, the first instruction i3
, The prefetch device 1 reads the subsequent address data from the main memory 2 and stores it in the prefetch buffer 30 irrespective of the operation of the processor 4. Thereafter, when the data of the address is held in the prefetch buffer 30 by a read request from the processor 4, the data is sent from the prefetch buffer 30 to the processor 4 without accessing the main memory 2. Therefore, processor 4
Can perform high-speed reading without waiting for reading from the main memory 2.

Further, when the address of the read request to the prefetch space matches the prefetch address assumed by the prefetch device 1 as in the program of FIG. 4, the waiting time of the read request to the prefetch space of the processor 4 Therefore, a program such as a stream filter can be executed at high speed.

According to the first embodiment of the present invention, the instruction i3 and the instruction i4 are the same ld instructions, and the compiler can execute the instruction without distinguishing between access to the prefetch space and access to the cache space. Can be generated.

Further, by executing the instruction i3, the cache memory 5 does not operate, and the data held in the cache memory 5 does not change. Therefore, the hit rate of the cache memory due to the prefetch does not decrease.

Here, for example, the instruction i3 is an instruction to access the cache space, and the address of the instruction i3 and the instruction i
In the case where the address 4 occupies the same entry in the cache memory 5, the data read by the instruction i4 is evicted from the cache memory 5 due to the cache miss caused by the execution of the instruction i3. Becomes Further, when the program example of the present embodiment is executed at the next opportunity, since the data of the instruction i3 is generated externally and stored in the main memory 2, the data remaining in the cache memory 5 is discarded. I have to. Thus, holding the data of the instruction i3 in the cache memory 5 is not only wasteful, but holding the data in the cache memory 5 such as the instruction i4 may result in expelling even valid data. According to the embodiment of the present invention, the cache memory 5 does not operate in response to the instruction i3, and the same operation as the cache memory 5 can be performed.

In the above description of the operation, for example, C
In step 11, if the read request address of the processor 4 does not match the address held in the prefetch address buffer 40 and the comparison circuit 50 detects that the address is in the prefetch space, the prefetch buffer 30 The data is discarded, the data requested by the processor 4 is read out again from the main memory 2 and stored in the prefetch buffer 30, and at the same time, the address at that time is stored in the prefetch address buffer 40. The address output from the processor 4 is also held in the buffer 21 of the prefetch address generation circuit 20, and is used for the subsequent prefetch. Thus, the prefetch device 1
If the processor 4 outputs an address in a prefetch space different from the address assumed by the processor 4, no malfunction occurs.

The first and second iterative prefetch means are started by the first and second iterative prefetch means for repeating reading of data in the prefetch buffer 30 and the first read request address to the main memory 2 of the processor 4. When the comparison circuit 50 detects that the second read request address to the main memory 2 of the processor 4 does not match the address of the data held in the prefetch buffer by the first repetitive prefetch means. , The first iterative prefetch means is terminated, and the second iterative prefetch means is started.

Although the prefetch address generation circuit 20 according to the embodiment of the present invention shows an example of adding 4 as shown in FIG. 6, a value other than 4 may be used. The same effect can be obtained by calculation.

When the address match detecting means (50) detects that the read request address of the storage device (2) of the processor 4 does not match the address of the data held in the prefetch buffer 30, the address of the prefetch buffer 30 is changed. Means for invalidating the held data may be provided.

As another embodiment of the prefetch address generation circuit, as shown in FIG. 7, a control register 25 rewritable by the processor 4 may be used to specify the operation method of the operation unit 24 and the operand. FIG.
, 24 is an operation unit capable of performing a plurality of operations on operands, 25 is an operation command and an operand to be given to the operation unit 24, and the processor 4
Is a rewritable control register. When the prefetch address generation circuit of FIG. 7 switches between, for example, the operation of inverting the bit sequence of the lower 4 bits and the case of adding 4 using the control register 25,
It is easy to generate a prefetch address in accordance with the characteristics of a program executed by the processor 4, and the effect of the present invention is further enhanced.

Further, as shown in FIG. 8, a prefetch address may be generated by adding an offset taken out of a table to an address. In FIG. 8, 2
Reference numeral 6 denotes a counter, 27 denotes a table ROM from which the offset can be read using the value of the counter 26 as an index, and 28 denotes an address obtained by adding the offset read from the table ROM 27 and the address stored in the register 21. It is an adder to be generated. The prefetch address generation circuit 20 in FIG. 8 can generate a random address only by storing a random offset in the table ROM 27, for example.

FIG. 9 is a block diagram showing a prefetch apparatus according to another embodiment having a circuit for terminating prefetch. 6. A control register for holding an end address, and a comparison circuit for comparing an address output from the prefetch address generation circuit with an address held in the control register. Corresponding to When a match is detected by the end address detection means, the repetition prefetch means is ended by the end means. Reference numeral 6 denotes a prefetch device including a control register 200 and a comparison circuit 201. Reference numeral 103 denotes a prefetch control circuit that controls the entire prefetch device 6. The prefetch device 6 and the prefetch control circuit 103 shown in FIG. 9 operate in the same manner as the prefetch device 1 and the prefetch control circuit 100 shown in FIG. 1, respectively, but the comparison circuit 201 outputs the address output from the prefetch address generation circuit 20 and the control register 20.
If it is detected that the address held at 0 matches, a signal to that effect is sent to the prefetch control circuit 10.
Output to 3. The prefetch control circuit 103 changes the internal state to the “non-prefetch state” and ends the prefetch operation. 9 are denoted by the same reference numerals as those in FIG.
And its description is omitted.

In the system including the prefetch device 6 shown in FIG. 9, the processor 4 sets an end address in the control register 200 in advance, and after the prefetch operation starts,
The address used in the prefetch operation is the control register 20
If the address is equal to the address set to 0, the prefetch operation ends. This has the effect of eliminating unnecessary prefetch operations that are not used by the processor 4.

Although FIG. 9 shows a circuit which terminates when the end address is specified and matches the prefetch address, means for counting the number of prefetches and terminating when the number of times specified by the control register is reached is obtained. However, a similar effect can be obtained. In this case, the number-of-times counting means for counting the number of times the repetitive prefetch means has been performed, and the number-of-times matching means for detecting that the value set in the control register matches the number of times of the prefetch means counted by the number-of-times counting means. When the match is detected by the number matching means, the repetition prefetch means is terminated. The same effect can be obtained by means for counting the total data size of prefetched data and ending when the data size specified by the control register is reached. In this case, the data size counting means for counting the size of the data held in the prefetch buffer by the iterative prefetch means, the data size set in the control register and the data held in the prefetch buffer obtained by the data size counting means. And a means for ending the repetitive prefetch means when a match is detected by the data size match detecting means.

The prefetch buffer 30 shown in FIGS. 1 and 9 exemplifies a configuration in which only one data read from the main memory 2 is held. However, a configuration capable of holding a plurality of data is more effective in the prefetch operation. The effect is higher.
For example, in the case of a configuration that can hold four data, even if the main memory 2 cannot be accessed for some reason, it is possible to respond to data supply to the processor 4 to some extent.

It is needless to say that the main memory 2 may be a storage device, and the same effect can be obtained with another device such as a recording medium such as a hard disk.

[0114]

According to the prefetch device of the first aspect, the processor issues a read request to the prefetch space, so that the prefetch device reads data from the main memory regardless of the operation of the processor and holds the data in the prefetch buffer. I do. Thereafter, when the processor issues a read request to the prefetch space, if the address is the address of the data held in the prefetch buffer, the data is not read from the main memory, but is stored in the prefetch buffer instead. Transfer data to the processor. That is, when the address of the read request to the prefetch space of the processor matches the prefetch address assumed by the prefetch device, there is no waiting time for the read request to the prefetch space of the processor. Can be performed.

The instruction for issuing a read request to the prefetch space is the same as the instruction for issuing a read request to the cache space or the normal space. Therefore, it is necessary for the compiler to generate instructions by distinguishing the prefetch space from other spaces. There is an effect that there is no.

Furthermore, the cache memory does not operate by executing an instruction for issuing a read request to the prefetch space, and the data held in the cache memory does not change. Therefore, the hit rate of the cache memory does not decrease due to the prefetch of the stream data or the like.

According to the prefetch device of the second aspect, the same effects as those of the first aspect can be obtained.

According to the prefetch device of the third aspect, the same effect as that of the first aspect is obtained.

According to the prefetch device of the fourth aspect, the same effect as that of the first aspect is obtained.

According to the prefetch device of the fifth aspect, the same effect as that of the first aspect is obtained.

According to the prefetch device of the sixth aspect, the same effects as those of the first aspect can be obtained.

According to the prefetch apparatus of the seventh aspect, the same effect as that of the first aspect can be obtained.

According to the prefetch device of the eighth aspect, the same effects as those of the first aspect are obtained.

According to the prefetch device of the ninth aspect, the same effect as that of the first aspect can be obtained.

According to the prefetch device of the tenth aspect, the same effect as that of the first aspect is obtained.

According to the prefetch device of the eleventh aspect, the same effect as that of the first aspect can be obtained.

According to the prefetch method of the twelfth aspect, the same effect as that of the first aspect is obtained.

According to the prefetch method of the thirteenth aspect, the same effect as that of the first aspect can be obtained.

According to the prefetch method of the fourteenth aspect, the same effect as that of the first aspect can be obtained.

According to the prefetching method of the fifteenth aspect, the same effect as that of the first aspect is obtained.

According to the prefetch method of the sixteenth aspect, the same effect as that of the first aspect can be obtained.

According to the prefetch method of the seventeenth aspect, the same effect as that of the first aspect can be obtained.

According to the prefetch method of the eighteenth aspect, the same effect as that of the first aspect can be obtained.

According to the prefetch method of the nineteenth aspect, the same effect as that of the first aspect can be obtained.

According to the prefetching method of the twentieth aspect, the same effect as that of the first aspect can be obtained.

According to the prefetch method of the twenty-first aspect, the same effect as that of the first aspect can be obtained.

According to the prefetching method of the twenty-second aspect, the same effect as that of the first aspect is obtained.

[Brief description of the drawings]

FIG. 1 is a hardware configuration diagram of a system including a prefetch device according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an internal state transition of a prefetch control circuit 100 according to the first embodiment.

FIG. 3 is an address space map for explaining the operation of the system including the prefetch device according to the first embodiment;

FIG. 4 is an explanatory diagram of an example of a program for explaining an operation of a system including a prefetch device according to the first embodiment;

FIG. 5 is an operation waveform diagram for explaining the operation of the system including the prefetch device according to the first embodiment.

FIG. 6 is a detailed block diagram of a prefetch address generation circuit 20 according to the first embodiment.

FIG. 7 is a block diagram of a prefetch address generation circuit 20 according to another embodiment of the present invention.

FIG. 8 is a block diagram of a prefetch address generation circuit 20 according to still another embodiment of the present invention.

FIG. 9 is a hardware configuration diagram of a system including a prefetch device according to still another embodiment of the present invention.

FIG. 10 is a program operation explanatory diagram for explaining the operation of a conventional prefetch device using a prefetch instruction.

FIG. 11 is a program operation explanatory diagram for explaining the operation of a prefetch device using a conventional cache memory.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Prefetch apparatus 2 Main memory 3 Instruction memory 4 Processor 5 Cache memory 10 Address space discrimination circuit 20 Prefetch address generation circuit 21 Buffer 22 Multiplexer 23 Adder 24 Arithmetic unit 25 Control register 30 Prefetch buffer 40 Prefetch address buffer 50 Comparison circuit 100 Prefetch control Circuit 101 Multiplexer 102 Multiplexer 200 Control register 201 Comparison circuit

Claims (22)

[Claims] 1. A space determining means for determining that a read request address to a storage device of a processor is a prefetch space, an address generating means for generating a prefetch address, and using the prefetch address obtained by the address generating means. Data reading means for reading out corresponding data from the storage device, and if the read request address to the storage device of the processor is determined to be the prefetch space by the space determination means, the storage device of the processor. A prefetch means having a prefetch buffer for reading and holding data by the data reading means irrespective of a read request to the memory; and a read request address to the storage device of the processor is held in the prefetch buffer. Address match detecting means for detecting a match with an address of data to be transferred, and data transfer means for transferring data held in the prefetch buffer to the processor when a match is detected by the address match detecting means. A prefetch device comprising: 2. The prefetch apparatus according to claim 1, further comprising: iterative prefetch means for repeating data reading by said prefetch means; and prefetch ending means for terminating said iterative prefetch means. 3. A number-of-times counting means for counting the number of times the repetitive prefetch means has been performed, and a number of times for detecting that the value set in the control register matches the number of times of the prefetch means counted by the number-of-times counting means. 3. The prefetch apparatus according to claim 2, further comprising a coincidence unit, and a unit for terminating the repetitive prefetch unit when a coincidence is detected by the number-of-times coincidence unit. 4. A data size counting means for counting the size of data held in a prefetch buffer by an iterative prefetch means, and a data size set in a control register and held in the prefetch buffer obtained by the data size counting means. 3. A data size match detecting means for detecting that the size of the data matches the data size, and means for terminating the iterative prefetch means when a match is detected by the data size match detecting means. Prefetch device. 5. An ending address detecting means for detecting that an address generated by an address generating means of an iterative prefetch means matches an address set in a control register; and, when a match is detected by the ending address detecting means, 3. The prefetch apparatus according to claim 2, further comprising means for terminating said iterative prefetch means. 6. The prefetch apparatus according to claim 1, wherein the address generating means is means for generating an address by adding a value set in a control register to a read request address of the storage device of the processor. 7. The address generation means according to claim 1, wherein the address generation means generates an address by performing an operation determined by information set in a control register on a read request address to the storage device of the processor. Prefetch device. 8. The method according to claim 3, further comprising means for rewriting the control register by a processor.
A prefetch device according to the item. 9. A first and second iterative prefetch means for repeating reading of data in the prefetch means;
The first iterative prefetch means is started by the first read request address to the storage device of the processor, and is held in the prefetch buffer by the second read request address to the storage device of the processor and the first iterative prefetch means. If the address match detecting means detects that the address of the data does not match, the first iterative prefetch means is terminated and the second iterative prefetch means is terminated.
2. A prefetch apparatus according to claim 1, further comprising means for starting said iterative prefetch means. 10. The prefetch apparatus according to claim 1, further comprising invalidating means for invalidating the data held in the prefetch buffer from the prefetch buffer when data in the prefetch buffer is transferred to the processor by the data transfer means. 11. When the address match detecting means detects that the read request address to the storage device of the processor does not match the address of the data held in the prefetch buffer, the data held in the prefetch buffer is invalidated. 2. The prefetch apparatus according to claim 1, further comprising: means. 12. A space discriminating step for discriminating that a read request address to a storage device of a processor is a prefetch space, an address generating step for generating a prefetch address, and using the prefetch address obtained in the address generating step. A data reading step for reading out corresponding data from the storage device, and if the read request address to the storage device of the processor is determined to be the prefetch space by the space determination step, the storage device of the processor A prefetch step in which data is read by the data read step and held in a prefetch buffer irrespective of a read request to the storage device; An address match detecting step of detecting that the address matches the address of the data held in the buffer, and when a match is detected by the address match detecting step, transferring the data held in the prefetch buffer to the processor. And a data transfer step. 13. The prefetch method according to claim 12, further comprising: an iterative prefetch step of repeating data reading in the prefetch step; and a prefetch ending step of terminating the iterative prefetch step. 14. A number counting step for counting the number of times the repetitive prefetch step has been performed, and detecting that a value set in a control register matches the number of the prefetch steps counted by the number counting step. 14. The prefetch method according to claim 13, further comprising a number matching step, and a step of terminating the iterative prefetch step when a match is detected by the number matching step. 15. A data size counting step for counting the size of data held in a prefetch buffer by an iterative prefetch step, and a data size set in a control register and holding in the prefetch buffer obtained by the data size counting step. 14. A data size match detecting step for detecting that the size of the data matches the data size, and a step of terminating the iterative prefetch step when a match is detected by the data size match detecting step. Prefetch method. 16. An end address detecting step for detecting that an address generated in an address generating step of an iterative prefetch step matches an address set in a control register; and, if a match is detected in the end address detecting step, 14. The prefetch method according to claim 13, further comprising the step of terminating the iterative prefetch step. 17. The prefetch method according to claim 12, wherein the address generating step is a step of generating an address by adding a value set in a control register to a read request address of a processor to a storage device. 18. The address generating step according to claim 1, wherein the address generating step generates an address by performing an operation determined by information set in a control register on a read request address to a storage device of the processor. Prefetch method. 19. The prefetch method according to claim 14, further comprising the step of rewriting a control register by a processor. 20. The first iterative prefetch step is started by a first and a second iterative prefetch step of repeating data reading in a prefetch step, and a first read request address to a storage device of the processor. When the address match detecting step detects that the second read request address to the storage device does not match the address of the data held in the prefetch buffer in the first repetitive prefetch step, 2. The method of claim 1, further comprising terminating the first iterative prefetch step and starting the second iterative prefetch step.
2. The prefetch method according to 2. 21. The prefetch method according to claim 12, further comprising the step of invalidating the data stored in the prefetch buffer from the prefetch buffer when the data in the prefetch buffer is transmitted to the processor in the data transfer step. . 22. When the address match detecting step detects that the read request address to the storage device of the processor does not match the address of the data held in the prefetch buffer, invalidates the data held in the prefetch buffer. 13. The prefetch method according to claim 12, further comprising the step of: