JP3450227B2 - Continuous matching sampling circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to continuous collation sampling for continuously sampling an input signal a predetermined number of times and, when sampled at the same level, determining that level as the true level of the input signal. Ru <br/> relates to a circuitry.

[0002]

2. Description of the Related Art In a conventional continuous collation sampling circuit, as shown in FIG.
FF) is connected to the input of the shift register 100, the input of the first OR circuit 101 is connected to each normal output Q of the shift register 100 and the CLK (clock) terminal, and the second OR circuit 102 is connected. The inverting output QB of the shift register 100 and the CLK terminal are connected to the input, the outputs of the OR circuits 101 and 102 are connected to the inputs of the latch circuit 103 configured by the OR circuit, and the output of the latch circuit 103 is It is a continuous collation flag.

Next, the operation will be described. Input signal IN
2 becomes 1 continuously for two times, the QB outputs of the two FFs of the shift register 100 both become 0, the output of the logical sum circuit 102 becomes 1, and the latch circuit 103 is set to set the continuous collation flag. It becomes 1. When IN becomes 0 twice consecutively, the Q outputs of the two FFs both become 0, the output of the OR circuit 101 becomes 1, the latch circuit 103 is reset, and the continuous collation flag becomes 0. .

As another prior art related to the present invention,
For example, there are those described in JP-A-63-12451 and JP-A-8-16751. Discloses a transmission data protection circuit that protects data from noise and other external disturbances when performing data transmission having a relatively long cycle with respect to the clock in the system. There is disclosed a transfer material counting device for eliminating a counting error due to noise when counting is performed by using.

[0005]

The main drawback of the conventional continuous collation sampling circuit described with reference to FIG.
This means that as the number of terminals increases, the circuit becomes larger in proportion to the number. In addition, there is a drawback that the number of consecutive collations is a fixed value and cannot be changed.

The reason why such a defect occurs is that, as to the size of the circuit, a circuit for continuous collation sampling is required for each IN terminal.
This is because as the number of N terminals increases, the number of circuits for continuous collation sampling increases in proportion to the number. Also,
The reason why the number of consecutive collations becomes a fixed value is that the number of consecutive collations cannot be changed because the number of samplings is determined by the number of FFs. Also,
In the prior art disclosed in each of the above publications,
It contains the same problems as above.

The present invention has been made to solve the above problems, and an object of the present invention is to make it possible to change the number and the number of input signals that can be continuously collated and sampled without increasing the size of the circuit.

[0008]

In order to achieve the above-mentioned object, a continuous collation sampling circuit according to the present invention has an address corresponding to a plurality of input signals, which has the same number of consecutive consecutive collations as the predetermined number of consecutive collations. Storage means for holding the number of consecutive times indicating that the signal level has continued, and a flag that changes when the number of consecutive times and the predetermined number of consecutive collations coincide, and the reading and writing of the memory means by designating the address. Exclusive logic of control means for controlling, selection means for selecting one input signal corresponding to the designated address from the plurality of input signals, and exclusive logic of the selected input signal and the corresponding flag of the storage means. A logical means for taking a sum, an updating means for updating a corresponding number of consecutive times in the storage means according to a result of the exclusive OR, and a comparing means,
The comparison means uses the updated number of consecutive times and the predetermined number of times.
If it matches after comparing with the number of consecutive collation, H is output,
If there is no match, a matching circuit that outputs L and the above
The output from the coincidence circuit and the corresponding flag of the storage means
And an EXOR circuit in the comparison means for taking the exclusive OR of
If the number of consecutive times and the predetermined number of consecutive
In case of
Is to clear.

[0009]

Further, it had your <br/> to the continuous verification sampling circuits, the predetermined continuous verification number, may be continuously count and flag can be set respectively.

Further, at the time of the updating, 1 may be added to the consecutive number when the result of the exclusive OR changes.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a continuous collation sampling circuit according to a first embodiment of the present invention.

First, the present embodiment will be schematically described.
In FIG. 1, a continuous collation data holding circuit 1 including an EXOR circuit 2, an adder 3, a comparator 4 and a RAM 5 inside is
External terminals IN0 to INn to which input signals are respectively input
The output of the selector 6 for selecting one of the above is connected.
The ADDRESS output signal of the counter 7 to which the CLK terminal is input is input to the address of the RAM 5 in the continuous collation data holding circuit 1 and the selector 6. Also, the counter 7
Write timing signal of RAM 5 (hereinafter, / WRIT
(Denoted as E).

In the continuous collation data holding circuit 1, an EXOR circuit (exclusive OR circuit) 2 is used to input the input signal selected by the selector 6 and continuous count data of the RAM 5 which will be described later.
To the adder 3, and the output of the adder 3 is input to the comparator 4 for comparison with the predetermined number of consecutive collations in the RAM 5. The output of the comparator 4 is used as the data input of the RAM 5, and the continuous collation flag is obtained from the RAM 5.

With the above configuration, it is possible to carry out continuous collation sampling of the IN0 to INn terminals having the number of addresses of the RAM 5. That is, one IN is assigned to one address in the RAM 5. When a certain address in the RAM 5 is accessed, the IN terminal corresponding to that address is selected by the selector 6.

If the level of the input signal of the selected IN terminal is the same as the level at the previous sampling, the RAM
A value obtained by adding 1 to the data read from 5 (hereinafter, referred to as continuous number data) by the adder 3 passes through the comparator 4 and is written in the same address of the RAM 5. In this way, the continuous count data of the same level signal is stored in the RAM 5
Hold on. In the RAM 5, as shown in FIG. 2, the collation number setting circuit 8 sets a predetermined consecutive collation number in a bit different from the data of the same address. When the consecutive number data and the consecutive collation number match, The comparator 4 writes data as a continuous collation flag in a bit different from the consecutive count data of the same address and the consecutive collation count.

Since one IN terminal is assigned to one address of the RAM 5, it is possible to set the same number of IN terminals as the address of the RAM 5 with the same circuit configuration. R
The address of AM5 is 2 ⁿ when the address bit is ^n.
The number of IN terminals that can be continuously collated and sampled can be increased exponentially without increasing the size of the circuit.

Next, the configuration and operation of this embodiment will be described in detail. In the present embodiment, a case will be described as an example in which the maximum value of the number of consecutive collations is 127, the number of external terminals IN is 64, and the sampling interval is 1 ms. The overall configuration is as described above with reference to FIG.

Details of the continuous collation data holding circuit 1 of FIG. 1 will be described with reference to FIG. RAM5 which is the continuous count data
DATA_OUT [6: 0] (signal 9) is connected to IN [6: 0] of the adder 3 and the RAM is the number of consecutive collations.
DATA_OUT [13: 7] of 5 is COM of the comparator 4.
DAT, which is connected to P [6: 0] and is a continuous matching flag
A_OUT [14] is connected to one input of the EXOR circuit 2 and IN_FLG of the comparator 4 and is output to the outside as a continuous collation flag.

The other input of the EXOR circuit 2 is connected to the input data signal which is the output of the selector 6 of FIG.
The output of the XOR circuit 2 is connected to the EN of the adder 3. The OUT [6: 0] of the adder 3 is connected to the IN [6: 0] of the comparator 4 by the signal 10, and the OUT [6: 0] of the comparator 4 is connected.
[6: 0] is DATA_I of the RAM 5 by the signal 11.
OUT_FLG of the comparator 4 connected to N [1: 0]
Is sent to the DATA_IN [14] of the RAM 5 by the signal 12.
It is connected to the.

ADDRESS input is the ADD of RAM5
It is connected to RESS and I of the collation number setting circuit 8 is connected.
OUT of the matching circuit setting circuit 8 connected to N is RAM
5 DATA_IN [13: 7]. / WR
The ITE input is connected to / WRITE of RAM5.

Next, details of the comparator will be described with reference to FIG. The COMP [6: 0] input is connected to A of the matching circuit 13, the IN [6: 0] input is connected to B of the matching circuit 13, and the B [6: 0] of the multi-bit AND circuit 14 is connected. Has been done. The COMP of the coincidence circuit 13 is connected to A of the multi-bit AND circuit 14 and to one input of the EXOR circuit 15. The IN_FLG input is connected to the other input of the EXOR circuit 15 and
Output of R circuit 15 is connected to OUT_FLG output.

Details of the multi-bit AND circuit 14 of FIG. 4 will be described with reference to FIG. The B [6: 0] inputs are independently connected to one input terminals of a plurality of AND circuits 16, and the other inputs of all the AND circuits 16 are all connected to the A inputs via the inverter 17. . All AN
The outputs of the D circuits 16 are connected to the OUT [6: 0] outputs, respectively.

Next, details of the counter 7 shown in FIG. 1 will be described with reference to FIG. The CLK input is connected to the T clock of the toggle FF 18 and is also connected to one input of the OR circuit 19. The Q of the toggle FF 18 is connected to the other input of the OR circuit 19, and the QB output of the toggle FF 18 is
The output of the 6-bit up counter 20 is connected to the CLK of the 6-bit up counter 20, and the output is ADDRESS.
It is connected to the [5: 0] output. The output of the OR circuit 19 is connected to the / WRITE output.

Next, the operation of this embodiment will be described. First, the bit mapping of the RAM shown in FIG. 2 will be described, then the overall timing of 1 ms sampling will be described, and then the timing and circuit operation for the sampling operation of one IN will be described. The continuous verification sampling operation when the number of times is four will be described in order.

Bit mapping of the RAM 5 of FIG. 2 is shown in FIG.
2 shows. The data in the RAM 5 has a 16-bit structure and b [6: 0] is continuous count data, which indicates how many times the input signal in FIG. 2 has the same level continuously. b [14] is an output of the continuous matching sampling circuit of the present embodiment as a continuous matching flag, which is a signal after noise of the input signal in FIG. 2 is removed. b [13:
7] is the number of consecutive collations, and the predetermined value shown here and b
When the value of [6: 0] matches, the continuous collation flag of b [14] is changed.

That is, the number of times of continuous collation means that when the input signal shown in FIG. 2 is continuously input at the same level or more at this value, the level is determined to be a true level, and is less than or equal to this value. In the case, it is judged as noise.

Next, the overall timing of 1 ms sampling will be described. The operation of the counter 7 of FIG. 1 will be described with reference to the circuit of FIG. 7 and the timing chart of FIG.

128K is applied to the CLK input of the counter 7.
7 Hz signal is input, and the 64 KHz signal divided by 2 by the toggle FF 18 of FIG.
, The ADDRESS [5: 0] output to which the output of the 6-bit up counter 20 is connected changes every 15.6 μs (= 64 KHz cycle). There are 64 variations from 0 to 63.

Further, the counter 7 outputs the / WRITE signal shown in the timing chart of FIG.
As shown in FIG. 1, the ADDRESS [5:
0] output is connected to a selector 6 that selects IN0 to INn (in the present embodiment, the value of n is 63). In this selector 6, there is only one IN corresponding to ADDRESS [5: 0]. To be selected. For example, ADDRESS
If [5: 0] = 0, IN0 is selected.

ADDRESS [5: 0] is 15.6 μs
Since it changes from 0, 1 and 2 every time, IN0, IN1 and IN2 are selected by the selector 6 accordingly, and
Is connected as an input signal to the continuous collation data holding circuit 1. The ADDRESS [5: 0] output of the counter 7 is the ADDRESS of the RAM 5 in the continuous collation data holding circuit 1.
Since it is also connected to, ADDRESS as well as IN
As [5: 0] changes to 0, 1, 2, the address of the RAM 5 to be accessed also changes in order of 0, 1, 2.

FIG. 9 shows the entire waveform of 1 ms sampling. ADDRESS [5: 0] is one ADDRESS
Since the value of 0 to 63 is repeated at the time of 15.6 μs, the time until the same ADDRESS value appears next is 15.6 μs × 64 = 1 ms. Therefore, ADDR
By measuring the level of the IN selected by the selector 6 for each ESS value, 1 ms of all 64 INs
Can be sampled.

Next, the timing and circuit operation of the sampling operation of one input signal IN will be described. Figure 10
Shows a timing chart of the operation for one ADDRESS. This FIG. 10 shows the case where the input signal of FIG. 2 is at the same level as the previous sampling. That is, that is, when the continuous count data is incremented.

When ADDRESS changes to n, RAM
The value m, which is the continuous count data from 5, is DATA_OUT
It is read from [6: 0].

This m value passes through the adder 3 and the comparator 4 in FIG. 2 and is at the same level as the input signal when it was sampled last time as described above. Therefore, 1 is added to m + 1, and DATA_IN [6 of RAM 5 is used. : 0]. Since the / WRITE signal from the counter 7 is input to the RAM 5 as a write timing signal, the m + 1 value at point A is written to b [6: 0] as continuous count data. Along with that, DATA_OUT [6: 0]
Also changes to m + 1, and DATA_IN [6: 0] also changes to m + 2 at the same time.

Next, the continuous collation sampling operation when the number of consecutive collations is set to 4 will be described, and FIG.
The operation of adding the continuous count data according to the level of the input signal and the manner in which the continuous circuit data matches the continuous check count and the continuous check flag changes will be described with reference to FIGS. 11 and 2 to 6. FIG. 11 shows the level of each signal line at point A in the timing chart of FIG. 10 over time. The elapsed time is serially numbered from 1 to 21 on the horizontal axis of the table, and one of the numbers on the horizontal axis indicates one address. The horizontal axis shows the same RAM address, so 1 and 2
Has a real time interval of 1 ms.

At 3 of the passage of time in FIG. 11, the input signal becomes H.
In the case of, the operation of counting up the continuous count data will be described. Since the input signal is H and the continuous matching flag is L, E
The EN of the adder 3, which is the output of the XOR circuit 2, becomes H.
When the EN of the adder 3 becomes H, the signal 10 of FIG. 2 which is the output of the adder 3 is added to the signal 9 which is the input of the adder 3 from the truth table of the adder 3 of FIG. Add h to the last digit).

The signal 10 is input to IN [6: 0] of the comparator 4. In the comparator 4, as shown in FIG. 4, IN [6:
2h of the signal 10 is input to the [0] input, and COMP [6:
0] input to DATA_OUT [13: 7] of FIG.
(Consecutive collation count) 4h is input, and the continuous collation flag L of FIG. 11 is input to the IN_FLG input.
The operation of the matching circuit 13 incorporated in the comparator 4 outputs L when the inputs A and B do not match as shown in FIG. 5, so that COMP [6: 0] and IN [ 6: 0]
Does not match, L is output from the comparator 4.

The operation of the multi-bit AND circuit 14 in the next stage of the coincidence circuit 13 is as follows when the A input is L as shown in FIG.
The same value as the B [6: 0] input is output from OUT [6: 0], and when the A input is H, OUT [6: 0] is all L. Since COMP of the matching circuit 13 is now L, the multi-bit AND circuit 14 has OUT [6: 0] = B [6: 0], and the OUT [6: 0] output of the comparator 4 causes the comparator 4 to output.
The value of the IN [6: 0] input of is output as it is.

Since COMP = L and IN_FLG = L of the coincidence circuit 13, L is output from the OUT_FLG output of the comparator 4. Therefore, the signal 11 in FIG. 2 has a value of 2h as shown in FIG.
It is written in b [6: 0] of AM5 and the continuous count data is counted up. Since the value L of the signal 12 of FIG. 2 is written in the continuous collation flag, there is no change.

Next, the operation when the input signal level is different from the previous one at 5 of the passage of time in FIG. 11 will be described. Since the input signal is L and the continuous collation flag is L, the EN of the adder 3, which is the output of the EXOR circuit 2, becomes L. Adder 3 EN
Is L, adder 3 from the truth table of adder 3 in FIG.
The signal 10 in FIG. 2 which is the output of the signal is 0h. The signal 10 is input to IN [6: 0] of the comparator 4.

In the comparator 4, as shown in FIG.
0h of signal 10 is input to the [6: 0] input, and COMP
For the [6: 0] input, DATA_OUT [13:
7] (the number of consecutive collations) is input, and IN_FLG
As the input, the continuous collation flag L in FIG. 11 is input. The operation of the coincidence circuit 13 built in the comparator 4 is shown in FIG.
As shown in, when the inputs A and B do not match, L is output, so now COMP [6: 0] and IN [6: 0]
Does not match, L is output from the comparator 4.

Since the operation of the multi-bit AND circuit 14 in the next stage of the matching circuit 13 is as described above, the CO of the matching circuit 13 is changed.
Since MP = L, the multi-bit AND circuit 14 outputs OUT [6:
0] = B [6: 0], and OUT [6: of the comparator 4
From the [0] output, the value of the IN [6: 0] input of the comparator 4 is output as it is. Further, COMP = of the matching circuit 13
Since L and IN_FLG = L, OUT_ of the comparator 4
L is output from the FLG output.

Therefore, the signal 11 in FIG. 2 has a value of 0h as shown in FIG. 11, and the value is b in the RAM 5.
It is written in [6: 0] and the continuous count data becomes 0h. Thus, when the input signal level is different from the previous one, the continuous count data is cleared. Since the value L of the signal 12 of FIG. 2 is written in the continuous collation flag, there is no change.

Next, at the passage of time 9 in FIG. 11, the continuous count data and the continuous matching count when the input signal is H (see FIG. 11).
DATA_OUT [13: 7]) of the above will be described.

Since the input signal is H and the continuous collation flag is L, the EN of the adder 3 which is the output of the EXOR circuit 2 becomes H. When the EN of the adder 3 becomes H, the signal 10 of FIG. 2 which is the output of the adder 3 from the truth table of the adder 3 of FIG.
One is added to the signal 9 which is the input of the adder 3 to obtain 4h.
The signal 10 is input to IN [6: 0] of the comparator 4.

In the comparator, as shown in FIG. 4, IN [6:
4h of the signal 10 is input to the [0] input, and COMP [6:
0] input to DATA_OUT [13: 7] of FIG.
4h of (the number of consecutive collations) is input, and the continuous collation flag L of FIG. 11 is input to the IN_FLG input.
Since COMP [6: 0] and IN [6: 0] match now, H is output from COMP of the matching circuit 13.

Since COMP of the coincidence circuit 13 is H, the multi-bit AND circuit 14 has OUT [6: 0] = 0h.
In addition, COMP = H of the matching circuit 13 and IN_FLG
= L, H is output from the OUT_FLG output of the comparator 4. Therefore, the signal 11 in FIG. 2 has a value of 0h as shown in FIG. 11, and the value is b in the RAM 5.
It is written at [6: 0], the continuous count data becomes 0h, and the value H of the signal 12 in FIG. 2 is written in the continuous collation flag. In this way, when the consecutive count data and the consecutive collation count match, the consecutive collation flag changes and the consecutive count data is cleared.

Next, the operation of counting up the continuous count data when the input signal is L at the elapse of time 10 in FIG. 11 will be described. Since the input signal is L and the continuous collation flag is H, the EN of the adder 3 which is the output of the EXOR circuit 2 is H.
become. When EN of adder 3 becomes H, adder 3 of FIG.
From the truth table of the above, the signal 10 of FIG.
The signal 10 is input to IN [6: 0] of the comparator 4.

In the comparator 4, as shown in FIG.
1h of the signal 10 is input to the [6: 0] input, and COMP
For the [6: 0] input, DATA_OUT [13:
7] (the number of consecutive collations) is input, and IN_FLG
As the input, the continuous collation flag H of FIG. 11 is input. Since the operation of the multi-bit AND circuit 14 at the next stage of the matching circuit 13 is as described above, COMP = L of the matching circuit 13
For more bits AND, OUT [6: 0] = B [6: 0]
Therefore, the value of the IN [6: 0] input of the comparator 4 is directly output from the OUT [6: 0] output of the comparator 4.

Further, since COMP = L and IN_FLG = H of the coincidence circuit 13, H is output from the OUT_FLG output of the comparator 4. Therefore, the signal 11 in FIG.
As shown in 1, the value becomes 1h, and that value is RA.
It is written in b [6: 0] of M5, and the continuous count data is counted up. The continuous verification flag includes the signal 12 of FIG.
Since the value H of is written, there is no change.

Next, the operation in the case where the continuous collation flag is H and the input signal level is different from the previous time at 13 of the passage of time in FIG. 11 will be described. Since the input signal is H and the continuous collation flag is H, the E of the adder 3 which is the output of the EXOR circuit 2
N becomes L. When the EN of the adder 3 becomes L, the signal 10 of FIG. 2 which is the output of the adder 3 is 0h from the truth table of FIG.
Becomes The signal 10 is input to IN [6: 0] of the comparator 4.

In the comparator 4, as shown in FIG.
0h of signal 10 is input to the [6: 0] input, and COMP
For the [6: 0] input, DATA_OUT [13:
7] (the number of consecutive collations) is input, and IN_FLG
As the input, the continuous collation flag H of FIG. 11 is input.

The operation of the matching circuit 13 built in the comparator 4 outputs L when the inputs A and B do not match as shown in FIG. 5, so that COMP [6: 0] is now set. IN
Since [6: 0] does not match, L is output from the comparator 4. Since the operation of the multi-bit AND circuit 14 in the next stage of the matching circuit 13 is as described above, the CO
Since MP = L, the multi-bit AND circuit 14 outputs OUT [6:
0] = B [6: 0], and OUT [6: of the comparator 4
From the [0] output, the value of the IN [6: 0] input of the comparator 4 is output as it is.

Further, COMP = L and I of the coincidence circuit 13
Since N_FLG = H, H is output from the OUT_FLG output of the comparator 4. Therefore, the signal 11 in FIG.
As shown in, the value becomes 0h, and the value is RAM.
It is written in b [6: 0] of 5 and the continuous count data becomes 0h. In this way, when the input signal level is different from the previous one, the continuous count data is cleared. Since the value H of the signal 12 in FIG. 2 is written in the continuous collation flag, there is no change.

Next, at the lapse of time 17 in FIG. 11, when the continuous collation flag is H and the input signal is L, the continuous count data and the continuous collation count (DATA_OUT [1 in FIG. 11 are obtained.
3: 7]) are matched with each other.

Since the input signal is L and the continuous collation flag is H, the EN of the adder 3 which is the output of the EXOR circuit 2 becomes H. When EN of the adder 3 becomes H, the signal 10 of FIG. 2 which is the output of the adder 3 is added to the signal 9 which is the input of the adder 1 from the truth table of FIG. The signal 10 is input to IN [6: 0] of the comparator 4.

In the comparator 4, as shown in FIG.
4h of signal 10 is input to the [6: 0] input, and COMP
For the [6: 0] input, DATA_OUT [13:
7] (the number of consecutive collations) is input, and IN_FLG
As the input, the continuous collation flag H of FIG. 11 is input. Since COMP [6: 0] and IN [6: 0] match now, H is output from COMP of the matching circuit 13. Since COMP of the coincidence circuit 13 is H, the multi-bit AND circuit 14OUT [6: 0] = 0h.

Further, since COMP = H and IN_FLG = H of the coincidence circuit 13, L is output from the OUT_FLG output of the comparator 4. Therefore, the signal 11 in FIG.
As shown in 1, the value becomes 0h, and that value is RA.
It is written in b [6: 0] of M5 and the continuous count data is 0.
h, and the and the continuous comparison flag value L of the signal 12 in FIG. 2 is written can write. In this way, when the consecutive count data and the consecutive collation count match, the consecutive collation flag changes and the consecutive count data is cleared.

As described above, looking at FIG. 11,
It can be seen that when the same level is continuously input to the input signal four times, the continuous collation flag output changes to the same level as the input signal level. Further, it can be seen that the continuous collation flag does not change in the case where the number of consecutive same levels of the input signal is three or less.

In FIG. 11, the part marked with a star is a part for explaining the above-mentioned operation, and the operation of each part is summarized below. Elapsed time 3 columns: When the input signal is at the same level as the previous time and continuous count data is added. Condition: Continuous collation flag = L, input signal = H elapsed time 5 columns .....
When continuous count data is cleared. Condition: continuous collation flag = L, input signal = L elapsed time 9 columns ... When the continuous count data matches the continuous collation count and the continuous collation flag changes to H next time. Condition: Input signal = H time has passed 10 columns ........ The input signal is at the same level as the previous time,
When continuous count data is added. Condition: Continuous collation flag = H, input signal = L Elapsed time 13 columns ... When the input signal is at a different level from the previous time and the continuous count data is cleared. Condition: continuous collation flag = H, input signal = H elapsed time 17 columns ... When the continuous count data matches the continuous collation count and the continuous collation flag changes to L next time. Condition: Input signal = L

The matching circuit setting circuit 8 shown in FIG.
5 is a circuit that determines the number of consecutive collations for each address, and when ADDRESS is input, the ADDR
This is a circuit for inputting the number of consecutive collations corresponding to ESS to the RAM 5.

In the description of this embodiment, the case where the number of continuous collations is 4 has been described. However, as shown in the bit mapping of the RAM 5 in FIG. Up to 127 times
It can be set up to (= 2 ⁷ -1) times. Also, R
By changing the configuration of bit mapping of AM5,
The bit with the smaller number of consecutive collation counts and consecutive count data is n
In this case, the number of continuous collations can be set up to 2 ⁿ -1 times, and the number of INs can be increased up to 2 ⁿ times.

Next, a second embodiment of the present invention will be described. In the present embodiment, as shown in FIG. 13, as the RAM 5 in the continuous collation data holding circuit 1, a 2-port type RA is used.
Use M, and use that port for continuous matching count
By connecting the second port to the CPU 21 via the CPU data bus, the CPU 21 can freely set the number of times of continuous collation and the like.

According to the above configuration, for example, the number of continuous collations can be arbitrarily changed by the CPU 21 by software. In a system using the continuous collation sampling circuit according to the present embodiment, for example, when the noise of the entire system increases, the number of consecutive collations is increased, and when the noise is reduced, the number of collations is reduced.
It is possible to set the number of continuous collations that is most suitable for the operating condition of the system for each IN terminal.

Further, even if the number of times of continuous collation is changed due to the change of the system specifications, it can be dealt with without changing the circuit, which is effective in reducing the cost and the design period in designing the system.

Further, not only the number of times of continuous matching but also the value of continuous matching flag and the number of times of continuous matching can be set by the CPU 21 at any timing. By doing so, the continuous collation flag can be reset and the start value of the continuous count data can be changed.

Further, in the above publication, the output level is transitioned only when the sampling value of the input transmission data has the same value n times consecutively. Therefore, the number of consecutive times when the output level changes is the same for all transmissions. The data is fixed as n times. On the other hand, in the present invention, the number of consecutive output levels (continuous collation flag) is determined by the bit mapping of the RAM 5 in FIG.
Each terminal) can be set.

In the above publication, the CPU is basically used.
It is realized by software control according to, and has a basic configuration different from that of the present invention. In particular, there is no configuration in which the RAM 5 stores the predetermined number of consecutive collations, the number of consecutive collations, and the consecutive collation flag for each address.

When the first and second embodiments are constructed by a computer system, a memory such as a ROM used in this computer system constitutes a storage medium according to the present invention. This storage medium stores a program that executes the procedure for performing the operation described in each embodiment.

As such a storage medium, a semiconductor storage device, an optical disk, a magneto-optical disk, a magnetic recording medium or the like is used.

[0072]

As described above, according to the present invention,
Since one input signal is assigned to one address of the RAM, continuous verification sampling can be performed for the same number of input signals as the addresses of the RAM with the same circuit configuration.

Since the address of the RAM increases by 2 ^{n when the} address bit is n, the number of input signals that can be continuously collated and sampled can be exponentially increased without increasing the size of the circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a continuous matching sampling circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a continuous collation data holding circuit.

FIG. 3 is a configuration diagram showing a truth table of an adder.

FIG. 4 is a block diagram showing a configuration of a comparator.

FIG. 5 is a configuration diagram showing a truth table of a matching circuit.

FIG. 6 is a configuration diagram of a multi-bit AND circuit.

FIG. 7 is a block diagram showing a configuration of a counter.

FIG. 8 is a timing chart showing the operation of the counter.

FIG. 9 is an overall waveform diagram in the case of 1 ms sampling.

FIG. 10 is a timing chart showing the operation of the RAM for one address.

11 is a timing chart showing level changes of each signal of FIG. 2 and the COMP output of FIG.

FIG. 12 is a configuration diagram showing a bit mapping of a RAM.

FIG. 13 is a block diagram showing a continuous matching sampling circuit according to a second embodiment of the present invention.

FIG. 14 is a block diagram showing a conventional continuous matching sampling circuit.

[Explanation of symbols]

1 Continuous collation data holding circuit 2 EXOR circuit 3 adders 4 comparator 5 RAM 6 selector 7 counter 8 Collation count setting circuit 9, 10, 11, 12 signals 13 Matching circuit 14 Multi-bit AND circuit 15 EXOR circuit 18 Toggle FF 19 OR circuit 20 6-bit up counter 21 CPU

Front page continuation (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04L 25/08 G06F 11/34 H03M 1/12

Claims (5)

(57) [Claims] 1. An address corresponding to a plurality of input signals,
Storage means for holding a predetermined number of consecutive collations, a number of consecutive times indicating how many times the same signal level has continued, and a flag that changes when the number of consecutive times and the predetermined number of consecutive collations match, Control means for designating the address to control reading / writing of the storage means; selection means for selecting one input signal corresponding to the designated address from the plurality of input signals; and the selected input signal And a corresponding flag of the storage means, a logical means for obtaining an exclusive OR of the storage means, an updating means for updating the corresponding continuous number of the storage means according to the result of the exclusive OR, and a comparing means. , The comparing means compares the updated number of consecutive times and the predetermined number of consecutive collations.
If they are compared and match, H is output and they do not match
In this case, a matching circuit that outputs L, an output from the matching circuit, and a corresponding flag of the storage means.
And an EXOR circuit in the comparison means that takes an exclusive OR with
When the number of consecutive times and the predetermined number of consecutive matching times match,
In this case, change the flag and click the
Sequential matching sampling circuit characterized by rear . 2. The continuous collation sampling circuit according to claim 1, further comprising setting means for setting the predetermined number of consecutive collations. 3. The continuous collation sampling circuit according to claim 1, further comprising setting means for setting the number of continuous times. 4. The continuous matching sampling circuit according to claim 1, further comprising setting means for setting the flag. 5. The continuous collation sampling circuit according to claim 1, wherein the updating means adds 1 to the continuous number when the result of the exclusive OR changes.