JPS63158637A - Memory tracing system - Google Patents

Abstract

PURPOSE:To simplify the constitution of a circuit, and to prevent the expansion of the scale of the circuit by using the same address signal as that of a main storing memory for the address signal of a trace condition memory. CONSTITUTION:Because an address bus 19 from a micro-processor 11 is connected to the main storing memory 12 and to the trace condition memory 21, when an address appears in the address bus 19, the main storing memory 12 and the condition memory 21 are simultaneously selected, and from the trace condition memory 21, a trace condition data, corresponding to the said address, is outputted. The outputted trace condition data is inputted to a condition comparison circuit 22, and is compared with the state of the address bus 19, a data bus 18 and a control line 20, and when a condition coincidence is detected, a write-in instruction is given to a memory write-in control circuit 16, and a contents to be traced is written in a trace storing memory 17.

Description

[Detailed Description of the Invention] [Summary] It has a trace condition memory that stores trace conditions at the same address as the main memory accessed by the microprocessor, and matches each signal condition with the trace condition when accessed by the microprocessor. Memory tracing is performed by storing each signal condition at that time in a trace storage memory upon detection.

C. Industrial Application Field] The present invention relates to a memory tracing method, and in particular, to a memory tracing method that reduces the circuit size by providing a memory for storing trace conditions.In an electronic computer using a microprocessor, , Debugging of microprocessor software can often be diagnosed primarily by observing changes in memory.

In this case, a memory tracing method for observing changes in the memory is required to have a small circuit scale and to be able to easily change and observe trace conditions in word units.

[Conventional technology]

FIG. 4 shows a conventional memory tracing method. In the figure, 11 is a microprocessor, 12 is a main memory, 131 to 13n are trace condition temporary storage circuits, 14 + to 14n are condition comparison circuits, 15 is an OR circuit, 16 is a memory write control circuit, and 17 is a trace accumulation circuit. Memory, 18 data bus, 19 address bus, 20
is the control line.

Further, FIG. 5 shows the operation timing of each part in the configuration of FIG. 4.

In FIG. 4, microprocessor 11 reads and writes data to main memory 12 via data bus 18 by addressing via address bus 19 and by providing control signals via control line 20. , to perform the desired operation.

When memory tracing is performed using the microprocessor 11 and the main memory 12 as parts under test, the address conditions, data conditions, and control signal conditions for each case are stored in the trace condition temporary storage circuits 131 to 13n. . The condition comparison circuits 141 to 14n compare the contents of the corresponding trace condition temporary storage circuits 13 to 13n and the address bus 19. Data bus18. It compares the status with the control line (source) and generates a match detection signal when the conditions match.

As a result, a memory write command is issued to the memory write control circuit 16 via the OR circuit 15, and in response, the memory write control circuit 16 instructs the trace storage memory 17 to use the address bus 19. Control is performed so that the state of the data bus 18° control line 20 is stored. In this way, the memory trace of the microprocessor 11 at that time is performed, and the trace contents are sequentially stored in the trace storage memory 17.

In FIG. 5, when address #1, which is a signal on the address bus 19, and trace condition data #1, which is the output of a certain trace condition temporary storage circuit, match, a match detection signal is generated from the corresponding condition comparison circuit. However, match detection depends not only on the address bus conditions;
This can also be done for other conditions.

[Problem that the invention seeks to solve]

In the conventional memory tracing method shown in FIG. 4, when tracing multiple addresses, multiple sets of the trace condition temporary storage circuit and condition comparison circuit shown in FIG. 4 are required. do.

Therefore, when tracing a large number of addresses, there is a problem in that the circuit scale inevitably increases.

Means for Solving Problem C) The present invention attempts to solve the problems of the prior art, and as shown in FIG. In a device that operates by accessing the memory 12, the trace condition memory 21
, a condition comparison circuit n, and a trace M product memory 17.

The trace condition memory 21 stores trace conditions that define each signal state exchanged between the microprocessor 11 and the main memory 12 for each address.
is stored at the same address as , and output in synchronization with the address designation of the main memory 12.

The condition comparison circuit 22 compares each signal state exchanged between the microprocessor 11 and the main memory 12 with the trace condition output of the trace condition memory 21, and when they match, generates a memory write command.

The trace storage memory 17 sequentially stores each signal state exchanged between the microprocessor 11 and the main memory 12 in response to a memory write command.

[For production]

In the memory trace method of the present invention, the same address signal as that of the main memory is used as the address signal of the trace condition memory that stores trace conditions, so that the microprocessor can synchronize with the selection of any main memory. , a trace condition memory corresponding to the selected main memory is selected, and each signal state exchanged between the microprocessor and the main memory is compared with the trace condition read from the trace condition memory. Since each signal state exchanged with the main memory according to condition matching is sequentially stored in the trace storage memory, each word of the main memory can have a trace condition and can be traced.

〔Example〕

FIG. 2 shows one embodiment of the present invention.
The same parts as in the figure are indicated by the same numbers, and their functions and operations are the same as in the case of FIG.

21 is a trace condition memory, and 22 is a condition comparison circuit.

Further, FIG. 3 shows the operation timing of each part in the configuration of FIG. 2.

In FIG. 2, the address bus 19 from the microprocessor 11 is connected to the main memory 12 and the trace condition memory 21, and when an address appears on the address bus 19, the address bus 19 from the microprocessor 11 is connected to the main memory I2 and the trace condition memory 21.
is selected at the same time, and trace condition data corresponding to that address is output from the trace condition memory 21 as shown in FIG.

The output trace condition data is input to the condition comparison circuit 22, and the address bus 19. The states of the data bus 18 and control line 20 are compared. When condition matching is detected in the condition comparison circuit 22, the condition comparison circuit n issues a write command to the memory write control circuit 16.

In response, the memory write control circuit 16 writes the trace storage memory 17 to the current address bus 19.
Data bus18. Control is performed so that the state of the control line 20 is stored. In this way, the memory trace of the current microprocessor 1 is performed, and the trace contents are sequentially stored in the trace storage memory 17.

In FIG. 3, when address #1, which is a signal on address bus 19, and trace condition data #l, which is an output from trace condition memory 21, match, a match detection signal is generated from condition comparison circuit 22, and This indicates that the current microprocessor state is written to the trace storage memory 17. In this case, matching detection can be performed not only for address bus conditions but also for other conditions, as in the conventional method.

〔Effect of the invention〕

As explained above, according to the memory tracing method of the present invention, memory tracing for multiple addresses is easily performed by having the same amount of memory as the main memory as the trace condition memory, which simplifies the circuit configuration. It is possible to prevent an increase in circuit scale. In this case, addresses can be used in units of one word at most, and trace conditions can be arbitrarily changed in units of words.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the principle configuration of the present invention, Fig. 2 is a diagram showing an embodiment of the invention, Fig. 3 is a diagram showing the operation timing of each part in the configuration of Fig. 2, and Fig. 4 is a diagram showing the operation timing of each part in the configuration of Fig. 2. FIG. 5 is a diagram showing the conventional memory trace method, and is a diagram showing the operation timing of each part in the configuration of FIG. 4. 11-Microprocessor 12-Main memory 131-13n--Trace condition temporary storage circuit 14, -
14n...-condition comparison circuit 15...-OR circuit 16-memory write control circuit 17-trace accumulation memory I8-data path 19...address bus 20-control line 21-) race condition memory 22-m-condition comparison circuit

Claims (1)

[Claims] In a device in which a microprocessor (11) accesses a main memory (12) to operate, each signal state exchanged between the microprocessor (11) and the main memory (12) is A trace condition memory (21) that stores trace conditions defined for each address at the same address as the main memory (12) and outputs them in synchronization with address designation of the main memory (12), and a microprocessor (11). a condition comparison circuit (22) that compares each signal state exchanged between the main memory (12) and the trace condition output of the trace condition memory (21) and generates a memory write command when they match; In response to the memory write command, the microprocessor (1
1) and a main memory (12).