JPH02159641A - Bit pattern trace circuit - Google Patents

Abstract

PURPOSE:To remarkably reduce a storage capacity required for a RAM by selecting only a desired bit pattern and storing a bit pattern trace circuit in the RAM. CONSTITUTION:The bit pattern trace circuit is provided with a latch circuit 1, a collating circuit 2, a RAM 3 and an AND gate 4, and the bit patter 101 of a measuring object is inputted to both the collating circuit 2 and the RAM 3. On the other hand, a desired bit pattern 102 is inputted to the latch circuit 1 and latched, and this latched desired bit pattern is inputted to the collating circuit 2, and compared and collated with the bit pattern 101. A timing coincidence output 108 by which both the patterns coincide with each other is outputted from the collating circuit 2, and inputted to the AND gate 4. Subsequently, the output of the AND gate 4 for taking AND with a synchronous pulse is inputted as a write signal and only a desired bit pattern is written in the RAM 3. In such a manner, the data quantum stored in the RAM 3 is decreased, and the storage capacity required for the RAM 3 can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bit pattern tracing circuit, and more particularly to a bit pattern tracing circuit that improves the method of storing bit patterns in an RAI 4.

[Conventional technology]

Conventionally, in this kind of bit pattern tracing circuit, when storing a bit pattern to be measured in a predetermined RAi4, the bit pattern to be measured and a synchronization pulse synchronized with this bit pattern are simultaneously transmitted to the R
In this case, the bit pattern is input to the AM and stored, and in this case, the entire bit pattern is input to the R, regardless of whether it is necessary or not.
Generally, it is stored in AM.

[Problem to be solved by the invention]

In the conventional bit pattern tracing circuit described above, the bit pattern to be measured is written and stored in the RAIIg together with a synchronization pulse synchronized with this bit pattern, regardless of whether it is necessary or not.

Therefore, the amount of data stored in the RAM increases,
This has the disadvantage of significantly increasing the storage capacity required for the RA14.

[Means to solve the problem]

The bit pattern trace circuit of the present invention includes a latch circuit that latches a desired bit pattern, a verification circuit that compares and verifies the output of the latch circuit and a bit pattern to be measured, and a timing matching circuit that outputs the output from the verification circuit. An AND gate that performs a logical product of the output and a synchronization pulse synchronized with the bit pattern to be measured, and a RAM that inputs the output of the AND gate as a write signal and writes only the desired bit pattern. be done.

〔Example〕

Next, four aspects of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention. As shown in FIG. 1, this embodiment includes a latch circuit 1, a verification circuit 2, a RAM 43, and an AND gate 4.

Moreover, FIGS. 2(a), (b), (C), and (d) are main operation waveform diagrams in this embodiment. A synchronization signal 103 synchronized with , a coincidence timing output 108 outputted from the collation circuit 2 , and a write signal 109 outputted from the AND gate 4 .

In FIG. 1, the bit pattern 101 to be measured is:
It is input to both the verification circuit 2 and the RAM 3. On the other hand, the desired bit pattern 102 is input to the latch circuit 1 and latched. This latched desired bit pattern 104 is input to the verification circuit 2 and is compared and verified with the bit pattern 101 described above. In this verification result, a timing match output 108 in which both patterns match is output from the verification circuit 2 and input to the AND gate 4.

In the AND gate 4, the synchronization signal 103 synchronized with the bit pattern 101 to be measured is ANDed with the timing coincidence output lO8 inputted from the matching circuit 2, and the output is sent to the RAM 3 as a write signal 109. Sent. The input/output relationship in the AND gate 4 is the second
This is as shown in the operational waveform diagrams in Figures (b), (C), and (d). In the timing coincidence output 108 shown in FIG. 2(C), an H level state indicates a matching state, and an L level state indicates a mismatch state.

In the RA 143, the bit pattern 101 to be measured is stored in the RAIll 3 under the control of the write signal 109 output from the AND gate 4, but the write signal 109 is controlled by the write signal 109 output from the AND gate 4.
8, the bit pattern stored in RAM3 is the bit pattern 1 to be measured.
The desired bit pattern is limited to 01. That is, the bit pattern 101 to be measured is stored in the RAM 3.
Only the desired bit pattern is stored, and other extra bit patterns are not stored.

〔Effect of the invention〕

As described above in detail, the present invention has a bit pattern trace circuit configured to select only a desired bit pattern and store it in the RAM.
This has the effect of significantly reducing the storage capacity required.

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2(a)
, (b), (c) and (d) are main operation waveform diagrams in this embodiment.

In the figure, ■...--Latch circuit, 2...
・Verification circuit, 3...--RAM, 4...--
AND gate.

Claims (1)

[Claims] A latch circuit that latches only the desired bit pattern,
a verification circuit that compares and matches the output of the latch circuit with the bit pattern to be measured; and an AND gate that performs a logical product of the timing match output output from the verification circuit and a synchronization pulse synchronized with the bit pattern to be measured. and,
A bit pattern trace circuit comprising: a RAM that inputs the output of the AND gate as a write signal and writes only the desired bit pattern.