JPH04326134A - Tracing device - Google Patents

Abstract

PURPOSE:To store a history whose width is 2 times by connecting >=2 trace memories in the width direction and successively recording respectively independent trace data. CONSTITUTION:When a trace write control signal 8 is activated, the clock of a trace address register 3 begins to be inputted and the output of one adder 4 is inputted, clock by clock. When an address is <=K at this time, the trace data input 1 is written in the 1st trace memory 1. When the value of a trace address register 3 reaches K+1, a trace memory write permission clock 7 begins to be inputted to the 2nd trace memory 2. At the same time, it is not inputted to the 1st trace memory 1. Further, a chip selection input is supplied to the 2nd trace memory 2 and not inputted to the 1st trace memory 1. The output of a multiplexer 6 is the trace data input 1, so the trace data input 1 is recorded in the 2nd trace memory 2 successively and continuously.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tracing device for recording processing history inside a data processing device.

0002

2 and 3 are examples of circuit diagrams of conventional trace devices, and 1 and 2 indicate first and second trace memories,
3 is a trace address register that holds write addresses to the first and second trace memories 1 and 2, 4 is an adder for updating the trace address by 1, 7 is a trace memory write enable clock input, and 8 is a trace memory write enable clock input. 1 and 2 are trace write control signals that control writing to the trace memories 1 and 2, 5 is an AND gate that controls the clock input of the trace address register 3 by the trace write control signal 8, and 10 and 11 are trace memory write enable ( WriteEnable) AND gate whose clock input 7 is controlled by a trace write control signal 8;
16 is an INVERTER gate that inverts the most significant bit of the trace address register 3; In the example of FIG. 2, the first and second trace memories 1 and 2 are connected in the depth direction to record trace data input 1. Further, in the example of FIG. 3, the first and second trace memories 1 and 2 are connected in the width direction to record trace data inputs 1 and 2.

Next, the operation of one example of a conventional tracing device will be explained with reference to FIG. If the content of the trace address register 3 is N at time t0, its output is the first and second
At the same time, it is input to the 1 adder 4, and its output (N+1) is input to the trace address register 3. If the trace write control signal 8 is not yet activated at this point, the clock input of the trace address register 3 will be the AND gate 5.
Since the write permission inputs of the first and second trace memories 1 and 2 are prohibited by AND gates 10 and 11, respectively, updating of the trace address register and writing of trace data are not performed. Thereafter, when the trace write control signal 8 is activated, the clock of the trace address register 3 is inputted via the AND gate 5, so the output (N+
1) is set. At this time, if the most significant bit of the trace address register 3 is 0, the trace memory write enable input clock is supplied to the first trace memory 1 through the AND gate 10, and is supplied to the chip select (Chip Select) through the INVERTER gate 16.
t) Since the input is supplied to the first trace memory 1, trace data input 1 is written to address N. after that,
While updating the trace address register 3 as N+2, N+3, etc., the trace data input 1 in each cycle is
The data is written to trace memory 1 of . Eventually, when the most significant bit of trace address register 3 becomes 1, AND
Gate 10 and INVERTER gate 16 are closed, AND gate 11 is opened instead, and the trace data input is written to the second trace memory 2. When the trace write control signal 8 is inactivated, the clock input becomes AN
At the D gate 5, the write permission inputs of the first and second trace memories 1 and 2 are inhibited at the AND gates 10 and 11, respectively, so updating of the trace address register and writing of trace data are stopped.

0004

[Problems to be Solved by the Invention] As described above, the conventional trace device is configured to record trace data of a fixed width for a fixed maximum number of clocks, that is, for the depth of the trace memory. Therefore, there is a problem that it is not possible to trace-record trace data that is at least twice the width, and a problem that it is not possible to trace-record a part of the trace data for at least twice the number of clocks. There was a point.

The present invention has been made in order to solve the above-mentioned problems, and it is possible to obtain a tracing device that can record trace data of at least twice the width, and at the same time, it is possible to It is an object of the present invention to provide a tracing device capable of recording traces for at least twice the number of clocks.

[0006]

[Means for Solving the Problems] A trace device according to the present invention is capable of controlling at least two or more trace memories by providing means for simultaneously controlling write permission clocks for individual trace memories and means for independently inputting trace data. It is possible to record trace data of at least twice the width by connecting them in the width direction, and means that can independently control the write permission clock for each trace memory, and the same trace data can be stored in each trace memory. By providing input means, at least two or more trace memories are connected in the depth direction and recorded sequentially, making it possible to record a history of at least twice as long.

[0007]

[Operation] The tracing device in this invention has at least two
By connecting two or more trace memories in the width direction and continuously recording independent trace data, a history of at least twice the width is recorded. Also,
By connecting at least two or more trace memories in the depth direction and continuously recording the same trace data, a history of at least twice as long is recorded.

[0008]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 1 is a first trace memory, 2 is a second trace memory, and 3 is a trace address register that holds address information supplied to the address inputs of the first and second trace memories 1 and 2. If the number of entries (depth) of the first and second trace memories 1 and 2 is the same and is K, the trace address register 3 holds a bit width that can address 2K entries, and its most significant bit is The outputs except for the trace memories 1 and 2 are connected to the address inputs of the first and second trace memories 1 and 2. 4 is an adder 1 that adds trace addresses by 1, 5 is an AND gate that gates the input clock of trace address register 3, and 6 is trace data input 1 and trace data input 2.
When the trace mode switching signal 9 is logic 1 in a multiplexer that selects and outputs one of the following, its output becomes the trace data input 1. Reference numeral 7 indicates a trace memory write enable clock input, and reference numeral 8 indicates a trace write control signal, which performs writing when the logic is 1 and stops writing when the logic is 0. Reference numeral 9 is a trace mode switching signal which instructs a concatenation operation in the depth direction when it is logic 1, and instructs a concatenation operation in the width direction when it is logic 0. 10 is a write permission input for the first trace memory 1 (
Write Enable) A to gate the clock
ND gate 11 is an AND gate that gates the write enable input (Write Enable) clock of the second trace memory 2; 12 is an AND gate when the trace mode switching signal 9 is logic 1 and the value of the most significant bit of the trace address register 3 is 0; 13 is an AND gate that outputs logic 1 when the value of the most significant bit is 1, and 14 and 15 are AND gates that output logic 1 when trace mode switching signal 9 is logic 0.
Logic 1 when the outputs of D gates 12 and 13 are each logic 1
Chip Select for the first and second trace memories 1 and 2 using the OR gate that outputs
Connected to input. 16 is trace address register 3
an INVERTER gate that inverts the most significant bit of
17 is an INV that inverts the trace mode switching signal 9
This is an ERTER gate.

Next, the operation when the trace mode switching signal 9 is logic 1 will be explained. When the trace write control signal 8 is activated, the clock of the trace address register 3 starts to be input through the AND gate 5, and the output of the 1 adder 4 is taken in every clock.

At this time, if the address is less than or equal to K, the most significant bit of the trace address register 3 is 0, so the AND gate 12 outputs a logic 1, and the AND gate 1
3 outputs a logic 0. On the other hand, since the output of the INVERTER gate 17 is logic 0, the output of the OR gate 14 is logic 1, and the output of the OR gate 15 is logic 0, so the trace write permission clock 7 is input to the first trace memory 1 via the AND gate 10. However, since the AND gate 11 is closed, it is not input to the second trace memory 2. Further, a chip selection input is also input only to the first trace memory 1. Therefore, the trace data input 1 is written to the first trace memory 1.

Trace recording continues as the value of the trace address register 3 increases by 1, and eventually from K to K+
When it becomes 1, the most significant bit changes from 0 to 1. Then, the output of AND gate 12 becomes logic 0, and conversely A
The output of the ND gate 13 becomes logic 1. Its output is OR
The trace memory write enable clock 7 is input to the AND gates 10 and 11 via the gates 14 and 15.
begins to be input to trace memory 2. They are not input to the first trace memory 1 at the same time. The chip selection input is also input to the second trace memory 2 and not to the first trace memory 1.

Since the output of the multiplexer 6 is the trace data input 1, the trace data input 1 is continuously recorded in the second trace memory 2.

Next, the operation when the trace mode switching signal 9 is switched to logic 0 will be explained. When the trace write control signal 8 is activated, the clock of the trace address register 3 starts to be input through the AND gate 5, and the output of the 1 adder 4 is taken in every clock.

At this time, the outputs of the AND gates 12 and 13 are both logic 0, and the output of the INVERTER gate 17 is logic 1, so the outputs of the OR gates 14 and 15 are both logic 1, and the trace write enable clock 7 is AND.
to the first trace memory 1 through the gate 10, AND
It is input to the second trace memory 2 via the gate 11, and the chip selection input is also input to the first and second trace memories 1,
2 are also input. Therefore, trace data input 1 is written to the first trace memory 1 and multiplexer 6
Since the output of is trace data input 2, trace data input 2 is simultaneously recorded in the second trace memory 2.

Example 2. Note that the above explanation is based on the case where the trace memory is divided into two parts, but as is clear from the above explanation, it goes without saying that the same effect can be obtained by dividing the trace memory into three or more parts. stomach.

[0016]

As described above, according to the present invention, in a trace device that operates by dividing a trace memory into at least two parts and connecting them in the depth direction, it is possible to store the same trace data in each trace memory. Since it is possible to select any of the independent trace data, and at least two or more trace memories can be connected in the width direction using a single trace write control signal, it is possible to operate by connecting at least two trace memories in the width direction. This has the effect of providing a trace device that can record processing data.

Furthermore, in a trace device that operates by dividing the trace memory into at least two parts and connecting them in the width direction, it is possible to select either independent trace data or the same trace data and input it to each individual trace memory. , and configured so that trace data can be recorded independently using one trace write control signal, and at least two
Since two or more trace memories are connected in the depth direction so that they can be recorded sequentially, a trace device that can record history for at least twice as long can be obtained.

[0018]

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a tracing device showing an embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional tracing device.

FIG. 3 is a circuit diagram showing a conventional tracing device.

[Explanation of symbols]

1 First trace memory 2 Second trace memory 3 Trace address register 4 1 adder 5 AND gate 6 Multiplexer 7 Trace memory write enable clock 8 Trace write control signal 9 Trace mode switching signal 10 AND gate 11 AND gate 12 AND gate 13 AND gate 14 OR gate 15 OR gate 16 INVERTER gate 17 INVERTER gate

Claims (2)

[Claims] Claim 1: In a trace device that operates by dividing a trace memory that records the processing history of a data processing device into at least two parts and connecting them in the depth direction, each trace memory has the same trace data independently. and a means for operating by connecting at least two or more trace memories in the width direction using one trace write control signal, and recording processing data of at least twice the width. A tracing device characterized by: Claim 2: In a trace device that operates by dividing a trace memory for recording the processing history of a data processing device into at least two parts and connecting them in the width direction, either independent trace data or the same trace data is processed. It is equipped with a means for selecting and inputting it into individual trace memories and a means for recording trace data independently with a single trace write control signal, and at least two or more trace memories are connected in the depth direction and recorded sequentially. A tracing device characterized in that it records a history for at least twice as long.