JP4560204B2 - Synchronous memory address buffer circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an address buffer circuit that holds an address signal in synchronization with a clock signal in a synchronous memory.
[0002]
[Prior art]
2A and 2B are schematic configuration diagrams showing an example of a conventional synchronous memory. FIG. 2A is an overall configuration, and FIG. 2B is a diagram in FIG. An address buffer circuit is shown.
[0003]
The synchronous memory operates in synchronization with the clock signal CK of the system bus having a relatively high frequency, thereby reading the data stored in the memory cell to the outside and the data given from the outside to the memory cell. This is a faster writing speed. As shown in FIG. 2A, this synchronous memory includes address buffer circuits 1 and 2 that take in an externally applied address signal AD in synchronization with a clock signal CK, an externally supplied clock signal CK, and chip selection. Based on the signal CS, the address fetch signal AS, the read / write control signal RW, and the like, a control circuit 3 that generates an internal control signal is provided.
[0004]
The control circuit 3 includes a clear signal CL for erasing the contents held in the address buffer circuits 1 and 2, an address fetch signal EX for designating data holding timing, and a write control signal WE for designating a write operation to a sense amplifier 7 described later. And a read control signal RE for designating a read operation.
[0005]
The address buffer circuit 2 takes in the lower bits A0 to Am of the address signal AD, and the address buffer circuit 1 takes in the upper bits Am + 1 to An of the address signal AD. A row decoder 4 is connected to the output side of the address buffer circuit 1, and a column decoder 5 is connected to the output side of the address buffer circuit 2. The output side of the row decoder 4 is connected to the word line of the memory core 6.
[0006]
The memory core 6 is provided with a memory cell (MC) for storing data at each intersection of a plurality of word lines (WL) and bit lines (BL) arranged in an intersecting manner. A memory cell connected to one word line selected by a signal is connected to a corresponding bit line. Each bit line is connected to a corresponding sense amplifier (not shown) in the sense amplifier group 7. Each sense amplifier is connected to the data line DT via a transfer gate (column switch) (not shown) controlled by the output signal of the column decoder 5.
[0007]
As shown in FIG. 2B, the address buffer circuits 1 and 2 are each a synchronizing unit 10 that takes in each address signal Ai that constitutes the address signal AD in synchronization with the clock signal CK, and a control circuit that takes in the taken address signal Ai. 3 is comprised of an address latch unit 20 that holds the timing at the address take-in signal EX given from 3.
[0008]
The synchronizer 10 includes a transfer gate (hereinafter referred to as “TG”) 11 composed of an N channel MOS transistor (hereinafter referred to as “NMOS”) 11a and a P channel MOS transistor (hereinafter referred to as “PMOS”) 11b. The address signal Ai is supplied to the input side of the TG 11. The output side of the TG 11 is connected to a latch 12 composed of inverters 12 a and 12 b, and the output side of the latch 12 is connected to the input side of the inverter 13.
[0009]
The output side of the inverter 13 is connected to the input side of the TG 14 composed of the PMOS 14a and the NMOS 14b, and the output side of the TG 14 is connected to the latch 15 composed of the inverters 15a and 15b. The output side of the latch 15 is connected to the node NA via the inverter 16. The clock signal CK is supplied to the gates of the PMOS 11b and NMOS 14b, and is further supplied to the gates of the NMOS 11a and PMOS 14a through the inverter 17.
[0010]
The address latch unit 20 includes a 2-input negative AND gate (hereinafter referred to as “NAND”) 21 and an inverter 22 connected to the node NA, and the output side of the inverter is connected to the input side of the 2-input NAND 23. It is connected. An address take-in signal EX is given to the second input side of the NANDs 21 and 23.
[0011]
The output side of the NAND 21 is connected to the first input side of the NAND 24 a in a flip-flop (hereinafter referred to as “FF”) 24 composed of a 2-input NAND 24 a and a 3-input NAND 24 b. Further, the output side of the NAND 23 is connected to the first input side of the NAND 25a in the FF 25 including the 2-input NAND 25a and the 3-input NAND 25b.
[0012]
The output side of the NAND 24a is connected to the second input side of the NAND 24b. The output side of the NAND 24b is connected to the second input side of the NAND 24a and the first input side of the NAND 25b. Similarly, the output side of the NAND 25a is connected to the second input side of the NAND 25b. The output side of the NAND 25b is connected to the second input side of the NAND 25a and the first input side of the NAND 24b. A clear signal CL is supplied to the third input sides of the NANDs 24b and 25b.
[0013]
Further, buffers 26 and 27 are connected to the output sides of the NANDs 24a and 25a, respectively, and complementary address signals Xi and / Xi synchronized from these buffers 26 and 27 (where "/" means inversion). ) Is output.
[0014]
FIG. 3 is a signal waveform diagram showing an example of the operation of the address buffer circuit of FIG. The operation of the conventional address buffer circuit will be described below.
[0015]
When the address fetch signal EX is at the level “L” and the clear signal CL falls from the level “H” to “L” at the time t1 in FIG. 3, the FFs 24 and 25 of the address latch unit 20 are reset, and the address signal Xi and / Xi are both “L”. Thereafter, at time t2, the clear signal CL rises from “L” to “H”.
[0016]
At time t3, that is, the clock signal CK is “L”, and a predetermined time before rising to “H”, the address signal Ai is determined. Since the clock signal CK is “L”, TG11 is open and TG14 is closed. As a result, the address signal Ai (for example, “H”) is held in the latch 12, and the held signal is output to the output side of the inverter 13.
[0017]
Thereafter, at time t4, the clock signal CK rises to “H”. As a result, the TG 11 is closed and the TG 14 is opened, and the output signal of the inverter 13 is held in the latch 15 and is output from the node NA via the inverter 16 as the signal SA.
[0018]
When the address fetch signal EX changes from “L” to “H” at time t5, the NANDs 21 and 23 are opened, and the signal SA of the node NA is output from the NAND 21. Further, the signal SA of the node NA is inverted by the inverter 22 and output from the NAND 23. Output signals of the NANDs 21 and 23 are held in the FFs 24 and 25, respectively, and synchronized complementary address signals Xi and / Xi are output from the buffers 26 and 27, respectively.
[0019]
When the address fetch signal EX becomes “L” at time t6, the NANDs 21 and 23 are closed, and the output signals of these NANDs 21 and 23 both become “H”. As a result, the levels of the address signals Xi and / Xi held in the FFs 24 and 25 are held until the “L” clear signal CL is supplied to the FFs 24 and 25 at time t7.
[0020]
[Problems to be solved by the invention]
However, the conventional address buffer circuit has the following problems.
That is, when the address signal is supplied without satisfying the timing specifications, the FF 24 and the FF 25 may become “H”.
[0021]
When “H” is held in both the FFs 24 and 25, the address signals Xi and / Xi both become “H”. On the other hand, the address signals Xi and / Xi must be supplied to the row decoder 4 and the like as complementary signals. In particular, the row decoder 4 selects a single word line based on the complementary address signals Xi and / Xi, and both the address signals Xi and / Xi to be complementary are “H”. Then, a plurality of word lines are selected at the same time. When a plurality of word lines are simultaneously selected, a plurality of memory cells are connected via the bit line, the stored content is a problem that is destroyed.
[0022]
Usually, as timing specifications , a setup time between the input of the address signal Ai and the rise of the clock signal CK and a hold time for holding the address signal as it is after the rise of the clock signal CK are specified. If this is observed, the above problems will not occur. However, in a dummy cycle in which data is not actually read / written, a circuit having a timing condition that violates the above-mentioned rule is assumed, and in such a case, the above-described problem may occur.
[0023]
The present invention solves the problems of the prior art, and provides an address buffer circuit that does not hold an erroneous address signal that leads to destruction of stored contents even if the timing of the address signal Ai changes in a dummy cycle or the like To do.
[0024]
[Means for Solving the Problems]
In order to solve the above-mentioned problems, the present invention holds an address signal given from the outside in synchronization with a clock signal, and outputs the held address signal to an internal node, and outputs the address signal to the internal node. In an address buffer circuit of a synchronous memory comprising an address signal and an inverted address signal obtained by inverting the address signal based on an address fetch signal, and an address latch unit that outputs the retained complementary address signal. The address latch unit is configured as follows.
[0025]
That is, the address latch unit receives a complementary signal of the address signal of the internal node and the inverted address signal generated by inverting the address signal when the capture permission signal and the address capture signal are given. A complementary signal generating means for outputting, a first holding means for holding and outputting the address signal output from the complementary signal generating means, and erasing the held content when a clear signal is given, and the complementary signal A second holding means for holding and outputting the inverted address signal output from the signal generating means and erasing the held content when the clear signal is given; and the first and second holding means Capture control means for outputting the capture permission signal only when the retained contents are both erased.
[0026]
According to the present invention, since the address buffer circuit of the synchronous memory is configured as described above, the following operation is performed.
[0027]
In the synchronizer, an externally applied address signal is read and held in synchronization with the clock signal, and the held address signal is output to the internal node. The address signal output to the internal node is given to the complementary signal generating means.
[0028]
Here, when the capture permission signal and the address capture signal are given, a complementary address signal is generated and output by the complementary signal generating means, and held in the first and second holding means. When complementary address signals are held in the first and second holding means, the take-in permission signal from the take-in control means is stopped. As a result, the contents held by the first and second holding means are fixed.
[0029]
When a clear signal is given to the first and second holding means, the contents held in these first and second holding means are erased, and a take-in permission signal is output from the take-in control means. Further, when an address fetch signal is given, the address signal output to the internal node at that time is held in the first and second holding means. Thus, a new complementary address signal is held and output by the first and second holding means.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a configuration diagram of an address buffer circuit showing an embodiment of the present invention.
This address buffer circuit is provided as the address buffer circuit in FIG. 2A instead of the address buffer circuit in FIG. 2B, and is common to the elements common to the elements in FIG. The code | symbol is attached | subjected.
[0031]
The address buffer circuit includes a synchronizer 10 that takes in each address signal Ai that constitutes the address signal AD in synchronization with the clock signal CK, and an address latch unit 20A that holds the fetched address signal Ai at the timing of the address fetch signal EX. It consists of
[0032]
The synchronizer 10 is the same as the synchronizer in FIG. 2B, and has a TG 11 composed of an NMOS 11a and a PMOS 11b, and an address signal Ai is given to the input side of the TG 11. A latch 12 including inverters 12 a and 12 b is connected to the output side of the TG 11, and the output side of the latch 12 is connected to the input side of the inverter 13.
[0033]
The output side of the inverter 13 is connected to the input side of the TG 14 composed of the PMOS 14a and the NMOS 14b, and the output side of the TG 14 is connected to the latch 15 composed of the inverters 15a and 15b. The output side of the latch 15 is connected to the node NA via the inverter 16. The clock signal CK is supplied to the gates of the PMOS 11b and NMOS 14b, and is further supplied to the gates of the NMOS 11a and PMOS 14a through the inverter 17.
[0034]
The address latch unit 20A has complementary signal generation means (for example, 3-input NANDs 21A and 23A and an inverter 22). The first input side of the NAND 21A and the input side of the inverter 22 are connected to the node NA, and the output side of the inverter 22 is connected to the first input side of the NAND 23A. An address fetch signal EX is supplied to the second input side of the NANDs 21A and 23A. Further, the third input sides of the NANDs 21A and 23A are connected to the node NB so as to be provided with the capture permission signal EN.
[0035]
The output side of the NAND 21A is connected to the first input side of the NAND 24a in the first holding means (for example, FF) 24 composed of a 2-input NAND 24a and a 3-input NAND 24b. The output side of the NAND 23 is connected to the first input side of the NAND 25a in the second holding means (for example, FF) 25 constituted by a 2-input NAND 25a and a 3-input NAND 25b.
[0036]
The output side of the NAND 24a is connected to the second input side of the NAND 24b. The output side of the NAND 24b is connected to the second input side of the NAND 24a and the first input side of the NAND 25b. Similarly, the output side of the NAND 25a is connected to the second input side of the NAND 25b. The output side of the NAND 25b is connected to the second input side of the NAND 25a and the first input side of the NAND 24b. A clear signal CL is supplied to the third input side of the NANDs 24b and 25b.
[0037]
Further, buffers 26 and 27 are connected to the output sides of the NANDs 24a and 25a, respectively, and synchronized address signals Xi and / Xi are output from the buffers 26 and 27, respectively. The address signals Xi and / Xi are connected to the input side of the capture control means (for example, 2-input negative OR gate, hereinafter referred to as “NOR”) 28, and the output side of this NOR 28 is connected to the node NB. Has been. The take-in permission signal EN is output from the NOR 28 to the node NB.
[0038]
FIG. 4 is a signal waveform diagram showing an operation of the address buffer circuit of FIG. The operation of the address buffer circuit of FIG. 1 will be described below with reference to FIG.
[0039]
At time T1 in FIG. 4, it is assumed that the clear signal CL is “H”, the capture enable signal EN is “L”, the FF 24 is reset, and the FF 25 is set. As a result, the address signals Xi and / Xi are “L” and “H”, respectively. Here, when the address signal clock signal CK rises from “L” to “H”, the address signal Ai (AD1) is held in the latch 15 of the synchronizer 10 and is output from the node NA as the signal SA. At this time, since the contents held in the FFs 24 and 25 of the address latch unit 20A are “L” and “H”, respectively, the capture permission signal EN of the node NB is “L”, and the output signals of the NANDs 21A and 23A are both “ H ”. Therefore, the contents held in the FFs 24 and 25 do not change.
[0040]
When the clear signal CL falls from “H” to “L” at time T2, the FFs 24 and 25 are reset, and the address signals Xi and / Xi both become “L”. As a result, the capture enable signal EN becomes “H”. Thereafter, at time T3, the clear signal CL rises from “L” to “H”.
[0041]
When the clock signal CK rises from “L” to “H” at time T4, the address signal Ai (AD2) is held in the latch 15 of the synchronizer 10 and output to the node NA.
[0042]
When the address take-in signal EX changes from “L” to “H” at time T5, the NANDs 21A and 23A are opened, the signal SA of the node NA is output from the NAND 21A, and the signal SA is inverted by the inverter 22 to be NANDed 23A. Is output from. Output signals from the NANDs 21A and 23A are supplied to the FFs 24 and 25, respectively, held in the FFs 24 and 25, and synchronized address signals Xi and / Xi are output from the buffers 26 and 27, respectively.
[0043]
Thereby, the node NB becomes “L”, the NANDs 21A and 23 are closed, and the output signals of these NANDs 21A and 23A both become “H”. Thereafter, even if the address fetch signal EX becomes “H”, the NANDs 21A and 23A are not opened, and the level of the address signals Xi and / Xi held in the FFs 24 and 25 is the “L” clear signal CL. Until FFs 24 and 25 are provided.
[0044]
For example, when the address signal Ai changes almost simultaneously with the rise of the clock signal CK at time T6, the signal held in the latch 15 of the synchronizer 10 becomes indeterminate. However, even if the address fetch signal EX becomes “H” at this time, the fetch permission signal EN is “L”, so that this indeterminate signal is not fetched by the FFs 24 and 25.
[0045]
As described above, the address buffer circuit according to the present embodiment has the NOR 28 that sets the capture enable signal EN to “L” in order to close the NANDs 21A and 23A while the complementary address signals Xi and / Xi are applied. is doing. This prevents the contents held in the FFs 24 and 25 from being inadvertently rewritten and eliminates the possibility that the address signals Xi and / Xi simultaneously become “H”. Therefore, destruction of the stored contents of the memory cell due to simultaneous selection of a plurality of word lines due to the influence of noise or the like is prevented.
[0046]
Further, even when a signal ignoring the timing conditions of the clock signal CK and the address signal AD is given in a dummy cycle in which access to the memory cell is not actually performed, there is a possibility that the contents held in the FFs 24 and 25 are rewritten. There is no advantage.
[0047]
In addition, this invention is not limited to the said embodiment, A various deformation | transformation is possible. Examples of this modification include the following (a) and (b).
[0048]
(A) The circuit configuration of the synchronizer 10 is not limited to that shown in FIG. In other words, any circuit can be applied as long as it reads and holds the address signal Ai in synchronization with the clock signal CK.
[0049]
(B) The circuit configuration of the address latch unit 20A is not limited to that shown in FIG. That is, it is provided with two FFs 24 and 25 that generate and output complementary address signals Xi and / Xi, and a circuit that controls an address fetch operation according to the output signals of these FFs 24 and 25. It is equally applicable.
[0050]
【The invention's effect】
As described above in detail, according to the present invention, when complementary address signals are output from the first and second holding means, the capture control means for stopping the output of the capture permission signal; Complementary signal generation means is provided for generating a complementary address signal and supplying it to the first and second holding means when the acquisition permission signal and the address acquisition signal are given. As a result, there is no possibility that the address signal is simultaneously output from the first and second holding means, and the memory contents stored in the memory cell can be prevented from being destroyed by simultaneous selection of a plurality of word lines.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an address buffer circuit showing an embodiment of the present invention.
FIG. 2 is a schematic configuration diagram showing an example of a conventional synchronous memory.
FIG. 3 is a signal waveform diagram showing an example of the operation of the address buffer circuit of FIG.
4 is a signal waveform diagram showing an operation of the address buffer circuit of FIG. 1. FIG.
[Explanation of symbols]
10 Synchronizing part 11, 14 TG (transfer gate)
12, 15 Latch 20A Address latch unit 21A, 23A NAND (negative AND gate)
22 Inverters 24, 25 FF (flip-flop)
28 NOR (Negative OR gate)

Claims (1)

A synchronization unit that holds an address signal supplied from the outside in synchronization with a clock signal and outputs the held address signal to an internal node, and an inverted address signal obtained by inverting the address signal output to the internal node and the address signal In the address buffer circuit of the synchronous memory including the address latch unit that holds the address based on the address fetch signal and outputs the held complementary address signal.
The address latch unit is
Complementary signal generation means for outputting a complementary signal of the address signal of the internal node and the inverted address signal generated by inverting the address signal when the capture permission signal and the address capture signal are given;
Holding and outputting an address signal output from the complementary signal generating means, and a first holding means for erasing the held content when a clear signal is given;
Holding and outputting an inverted address signal output from the complementary signal generating means, and second holding means for erasing the held content when the clear signal is given;
Capture control means for outputting the capture permission signal only when the retained contents of the first and second retaining means are erased together;
An address buffer circuit for a synchronous memory, comprising:

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