JPH01202021A - Writing timing signal generating circuit - Google Patents

Abstract

PURPOSE:To accurately write data in a storage circuit and to suppress the generation of irregular writing by providing the title circuit with a delay circuit and 1st and 2nd logical circuits. CONSTITUTION:The writing timing signal generating circuit has the delay circuit 1 for outputting a 1st delay signal obtained by inputting a write instruction signal and delaying the signal by a fixed time and a 2nd delay signal obtained by delaying the 1st delay signal furthermore by a prescribed time, a 1st logic circuit 2 for validating its output when both the write instruction signal and the 1st delay signal are valid and a 2nd delay circuit 3 for outputting a write timing signal to be validated when the output of the 1st logical circuit is valid and the 2nd delay signal is invalid. When an irregular pulse signal is generated as the write instruction signal, the write instruction signal is delayed by a time longer than the time width of the irregular signal to obtain the 1st delay signal and the 1st delay signal and the write instruction signal are inputted to the 1st logic circuit 2, so that both the outputs of the 1st and 2nd logic circuits are not validated and the irregular write instruction signal does not appear in the write timing signal.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a write timing signal generation circuit used when configuring a memory circuit in a digital circuit.

2. Description of the Related Art In a conventional digital circuit, when writing data to a storage circuit such as a register or a memory, a circuit configuration as shown in FIG. 4 is used. Each component of the circuit shown in FIG. 4 will be explained.

The memory circuit 6 is composed of registers and memories, and has data input/output and a write input for instructing writing. Data can be written to the memory circuit 5 by making the signal input to the write input valid during data input, and deactivating it after a time dependent on the memory circuit 6 has elapsed. When address signal f indicating writing of data to storage circuit 6 and read/write control signal g are input, address decoder 4 makes valid write instruction signal a as an output. Bidirectional data buffer 6.

It has a data direction switching input, and depending on the signal input thereto, data h is output to the memory circuit 6 when writing to the memory circuit 6, and data h is input when reading.

The configuration and operation of the circuit shown in FIG. 4 will be described next.

When the address signal f indicating writing to the memory circuit 6 and the read/write control signal g are input to the address decoder 4, the write instruction signal a is enabled as shown in FIG. (L level). By inputting this write instruction signal a to the data direction switching input of the bidirectional data buffer 6, the bidirectional data buffer 6 transfers the write data h to the storage circuit 6, as shown in FIG.
Output to. The write instruction signal a is also input to the memory circuit 6, and when the write instruction signal a becomes invalid,
That is, data h is written into the storage circuit 6 when rising from the L level to the H level.

Problem to be Solved by the Invention In the circuit configuration shown in FIG. 4, the write instruction signal a is input to both the data direction switching input of the bidirectional data buffer 6 and the write input of the storage circuit 6. As is clear from the figure, the data h input to the memory circuit 6 is lost at the same time as the write input to the memory circuit 6 becomes invalid and writing is performed (at time 14).

Therefore, there is a possibility that accurate data cannot be written into the memory circuit 6, and the write operation becomes uncertain.

Furthermore, in the circuit configuration of FIG. 4, even if the address signal f does not represent writing to the memory circuit 6.

When the address signal f changes, the time of change is shifted for each bit of the address signal f, which causes the address decoder 4 to output an incorrect signal as the write instruction signal a, as shown in FIG. 6B. There is a possibility that Therefore, there is a possibility that a malfunction such as illegal writing to the memory circuit 5 may occur.

In order to solve the above-mentioned problems, the present invention can accurately write data to a memory circuit and also suppress the occurrence of unauthorized writing.

An object of the present invention is to provide a write timing signal generation circuit for a memory circuit.

Means for Solving the Problems The present invention employs the following configuration in order to solve the above problems. A delay circuit that receives a write instruction signal and outputs a first delayed signal obtained by delaying the write instruction signal by a predetermined time, a second delay signal obtained by further delaying the first delayed signal by a predetermined time, and a write instruction signal. A first logic circuit whose output is valid when both the first delay signals are valid, and a write timing that is valid when the output of the first logic circuit is valid and the second delay signal is not valid. The W2 logic circuit outputs a signal and is composed of the above circuits.

Effect: By adopting the above-mentioned configuration, one problem is solved as follows.

When an invalid pulse signal is generated as a write instruction signal, the write instruction signal is delayed by a time longer than the time width of this invalid signal to obtain a first delayed signal, and this first delayed signal and write instruction signal are combined. When input to the first logic circuit, the write instruction signal and the first delay signal are never valid at the same time, and as a result, the output of the logic circuit in box 1 is not valid. Since the output of the first logic circuit is not valid, the output of the second logic circuit is also not valid,
An invalid write instruction signal does not appear in the write timing signal.

Next, the case of writing to the memory circuit will be described.

The write timing signal is valid only after the output of the first logic circuit becomes valid until the second delay signal becomes valid. The output of the first logic circuit becomes valid when the first delay signal becomes valid. That is,
The period during which the write timing signal is valid is from when the first delay signal becomes valid until when the second delay signal becomes valid. In other words, the first delay signal of the second delay signal
is the delay time of the delayed signal. By adjusting this delay time, it is possible to obtain a write timing signal necessary for writing data into the memory circuit.

In this way, by adopting the above-described configuration, it becomes possible to supply a write timing signal that allows reliable writing to the memory circuit.

Example An embodiment of the present invention is shown in FIG. In this example.

Both the write instruction signal and the write timing signal are negative logic. That is, the above two signals are.

It means that the logic value is valid when it is at L level, and it is not valid when it is at H level. A delay line is used as the delay circuit 1 to which a write instruction signal is input. Delay circuit 1
When the write instruction signal is delayed by a time t1, a first delay signal C is output, and a second delay signal C, which is delayed by a time t2, is output.

However, t2 must be larger than tl.

The write instruction signal a and the first delay signal S are input to a two-manpower NOR gate, which is the first logic circuit 2 . The output d of the first logic circuit 2 and the second delay signal C are input to a second logic circuit (two-manufactured NANI) gate, and the output of this second logic circuit becomes the write timing signal e.

FIG. 2 shows a circuit configuration when the circuit shown in FIG. 1 is used to improve the conventional circuit shown in FIG. 4. The circuit shown in FIG. 2 is constructed. address decoder 4, memory circuit 6,
Bidirectional data buffer 16 is the same as that in the conventional circuit example of FIG.

Here, the same components are given the same numbers and detailed explanations are omitted. The circuit shown in FIG. 2 differs from the circuit shown in FIG. The write timing signal e which is the output of the memory circuit 6
This is the point where the input is made.

The operation of the embodiment of the present invention will be explained based on FIG.

Here, the operating characteristics of the components and signals of the circuit shown in FIG. 2 are as follows. Assume that when the address signal f changes, there is a maximum time lag of 10+1 seconds between the bits forming the signal.

Next, when reading or writing data to a certain address.

Address signal f and read/write control signal g.

It is assumed that the address is input to the address decoder 4 for 250+1 seconds. From this, when the address signal f representing writing to the memory circuit 6 and the read/write control signal g are input to the address decoder 4, the address decoder 4 receives 250+
The write instruction signal & is valid for only one second. In order to write data to the memory circuit 6, the write input must be 150+1.
It is necessary to make it valid for more than a second and then make it invalid. The delay circuit 1 outputs the write instruction signal a by 16+1
When the first delay signal is delayed by seconds, the write instruction signal a
A second delayed signal C, which is delayed by 175-)-1 seconds, is output.

FIG. 3 shows the waveforms of each signal in FIG. 2. First, the operation when data is written into the memory circuit 5 will be explained.

(See Fig. 3) The address signal f indicating writing to the memory circuit 6 and the read/write signal g are sent to the address decoder 4.
, the write instruction signal a output from the address decoder 4 becomes valid for 250+1 seconds. When this write instruction signal a enters the data direction switching input of the bidirectional data buffer 6, data h is output from the bidirectional buffer 16 to the storage circuit 6. On the other hand, the write instruction signal a is input to the delay circuit 1 and the first logic circuit 2. The first logic circuit 2 is inputted with a first delay signal S which is the write instruction signal a delayed by 15+1 seconds. As the output d of the first logic circuit 2, a signal is obtained which becomes valid 16,011 seconds after the write instruction signal a becomes valid and becomes invalid at the same time as the write instruction signal a becomes invalid.

The output d of the first logic circuit 2 and the second delay signal C are input to the second logic circuit 3, and the output becomes valid 16,01 seconds after the write instruction signal a becomes valid. Thereafter, a write timing signal e is obtained which is valid for only 160+1 seconds. This write timing signal e
is 160 while data h is input to the memory circuit 6.
Valid for +1 second only. By inputting such a write timing signal e to the write input of the memory circuit 6,
It becomes possible to write data reliably.

Next, the operation when an invalid write instruction signal a is generated will be explained. (See Figure 3B) This illegal write instruction signal a is generated in the form shown in Figure 3B due to the shift in the change time of each pit of the address signal f, and the width of the signal is 1o.
+1 second or less.

When the invalid write instruction signal & is input to the delay circuit 1, both the first delay signal b and the second delay signal C are generated as invalid signals. However, since the first delay signal a is delayed by 16,01 seconds from the write instruction signal a, the first delay signal
The write instruction signal a will not become valid at the same time if the delay signal a is used. Therefore, the output of the first delay circuit 2 never becomes valid, and therefore the output of the second logic circuit 3, that is, the write timing signal θ never becomes valid. As described above, even if an incorrect write instruction signal a is generated, malfunctions can be prevented.

As explained above, daylay line and NOR game),
With a simple configuration in which one NANI) gate is used, a circuit has been obtained that can generate a timing signal necessary for writing data into a memory circuit and can prevent malfunctions. With this circuit configuration, it is possible to adjust the delay time of the delay circuit even if the time required to enable the write input when writing data to the memory circuit or the shift in address signal change differs from the above example. It is possible to easily deal with this.

Effects of the Invention The present invention takes a write instruction signal as input, and outputs a first delayed signal that is delayed by a certain amount of time, and a second delayed signal that is further delayed from the first delayed signal by a certain amount of time. a delay circuit, a first logic circuit which receives a write instruction signal and a first delay signal as inputs and whose output is valid when both of these two signals are valid; The second logic circuit receives the second delay signal as input and outputs a write timing signal that becomes valid when the output of the first logic circuit is valid and the second delay signal is not valid.

When the above circuit configuration is adopted, when an invalid write instruction signal is generated, the first delay signal that delays the write instruction signal by a time longer than the width of this invalid signal, and the By using the first logic circuit that makes the output valid only while both are valid, it is possible to suppress illegal write instruction signals. Furthermore, when writing to the memory circuit, the second logic circuit makes the output valid only after the first delay signal becomes valid until the second delay signal becomes valid. A write timing signal necessary for writing data can be generated.

By implementing the above-described circuit configuration and operation, the present invention makes it possible to obtain a write timing signal that can reliably write to a memory circuit with a simple circuit configuration.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a write timing signal generation circuit according to an embodiment of the present invention, FIG. 2 is a configuration diagram of a memory circuit and its peripheral circuits to which the circuit of FIG. 1 is applied, and FIG. Fig. 2 is a signal waveform diagram of each part, Fig. 4 is a configuration diagram of a conventional memory circuit and its peripheral circuits, and Figs.
FIG. 3 is a signal waveform diagram of each part in the figure. DESCRIPTION OF SYMBOLS 1... Delay circuit, 2... First logic circuit, 3... Second logic circuit, a... Write instruction signal, b... ...First delayed signal, C.
...Second delay signal, e...Write timing signal. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 3
Figure □

Claims (1)

[Claims] a first delay signal that receives a write instruction signal and delays the write instruction signal by a certain period of time; and
a delay circuit that outputs a second delayed signal obtained by delaying the delayed signal of 1 by a predetermined time, and receives the write instruction signal and the first delayed signal as inputs, and the states of both of the inputs are valid. a first logic circuit whose output is valid at the time; the output of the first logic circuit and the second delay signal are input, and the output of the first logic circuit is valid and the output of the first logic circuit is A second logic circuit is provided that makes the output valid when the second delay signal is not valid, and upon receiving the write instruction signal, the second logic circuit outputs a write timing signal necessary for writing to the memory circuit. A write timing signal generation circuit characterized in that it is configured to obtain an output from a logic circuit.