JPH05144269A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To achieve the high speed of an STRAM by means of a simple constitution by a method wherein a piece of address data is input in synchronization with a clock signal and a piece of data is read out at the cycle of the clock signal. CONSTITUTION:A synchronizing-signal generation circuit 9 generates clock signals A to D which are output so as to be delayed sequentially on the basis of a fundamental clock CLOCK. The signal A is sent to an input register circuit 2, and a piece of address data is held. Then, the signal B is sent to a selection register circuit 3, and a selection signal which is output by an address decoder circuit 1 on the basis of the piece of address data is held. Then, the signal C is sent to a drive register circuit 6, an amplifier circuit 5 is activated, and the piece of data, of a memory cell in a memory cell array circuit 4, which has been selected and read out on the basis of the selection signal is amplified. The signal D is sent to an output register circuit 7. A piece of data which is not output from the circuit 5 is held, and it is sent to a data output circuit 8. Consequently, when the piece of data is input in synchronization with the clock signals, it is read out at a clock cycle.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
Specifically, it relates to a clock synchronous static RAM.

Increasing the capacity of semiconductor memory devices in recent years
Along with the increase in speed, there is a demand for larger capacity and higher speed even in a clock synchronous static RAM.

[0003]

2. Description of the Related Art Conventionally, a static RAM is a clock synchronous static RAM (hereinafter referred to as STRAM).
There is. The STRAM is adapted to perform various operations such as reading and writing in synchronization with a clock signal.

[0004]

[Problems to be Solved by the Invention] However, STR
In AM, operation in a cycle faster than the access time cannot be guaranteed. In other words, increasing the speed of the STRAM has become a major problem that must be solved when it is used as a memory of a high-speed workstation or a cache memory used in a large computer.

The present invention has been made to solve the above problems, and its purpose is to provide a STRAM with a simple structure.
Another object of the present invention is to provide a semiconductor memory device capable of achieving higher speed.

[0006]

FIG. 1 illustrates the principle of the present invention. The address decoder circuit unit 1 is provided with an input register circuit 2 at the preceding stage, and inputs address data via the input register circuit 2. The selection register circuit 3 is connected between the address decoder circuit unit 1 and the memory cell array circuit unit 4, and holds the selection signal selected by the address decoder circuit unit 1. The main sense amplifier circuit section 5 amplifies the data of a predetermined memory cell read from the memory cell array circuit section 4 based on the contents held by the drive register circuit 6. The output register circuit 7 is provided on the output side of the main sense amplifier circuit unit 5, holds the data output by the amplifier circuit unit 5, and outputs it to the data output circuit unit 8 of the next stage.

The synchronizing signal generating circuit 9 is a basic clock signal C.
First to fourth clock signals A to D that are sequentially delayed and output based on LOCK are generated. Then, the first clock signal A output earlier is output to the input register circuit 2 to operate the circuit 2 and hold the address data. Second clock signal B that is output with a delay
To the selection register circuit 3 to output the selection register circuit 3
Is operated later than the input register circuit 2, and the address decoder circuit unit 1 holds the selection signal output based on the address data.

Next, the third clock signal C output with a delay is output to the drive register circuit 6, the amplifier circuit section 5 is activated with a delay from the selection register circuit 3, and selection is made based on the selection signal. The read data of the memory cell of the memory cell array circuit unit 4 is amplified. And
The fourth clock signal D finally output is output to the output register circuit 7, and the data output from the main sense amplifier circuit unit 5 is held and output to the data output circuit unit 8.

[0009]

Therefore, according to the present invention, each circuit section 1, through each circuit 2, 3, 6, 7 corresponding to the first to fourth clock signals A to D outputted by the synchronizing signal generating circuit 9, respectively.
4, 5, and 8 operate while sequentially shifting the timing.
As a result, if address data is input in synchronization with the clock signal CLOCK, data can be read in the cycle of the clock signal.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment embodying the present invention will now be described with reference to FIGS.
It will be described with reference to FIG. FIG. 2 shows a block circuit diagram of a main part of the STRAM, in which each bit signal of the address data is input to the address decoder 22 via the input register 20 and the level conversion circuit 21. Each input register 20 is shown in FIG. Each input register 20 is an ECL input register, and includes resistors R1 and R2, ECL-coupled transistors T1 and T2, a constant current source I1, and a synchronization connected between the emitters of the transistors T1 and T2 and the constant current source I1. Transistor T3 for current control, an output circuit section including emitter follower transistors T4, T5 and constant current sources I2, I3, and ECL-coupled transistors T6, T7 and their transistors T6, T
7 and a holding circuit section including a transistor T8 connected between the constant current source I1 and the constant current source I1.

The ECL level bit signal is input to the base of one transistor T1 of the transistors T1 and T2 that are emitter-coupled in the current control circuit section, and the reference voltage VR1 is input to the base of the other transistor T2. Has been done. A clock signal (hereinafter, referred to as a first clock) A is input to the base of the synchronizing transistor T3, and a reference voltage VR2 is input to the base of the transistor T8 of the holding circuit section.

Then, a bit signal that constitutes one of the address data is input, and the first clock A has a low potential (hereinafter,
When the voltage rises from L level) to a high potential (hereinafter, H level), one of the ECL-coupled transistors T1 and T2 is turned on and the other is turned off based on the level of the bit signal. Based on this operation, the complementary output signal (complementary bit signal) corresponding to the bit signal at that time is output from the emitters of the transistors T4 and T5 in the output circuit section. Further, even if the first clock A falls from the H level to the L level, the complementary bit signals are input to the bases of the transistors T6 and T7 of the corresponding holding circuit sections, respectively, so that the first clock of the next H level is generated. The contents of the bit signal are held until A is input. Therefore, each input register 20 outputs each complementary bit signal of the address data to the level conversion circuit 21 of the next stage in response to the first clock A.

The level conversion circuit 21 is a circuit for converting an ECL level signal into a TTL level. The level conversion circuit 21 converts the ECL level complementary bit signal output from the input register 20 into a TTL level and then the address decoder 22.
To enter. FIG. 4 shows an example of the level conversion circuit 21. That is, this input register 20 is a P channel MO
S transistor (hereinafter referred to as PMOS transistor)
Q1-Q4, N-channel MOS transistor (hereinafter N
It is composed of Q5 to Q8 (referred to as MOS transistors) and bipolar transistors T9 and T10.

Then, the PMOS transistors Q1 and Q4
And complementary bit signals of ECL level corresponding to the PMOS transistors Q2 and Q3, respectively, are input, and based on the levels, the bipolar transistors T9 and T10 are turned on / off so as to oppose each other, and the transistors T9 and T1 are turned on and off.
A complementary bit signal of TTL level is output from the emitter of 0. Therefore, the level conversion circuit 21 uses the first clock A
In synchronism with the above, the ECL level complementary bit signal output from the input register 20 is level-converted into a TTL level complementary bit signal and output to the address decoder 22 which operates at the TTL level in the next stage.

The first clock A is generated by a synchronizing signal generating circuit. This synchronization signal generation circuit is shown in FIG.
As shown in FIG. 5, it is composed of a chopper circuit 23, a level conversion circuit 24, and three delay circuits 25 to 27. The chopper circuit 23 is a well-known circuit, and as shown in FIG. 5, receives the basic clock CLOCK, rises to the H level in response to the rise, and rises to the L level at a predetermined time faster than the fall of the clock CLOCK. The first clock A that goes down is output. Then, the clock A is output to the input register 20 and is level-converted by the level conversion circuit 24 from the ECL level to the TTL level first clock A and output to the delay circuit 25.

FIG. 6 shows an example of the delay circuit 25. In the delay circuit 25, a plurality (even number) of inverter circuits INV are connected in series, and one end of a series circuit in which a plurality of NMOS transistors Q10 are connected in series is connected to a node between the respective inverter circuits INV. The other end of the series circuit is connected to the ground wiring. Also,
A capacitor element C having the other end connected to the ground wiring is connected between the NMOS transistors Q10 in the series circuit. Then, the NMOS transistor Q10
NMOS transistor Q1 in each row of each series circuit
The gates of 0 are common memories (ROM) M1 and M, respectively.
2 ... is connected. The fuse ROM 28 is appropriately written at the time of shipping or testing, and when the NMOS transistor Q10 in the corresponding row is turned on, a logical value “H” is written (fuse RO).
M28 is cut by a laser or the like), and if not turned on, writing is not performed and the logical value "L" is kept (the fuse ROM 28 is not cut). Then, when turning on, the NMOS transistor Q close to the inverter circuit INV
It is designed to be turned on in order from 10.

Therefore, the NMOS transistor Q1 of each row is
When all 0s are turned off, the first-stage inverter circuit I
The first clock A input to the NV is the inverter circuit I
After being delayed by the time based on the operation delay of NV, it is output as the second clock B from the inverter circuit INV at the final stage. When the delay time td1 is increased, the NMOS transistor Q1 close to the inverter circuit INV
When turned on sequentially from 0, the capacitor element C is connected to each node between the inverter circuits INV, and the delay time td1 becomes longer due to the increase in the number.

In the present embodiment, the delay time td1 is the time at which the address decoder 22 inputs the address data and the next first clock A is output at the timing before the new address data is input. I am trying to.

The second clock B is input to the delay circuit 26 at the next stage. The delay circuit 26 has the same circuit configuration as the preceding stage and the delay circuit 25, and the delay time td2 is appropriately selected to be the second circuit.
The third clock C delayed by the delay time td2 with respect to the clock B is output. This delay time td2 is the time when the data of the memory cell MC of the cell array circuit section, which will be described later, is read out through the pre-sense amplifier, and the next second clock B is output and the memory cell MC newly selected is output. The output time is set to the timing before the data is output.

Similarly, the third clock C is input to the delay circuit 27 at the next stage. The delay circuit 27 has the same circuit configuration as the delay circuit 25, and outputs the fourth clock D delayed by the delay time td3 with respect to the third clock C by appropriately selecting the delay time td3. This delay time td3 is the memory cell M read by the main sense amplifier 40 described later.
When the C data is output, the next third clock C
Is output and the data of the newly selected memory cell MC is output at the timing before being output from the main sense amplifier 40.

The clocks B to D are output to the register provided in the STRAM described later. An address decoder 22 that inputs each bit signal of address data via the input register 20 and the level conversion circuit 21 in synchronization with the first clock A is shown in FIG.

The address decoder 22 is composed of a row address decoder section and a column address decoder section. Then, the address data is decoded, and the row address decoder unit is selected from the plurality of global word lines GWL and also selected from the plurality of local word lines LWL. Further, the column address decoder section selects one of the plurality of block selection lines BSL.

Then, in this embodiment, when the global word line GWL and the local word line LWL are selected, these same lines become L level. Also, the block selection line BS
When L is selected, the same line becomes H level.

A NAND circuit 30 (only one is shown in the figure) constituting the selection register circuit 29 is provided corresponding to each block selection line BSL, and a selection signal is input from the column address decoder section via the block selection line BSL. To do. Also, the second clock B is input to one input terminal of the NAND circuit 30. The output terminal of each NAND circuit 30 is connected to each column selection line CSL. Then, in the present embodiment, the block selection line BSL is selected and becomes H level, and the second clock B rises to H level and the output of the NAND circuit 30 (column selection signal).
When it goes to L level, the column selection line CSL is selected. When the column selection line CSL is selected, the bit line B corresponding to the column selection line CSL is selected.
Memory cell array circuit section 34 connected to L and BL
The transfer gate transistor constituting the above is turned on.

On the other hand, similarly, to each local word line LWL, NOR circuits 31 and 32 (corresponding to the NAND circuit 30 are shown in the figure) constituting the selection register circuit 29 are connected to each local word line LWL. , A selection signal is input from the row address decoder unit via the local word line LWL. The column selection signal from the NAND circuit 30 is input to one of the input terminals of the NOR circuits 31 and 32. And the local word line LW
When L is selected and becomes L level and a column selection signal of L level is input, the corresponding NOR circuits 31, 32
Outputs an H level control signal.

A register circuit 33 (only one of the NOR circuits 31 and 32 is shown in the figure) forming a corresponding selection register circuit 29 is connected to the output terminals of the NOR circuits 31 and 32, respectively. Each register circuit 33 is shown in FIG.
As shown in, the control signals are input from the corresponding NOR circuits 31 and 32 to the input terminals of the inverter circuit 33a composed of the PMOS transistor Q21 and the NMOS transistor Q22. A selection signal is input to the source terminal of the NMOS transistor Q22 from the row address decoder section via the corresponding global word line GWL. PMOS
A reset PMOS transistor Q23 is connected in parallel to the transistor Q21. The output terminal of the inverter circuit 33a is connected to the latch circuit 33b composed of two inverter circuits, and the output terminal of the latch circuit 33b is connected to the word line WL. Each word line WL is connected to a plurality of corresponding memory cells MC provided between each bit line pair BL and bar BL. Then, when the control signal is at the H level,
When the corresponding global word line GWL is selected and becomes L level, the latch circuit 33b holds the H level and the word line WL of the register circuit 33 is selected.

That is, when the selection signal is output from the row address decoder section and the column address decoder section of the address decoder 22 and the H-level second clock B is output, a predetermined word line WL and a bit line pair. BL,
The bar BL is selected, and one memory cell MC forming the memory cell array circuit section 34 is selected.
Then, the data of the selected memory cell MC is output to a pre-sense amplifier (not shown) forming the memory cell array circuit section 34.

Next, P for resetting the register circuit 33 is set.
A reset signal generation circuit that generates a reset signal input to the gate terminal of the MOS transistor Q23 will be described with reference to FIG. In FIG. 9, the reset signal generation circuit includes a word line selection detection circuit 35, a chopper circuit 36, and a delay circuit 37.

The word line selection / detection circuit 35 uses each word line W.
When an L selection signal is input and all the word lines WL are L level and not selected, an H level output signal is output. On the contrary, one word line WL is selected from all the word lines WL.
Is selected at the H level, the word line selection detection circuit 35 outputs an L level output signal.

The chopper circuit 36 is a known chopper signal generating circuit composed of a NOR circuit 36a for inputting the output signal of the word line selection detection circuit 35 and an even number of inverter circuits 36b for feeding back the output signal of the NOR circuit 36a. When the output signal of the word line selection detection circuit 35 changes from H level to L level, a chopper signal is output. The pulse width from the rising edge to the falling edge of the chopper signal is preset by the number of even-numbered inverter circuits 36b. The chopper signal of the chopper circuit 36 is input to the delay circuit 37.

The delay circuit 37 has the same circuit configuration as that of the delay circuit 25 shown in FIG. 6, and inverts the chopper signal and delays the inverted chopper signal for a predetermined time to reset each register as a reset signal. The signal is output to the gate of the PMOS transistor Q23 of the circuit 33. Therefore, each register circuit 33 is reset all at once based on this reset signal, and all the word lines WL are brought into the L level non-selected state.

That is, the second clock B is output, the register circuit 33 selects a predetermined word line WL (at this time, the bit line pair BL and bar BL are also selected), and one memory cell MC is selected. After a lapse of a certain time, the reset signal generation circuit resets the register circuit 33 and deselects all the word lines WL.

The data of the selected memory cell MC is output to a pre-sense amplifier (not shown) forming the memory cell array circuit section 34. The data amplified by the pre-sense amplifier is output to the main sense amplifier 40.
The circuit of the main sense amplifier 40 is shown in FIG. In FIG. 10, main sense amplifiers for each bit line pair BL and bar BL (in the figure, one bit line pair B
Main sense amplifier for L and BL is shown) 40
Is an input transistor T consisting of a bipolar transistor
21 and T22 have base terminals BL and BL, respectively.
The bar BL is connected. The emitters of the input transistors T21 and T22 are NMs that form a constant current circuit.
Transistors T23 and T24 which are connected to the OS transistors Q31 and Q32 and are ECL coupled
It is connected to the base terminal of. The emitter terminals of the ECL-coupled transistors T23 and T24 are connected to an NMOS transistor Q33 which constitutes a constant current circuit.

Each of the NMOS transistors Q31 to Q33 forming the constant current circuit is turned on based on an H level control signal from the register circuit 41 as a drive register circuit. That is, each of the NMOS transistors Q31 to Q33
The main amplifier operates based on the turning on.

The register circuit 41 has the same circuit configuration as the register circuit 33 shown in FIG. 8, and the inverter circuit 41a composed of a PMOS transistor and an NMOS transistor inputs the third clock C into its input terminal. ing. The source terminal of the NMOS transistor is connected to the ground wiring. The output terminal of the inverter circuit 41a is connected to the latch circuit 41b composed of two inverter circuits, and the output terminal of the latch circuit 41b is connected to each of the NMOS transistors Q31 to Q31.
It is connected to the gate terminal of 33. Therefore, when the third clock C rises to the H level, the latch circuit 41b holds the H level and each of the NMOS transistors Q31 to Q3.
3 is turned on to start the amplification operation of the main amplifier.
The reset PMOS transistor Q34 receives the reset signal from the reset signal generation circuit and resets the contents of the latch circuit 41b.

The ECL-coupled transistor T2
The collector terminals of T3 and T24 are connected to the emitter terminals of bipolar transistors T25 and T26, respectively. On-resistances composed of PMOS transistors Q35 and Q36 are connected to the emitter terminals of the transistors T25 and T26, and resistors R3 and R4 are connected to the collector terminals.
Are connected. Then, the transistors T25 and T2
A predetermined reference voltage VR3 is connected to the base terminal of the transistor 6, and the read and amplified cell data from the bit lines BL and BL are respectively transferred to the transistor T2.
It outputs to the base terminals of the emitter follower transistors T27 and T28 of the next stage output circuit section through the collector terminals of T5 and T26.

Emitter follower transistors T27, T
An NMOS forming a constant current circuit is provided at the emitter terminal of 28.
Transistors Q37 and Q38 are connected. Then, the amplified cell data is transferred to the transistor T27,
It is output from the emitter terminal of T28 to the output register 50 of the next stage.

The output register 50, as shown in FIG.
Resistors R6 and R7, ECL coupled transistor T3
1, T32, constant current source I11 and transistor T31,
A current control circuit unit including an NMOS transistor Q41 for synchronization connected between the emitter of T32 and the constant current source I11, and emitter follower transistors T33 and T3.
4 and an output circuit section consisting of constant current sources I12 and I13, and ECL-coupled transistors T35 and T36, and an NMOS transistor Q42 for synchronization connected between the emitters of the transistors T35 and T36 and the constant current source I11.
And a holding circuit section.

The EC of the main sense amplifier 40 is provided at the base of one transistor T31 of the transistors T31 and T32 which are ECL-coupled in the current control circuit section.
One of the L-level data signals (complementary signals) is input, and the other of the data signals (complementary signals) is input to the base of the other transistor T32. The fourth clock D is input to the gate of the synchronization NMOS transistor Q41, and the inverted signal bar D of the fourth clock D is input to the gate of the synchronization NMOS transistor Q42 in the holding circuit section. ..

When the data signal is input and the fourth clock D rises from the L level to the H level, either one of the ECL-coupled transistors T31 and T32 is turned on based on the level of the data signal and the other is turned on. Turns off. Based on this operation, complementary data signals corresponding to the data signal at that time are output from the emitters of the transistors T33 and T34 in the output circuit section. Further, even when the fourth clock D falls from the H level to the L level, the complementary data signals are input to the bases of the transistors T35 and T36 of the corresponding holding circuit units, respectively.
The content of the complementary data signal is held until the next fourth clock D of H level is input.
Therefore, each output register 50 outputs the complementary data signal to the output buffer circuit 60 as the data output circuit unit of the next stage in response to the fourth clock D.

The output buffer circuit 60 is composed of an ECL circuit, and includes a resistor R8 and an ECL-coupled transistor T3.
7, T38, a constant current source I14, and a current control circuit section, and an output circuit section whose base is an emitter follower transistor T39 connected to the collector of the transistor T38.

Then, the ECL coupled transistor T
One of the complementary data signals of the output register 50 is input to the base of one transistor T37 of 37 and T38, and the other data signal of the complementary data signals is input to the base of the other transistor T38.

Based on the level of the complementary data signal, one of the ECL-coupled transistors T37 and T38 is turned on and the other is turned off. Based on this operation, the data stored in the selected memory cell at that time is output from the emitter of the emitter follower transistor T39.

Next, the STRAM configured as described above
The action of will be described. Now, as shown in FIGS. 5 and 12, when the address data A1, A2, ... Are input in synchronization with the rising edge of the basic clock CLOCK, the chopper circuit 23 outputs the first data from the chopper circuit 23 in response to the basic clock CLOCK.
The clock A is output, and based on the clock A, each input register 20 inputs the address data A1 and outputs it to the address decoder 22 via the level conversion circuit 21. The input register 20 waits for the input of the next address data A2 with the disappearance of the first first clock A, and holds the previous data A1. That is, the selecting operation of the address decoder 22 based on the address data A1 is surely performed.

When td1 time has elapsed since the first clock A was output, the delay circuit 25 outputs the second clock B based on the first clock A to the NAND circuit 30. On the other hand, the address decoder 22 selects a predetermined block selection line BLS based on the address data A1 to bring it to the H level, and also selects a predetermined global word line GWL and local word line LWL to bring it to the L level. Based on the selection of the second clock B, the block selection line BLS, the global word line GWL and the local word line LWL,
A predetermined column selection line CSL is selected and becomes L level, and a predetermined NOR circuit (for example, NOR circuit 31) is selected and outputs an H level control signal.

With the control signal and the selected global word line GWL, the selected register circuit 33 sets the word line WL connected to the register circuit 33 to the H level and latches the contents in the latch circuit 33b. To do.

When a predetermined word line WL is selected, a predetermined memory cell M is formed by the selected column selection line CSL.
C is selected and the data in the memory cell MC is read. On the other hand, at the same time as this read operation, the next basic clock CLOCK is output, and each input register 20 receives and holds new address data A2 based on the new first clock A, and at the same time, the address is transferred via the level conversion circuit 21. Output to the decoder 22. Address decoder 22
While the new address data A2 is input, the data read operation of the memory cell MC is being performed. And
When a reset signal is output from the reset signal generation circuit based on the selection of a predetermined word line WL, the register circuit 33 is reset, all the word lines WL are in the non-selected state, and at the next second clock B. Wait for selection based. This reset signal resets the register circuit 41 of the main sense amplifier 40.

Register circuit 4 of main sense amplifier 40
When 1 is reset, the third sense clock C delayed from the second sense clock B by td2 time is input through the delay circuit 26 based on the second sense clock B to input the main sense amplifier 40.
Is activated, and the data of the memory cell MC based on the address data A1 is read out and amplified through a pre-sense amplifier or the like. Although the reset signal is output before the third clock C, the word line W is output based on the reset signal.
L is deselected at a timing sufficient for the main sense amplifier 40 to read the data due to the operation delay of the register circuit 33 and the like, and the data being held in the output register 50 described later.

When the main sense amplifier 40 is amplifying the data based on the address data A1, the operation of selecting and reading the memory cell MC based on the address data A2 based on the second clock B is the same as that described above. Has been done in. At this time, the first clock A is output, and new address data A3 is latched in the input register 20 and output to the address decoder 22.

When the memory cell MC is selected and read based on the address data A2 and the reset signal is output, the register circuit 41 of the main sense amplifier 40 is reset and the next third clock C is applied. The input of data of the memory cell MC based on the address data A2 is waited for.

Then, the third clock C and the fourth clock D delayed by td3 time from the preceding third clock C are output via the delay circuit 27 based on the preceding third clock C. Then, the main sense amplifier 40 is activated based on the new third clock C, and the output register 50 latches and outputs the data based on the address data A1 previously amplified by the main sense amplifier 40 based on the fourth clock D. Output to the buffer circuit 60. The output buffer circuit 60 outputs data based on this address data A1 as output data O1.

Based on the fourth clock D, the output register 50 and the output buffer circuit 60 cause the address data A1
The main sense amplifier 40 is amplifying the data (output data O2) of the memory cell MC based on the address data A2 while the output data O1 based on the output data O2 is output. At this time, the memory cell MC is selected and read based on the address data A3 based on the second clock B, and new address data A4 is latched in the input register 20 based on the first clock A and the address is read. The operation output to the decoder 22 is being performed.

Therefore, the output data O1 based on the address data A1 is read from the output buffer circuit 60 when four basic clocks CLOCK are output.
Address data A2, A3, A are sequentially transmitted in response to the fourth clock D output at the same cycle as the basic clock CLOCK.
Output data O2, O3, O4, etc. based on 4 etc. are output. Therefore, the conventional access time is the basic clock CL
Data corresponding to 3 cycles of OCK is read in 1/3 cycle of the access time.

As described above, in this embodiment, the first clock A is generated based on the basic clock CLOCK, and the second to fourth signals are output after being delayed with respect to the first clock A.
Clocks B, C, D are created, and address data is input to the address decoder 22 at the timing of the first clock A,
At the timing of the second clock B, the memory cell MC is selected and read based on the address data that has been input to the address decoder 22. At the timing of the third clock C, the selected and read memory cell M is read.
The data of C is amplified by the main amplifier 40, and the data amplified by the main amplifier 40 is output by the output register 50 and the output buffer circuit 60 at the timing of the fourth clock D. That is, since the memory cell MC is selected and read by the pipeline method, the next new address is input until the address data is input as in the conventional case and the data based on the address data is read from the output buffer circuit. The read speed is much faster than the data cannot be input and read.

Further, since the write processing operation is also an operation for selecting and writing the memory cell MC, the speed can be similarly increased as compared with the conventional case. Moreover, in this embodiment, the delay circuits 25 to 27 and 37 for generating the second to fourth clocks B to D and the reset signal can appropriately select the delay time of each signal by writing the contents in the fuse ROM 28. It is possible to accurately and surely set the operation timing at which each circuit unit operates reliably before shipping.

When the delay time is set, as shown in FIG.
The delay time detection circuit shown in FIG. 15 may be provided in the STRAM. That is, as shown in FIG. 13, the basic clock C
Four first inputs that input LOCK as a data signal Din
~ Fourth register circuits 61 to 64 are provided. Each of the register circuits 61 to 64 has two transfer gate circuits 65a and 65b and both gate circuits 65a and 65a, as shown in FIG.
The latch circuit 66 is provided between 65b. The first register circuit 61 outputs the first clock A and its inverted clock bar A, the second register circuit 62 outputs the second clock B and its inverted clock bar B, and the third register circuit 63 inverts the third clock C. The clock bar C, the fourth register circuit 64 outputs the fourth clock D and its inverted clock bar to the gates of the gate circuits 65a and 65b as control signals, respectively. Therefore, FIG.
When the basic clock CLOCK as shown in (1) is input, the clocks A to D output from the delay circuits 25 to 27 are output sequentially with a delay.

Each of the register circuits 61 to 64 outputs the latched values a to d based on the clocks A to D and the inverted clock bars A to D to the determination circuit 67 shown in FIG. The determination circuit 67 is a PMOS transistor Q91
To Q94, NMOS transistors Q95 to Q98, a NAND circuit 67, and an inverter circuit 68. Then, the value a from the first register circuit 61 and its inverted value bar a are used as a gate control signal for the fourth register circuit 6
The value d of 4 and its inverted value bar d are output to the NAND circuit 67. Further, the value b from the second register circuit 62 and its inverted value bar b are used as a gate control signal in the third register circuit 63.
The value c of c and its inverted value c are output to the NAND circuit 67. The inverter circuit 68 inputs the output of the NAND circuit 67 and outputs it as a detection signal. That is, the determination circuit 67 is expressed by the following logical expression, and its detection signal is shown in FIG. 1 for each clock a to d based on the basic clock CLOCK.
The waveform is as shown in FIG.

[0058]

[Equation 1]

Therefore, the time from the first rise to the fall of the detection signal is the delay time td1 of the second clock B, and the time from the fall to the next rise is the delay time td2 of the third clock C, The time from the rise to the next fall is the delay time td3 of the fourth clock C. As a result, it is possible to detect this detection signal externally and set each delay circuit to a more optimal delay time.

In the above embodiment, the address decoder 2
2 and the delay circuits 25 to 27 operate at the TTL level, the address data at the ECL level and the first clock A
Is converted to the TTL level by the level conversion circuits 21 and 24, but the TTL level address data and the first clock A may be input. In this case, the level conversion circuits 21 and 24 are unnecessary. At this time, input register 2
For example, 0 has a simple circuit configuration including a gate transistor Q51 formed of an NMOS transistor and a latch circuit 71 formed of two inverter circuits as shown in FIG.

In the above embodiment, the data amplified by the main sense amplifier 40 at the ECL level is directly used as the ECL.
Although the level is output via the output register 50 and the output buffer circuit 60, the ECL level data output from the main sense amplifier 40 may be converted to the TTL level and output. In this case, it is necessary to provide a level conversion circuit next to the main sense amplifier 40. Corresponding to this, as shown in FIG. 18, the output register 50 is an NMOS.
A gate transistor Q52 formed of a transistor and a latch circuit 72 formed of two inverter circuits are included, and the output buffer circuit 60 is formed of an inverter circuit 73 and two NMOS transistors Q53 and Q54.

Further, in the above embodiment, the delay circuits 25-2 are used.
Although the delay times of 7 and 37 are adjusted by the number of capacitor elements C connected between the respective inverter circuits INV as shown in FIG. 6, this is adjusted between the appropriate inverter circuits INV as shown in FIG. And the NMOS transistor Q55 is connected to the memories M1 and M
Inverter circuit INV controlled by 2 etc. and connected in series
The delay time may be set by adjusting the number of stages.

Further, in the reset signal generating circuit of the above-mentioned embodiment, the register circuit 33 is reset by the reset signal for all blocks, but the reset signal may be output only for the register in the selected block. .. That is, as shown in FIG. 20, the RS inputting the L level column selection signal of the NAND circuit 30 is input.
A flip-flop 75, an inverted output bar Q thereof, a NOR circuit 76 for inputting a reset start signal, and inverter circuits 77 for inputting the output of the NOR circuit 76 and outputting a reset signal to the reset PMOS transistor Q23 of the corresponding register circuit 33; You may comprise from. In this case, the reset start signal is a signal which falls after a predetermined time delay before the next second clock B is output with respect to the second clock B as shown in FIG. Is generated and output in.

That is, the selected block selection line BL
Based on S, the NAND circuit 30 corresponding to the block outputs a column selection signal. The flip-flop 75 is set based on this selection signal. Then, the reset signal is output via the inverter circuit 77 based on the reset start signal. The flip-flop 75 is reset based on this reset signal,
After that, even if the reset start signal is output, the reset signal is not output unless the block is selected. In addition,
As shown in FIG. 21B, the reset start signal is changed to the second
It may be outputted before the clock B. In this case, after the previously selected block is reset, the block is selected at the second clock B.

Furthermore, in the above embodiment, the input register 20 and the level conversion circuit 21 and the output register 50 and the output buffer circuit 60 are shown in FIG. In place of the register circuit 80 including the latch circuit 82 including the inverter circuit, the same register circuit 80 is replaced with the register circuits 33 and 41 illustrated in FIGS. 7 and 10 as illustrated in FIGS. 23 and 24. You may. The corresponding first clocks A to D are input to the NMOS transistors of the transfer gate 81, and the first clocks A to D are input to the PMOS transistors.
Inverted signal bars A to D are input.

The global word line GWL in FIG. 23 is selected at the H level, and the inverter circuit 88 is connected instead of the NAND circuit 30. Then, it is connected to the register 80 via the NAND circuit 89 which inputs the control signal from the NOR circuits 31 and 32 and the selection signal of the global word line GWL. Further, the inverter circuit 90 is an inverter circuit that produces an inverted signal bar B of the second clock B.

With this structure as well, a high-speed reading operation can be realized as in the above embodiment. Further, in this case, as shown in FIG. 23, the activation signal of the H level is set so that the basic clock CLOCK is invalidated to the chopper circuit 23 based on the mode control signal so that the transfer gate 81 of each register 80 is always turned on. It is also possible to provide a mode selection circuit 91 for outputting. With this configuration,
If the activation signal is output from the chopper circuit 23, it can be used as an SRAM that operates with a normal access time that is not a pipeline method. As a result, the application can be expanded.

[0068]

As described above in detail, according to the present invention, the speed of the STRAM can be increased with a simple structure, and there is an excellent effect as a semiconductor memory device.

[Brief description of drawings]

FIG. 1 is an explanatory diagram illustrating the principle of the present invention.

FIG. 2 is a block circuit diagram of a main part of a STRAM.

FIG. 3 is a circuit diagram of an input register.

FIG. 4 is a level conversion circuit diagram.

FIG. 5 is a timing waveform chart of first to fourth clocks.

FIG. 6 is a delay circuit diagram.

FIG. 7 is a circuit diagram showing a wiring between an address decoder and a memory cell.

FIG. 8 is a circuit diagram of a register.

FIG. 9 is a reset signal generation circuit diagram.

FIG. 10 is a circuit diagram of a main amplifier.

FIG. 11 is a circuit diagram of an output register and an output buffer circuit.

FIG. 12 is a waveform chart of each output timing with respect to a clock.

FIG. 13 is a circuit diagram of a delay time detection circuit.

FIG. 14 is a register circuit diagram provided in a delay time detection circuit.

FIG. 15 is a determination circuit diagram provided in a delay time detection circuit.

FIG. 16 is an output waveform diagram of the delay time detection circuit.

FIG. 17 is a circuit diagram of an input register of another embodiment.

FIG. 18 is a circuit diagram of an output register of another embodiment.

FIG. 19 is a delay circuit diagram of another embodiment.

FIG. 20 is a reset signal generation circuit diagram according to another embodiment.

FIG. 21 is a timing waveform chart of a reset start signal.

FIG. 22 is a register circuit diagram of another embodiment.

FIG. 23 is a circuit diagram showing a register of another embodiment.

FIG. 24 is a main part circuit diagram of a main sense amplifier of another embodiment.

[Explanation of symbols]

 1 Address Decoder Circuit Section 2 Input Register Circuit 3 Selection Register Circuit 4 Memory Cell Array Circuit Section 5 Main Sense Amplifier Circuit Section 6 Drive Register Circuit 7 Output Register Circuit 8 Data Output Circuit Section 9 Synchronization Signal Generation Circuit 23 Activation Signal Generation Circuit 91 Selection Circuit CLOCK Basic clock signal A to D First to fourth clock signals

Claims (2)

[Claims] 1. An address decoder circuit section (1) for inputting address data, a memory cell array circuit section (4) in which a predetermined memory cell is selected by the decoder circuit section (1), and the selected memory. In a semiconductor memory device comprising a main sense amplifier circuit section (5) for amplifying cell data and a data output circuit section (8) for outputting data amplified by the main sense amplifier circuit section (5), a basic clock A synchronization signal generation circuit (9) which outputs first to fourth clock signals (A to D) generated based on a signal (CLOCK) and sequentially delayed and output; and an address decoder circuit unit (1). It is installed in the front stage,
An input register circuit (2) which operates in response to a first clock signal (A) and holds address data, is provided between the decoder circuit unit (1) and the memory cell array circuit unit (4), A selection register circuit (3) which operates in lag behind the input register circuit (2) and holds a selection signal in response to a two-clock signal (B); and a main sense amplifier circuit section (5).
A drive register circuit (6) which operates in response to a clock signal (C) later than the selection register circuit (3) and activates a main sense amplifier circuit section (5); and the main sense amplifier circuit section (5). Is provided between the main sense amplifier circuit section (5) and the data output circuit section (8), and operates later than the main sense amplifier circuit section (5) in response to the fourth clock signal (D). And a output register circuit (7) for holding data. 2. A synchronization signal generation circuit (9) for outputting first to fourth clock signals (A to D) generated based on a basic clock signal (CLOCK) and sequentially delayed and output, and the address. It is provided in the preceding stage of the decoder circuit section (1),
An input register circuit (2) which operates in response to a first clock signal (A) and holds address data, is provided between the decoder circuit unit (1) and the memory cell array circuit unit (4), A selection register circuit (3) which operates in lag behind the input register circuit (2) and holds a selection signal in response to a two-clock signal (B); and a main sense amplifier circuit section (5).
A drive register circuit (6) which operates in response to a clock signal (C) later than the selection register circuit (3) and activates a main sense amplifier circuit section (5); and the main sense amplifier circuit section (5). Is provided between the main sense amplifier circuit section (5) and the data output circuit section (8), and operates later than the main sense amplifier circuit section (5) in response to the fourth clock signal (D). In the semiconductor memory device having an output register circuit (7) for holding data, the register circuits (2, 3, 6, 7) are output to the register circuits (2, 3, 6, 7). Activation signal generation circuit (23) that outputs activation signals to activate all at once
And selecting either the activation signal generation circuit (23) or the synchronization signal generation circuit (9) to cause each register circuit to output either the activation signal or the clock signal (A to D). A semiconductor memory device comprising a selection circuit (91).