KR100801032B1 - Input circuit of a non-volatile semiconductor memory device and method of inputting data of the same - Google Patents

Abstract

An input circuit of a non-volatile semiconductor memory device and a method of inputting data of the same are provided to buffer an input signal with small swing width safely, as trimming a reference voltage and/or a clock signal. A memory cell array comprises a plurality of memory transistors. An input circuit(1000) controls voltage level of an internal reference voltage and/or delay time of an internal clock signal in response to an MRS(Mode Register Set) trim code and/or an electrical fuse trim code, and generates a first buffered input signal. A column gate gates the buffered input signal in response to a decoded column address signal. A sense amplifier amplifies an output signal of the memory cell array and then provides the amplified output signal to the column gate, and receives an output signal of the column gate and then provides the received output signal to the memory cell array.

Description

Input circuit of nonvolatile semiconductor memory device and data input method of nonvolatile semiconductor memory device {INPUT CIRCUIT OF A NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF INPUTTING DATA OF THE SAME}

1 is a circuit diagram illustrating an input circuit of a conventional nonvolatile semiconductor memory device.

2 is a block diagram illustrating an input circuit of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

3 is a circuit diagram illustrating an example of an input buffer included in an input circuit of the nonvolatile semiconductor memory device shown in FIG. 2.

4 is a circuit diagram illustrating an example of a sampler included in an input circuit of the nonvolatile semiconductor memory device shown in FIG. 2.

FIG. 5 is a circuit diagram illustrating an example of a reference voltage generation circuit included in an input circuit of the nonvolatile semiconductor memory device shown in FIG. 2.

FIG. 6 is a circuit diagram illustrating an example of an internal clock signal generation circuit included in an input circuit of the nonvolatile semiconductor memory device shown in FIG. 2.

FIG. 7 is a circuit diagram illustrating a delay line and a multiplexer included in the internal clock signal generation circuit illustrated in FIG. 6.

8 is a block diagram illustrating an input circuit of a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

FIG. 9 is a circuit diagram illustrating an example of a reference voltage generation circuit included in an input circuit of the nonvolatile semiconductor memory device shown in FIG. 8.

10 is a block diagram illustrating an input circuit of a nonvolatile semiconductor memory device according to a third embodiment of the present invention.

FIG. 11 is a circuit diagram illustrating an example of an input buffer included in an input circuit of the nonvolatile semiconductor memory device shown in FIG. 10.

12 is a block diagram illustrating an input circuit of a nonvolatile semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 13 is a block diagram illustrating a trim code generation circuit for generating trim codes used in a reference voltage generation circuit and an internal clock signal generation circuit included in embodiments of the present invention.

FIG. 14 is a block diagram illustrating an MRS logic circuit for generating MRS control signals used in the trim code generation circuit illustrated in FIG. 13.

15A is a diagram illustrating a reference voltage trimming range for an input signal, and FIG. 15B is a diagram illustrating a sampling clock trimming range for an input signal.

16A, 16B, and 16C are flowcharts illustrating a trimming method of a reference voltage and an internal clock signal.

17 is a block diagram illustrating an example of a nonvolatile semiconductor memory device including an input circuit according to embodiments of the present invention.

Explanation of symbols on the main parts of the drawings

1000, 2000, 3000, 4000: input circuit

1100, 1600: input buffer

1200: sampler

1300, 1500: reference voltage generator

1310, 1420, 1430: Multiplexer

1320: reference voltage generator

1400: internal clock signal generation circuit

1410: delay line

5000: Trim code generating circuit

5100: MRS logic circuit

6000: Nonvolatile Semiconductor Memory Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to an input circuit and a method of inputting a nonvolatile semiconductor memory device.

Conventionally, nonvolatile semiconductor memory devices such as flash memory devices use a low voltage complementary metal oxide semiconductor (LVCMOS) interface including a NOR gate or a NAND gate because the write speed is not so fast.

1 is a circuit diagram illustrating an input circuit of a conventional nonvolatile semiconductor memory device. Referring to FIG. 1, an input circuit of a nonvolatile semiconductor memory device includes an input buffer 10, a clock buffer 20, and a sampler 30. The input buffer 10 includes a NOR gate 11 and inverters 13, 15, and 17, and the clock buffer 20 includes a NOR gate 21 and inverters 23, 25, 27. The sampler 30 includes a D flip-flop 31 and inverters 33 and 35. The input buffer 10 buffers the input signal IN in response to the enable signal EN, and the clock buffer 20 buffers the clock signal CLK in response to the clock enable signal CLK_EN. The sampler 30 samples the output signal of the input buffer 10 in response to the output signal of the clock buffer 20 and generates a buffer output signal BOUT.

In the past, since the write operation of most nonvolatile semiconductor memory devices was not fast, the LVCMOS interface circuit shown in FIG. 1 was used to convert the CMOS signal into an internal circuit.

However, as the transmission speed of the signal on the system bus increases, the swing width of the signal transmitted between the chips connected to the bus decreases and the setup / hold margin of the signal decreases. Therefore, it is difficult to safely buffer the input signal with the conventional input circuit as shown in FIG.

Therefore, there is a need for an input circuit capable of safely buffering an input signal having a small swing width.

SUMMARY OF THE INVENTION An object of the present invention is to provide a nonvolatile semiconductor memory device including an input circuit capable of trimming a reference voltage and / or a clock signal and safely buffering an input signal having a small swing width.

Another object of the present invention is to provide a data input method of a nonvolatile semiconductor memory device capable of trimming a reference voltage and / or a clock signal and safely buffering an input signal having a small swing width.

In order to achieve the above object, a nonvolatile semiconductor memory device according to one embodiment of the present invention includes a memory cell array composed of a plurality of memory transistors, an input circuit, a column gate, and a sense amplifier.

The input circuit may adjust the voltage level of the internal reference voltage and / or the delay time of the internal clock signal in response to the MRS trim code and / or the electrical fuse trim code and generate a first buffered input signal. The column gate gates the buffered input signal in response to the decoded column address signal. The sense amplifier amplifies an output signal of the memory cell array and provides it to the column gate, and receives an output signal of the column gate and provides it to the memory cell array.

According to one embodiment of the invention, the input circuit comprises a reference voltage generator circuit, an internal clock signal generator circuit, an input buffer, and a sampler.

The reference voltage generating circuit generates the internal reference voltage in response to the first MRS trim code and the first electrical fuse trim code. The internal clock signal generation circuit generates the internal clock signal in response to a second MRS trim code and a second electrical fuse trim code. The input buffer buffers an input signal in response to the internal reference voltage and generates a second buffered input signal. A sampler samples the second buffered input signal in response to the internal clock signal and generates the first buffered input signal.

A data input method of a nonvolatile semiconductor memory device according to an embodiment of the present invention includes generating an internal reference voltage in response to a first MRS trim code and a first electric fuse trim code; Generating an internal clock signal in response to the second MRS trim code and the second electrical fuse trim code; Buffering an input signal in response to the internal reference voltage and generating a first buffered input signal; And sampling the second buffered input signal in response to the internal clock signal and generating a first buffered input signal.

With respect to the embodiments of the present invention disclosed in the text, specific structural to functional descriptions are merely illustrated for the purpose of describing embodiments of the present invention, embodiments of the present invention may be implemented in various forms and It should not be construed as limited to the embodiments described in.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific disclosure form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between. Other expressions describing the relationship between components, such as "between" and "immediately between," or "neighboring to," and "directly neighboring to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "having" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is described, and that one or more other features or numbers are present. It should be understood that it does not exclude in advance the possibility of the presence or addition of steps, actions, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

On the other hand, when an embodiment is otherwise implemented, a function or operation specified in a specific block may occur out of the order specified in the flowchart. For example, two consecutive blocks may actually be performed substantially simultaneously, and the blocks may be performed upside down depending on the function or operation involved.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

2 is a block diagram illustrating an input circuit of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

Referring to FIG. 2, the input circuit 1000 includes a reference voltage generation circuit 1300, an internal clock signal generation circuit 1400, an input buffer 1100, and a sampler 1200.

The reference voltage generator 1300 generates an internal reference voltage VREF in response to the first MRS trim code MRS1 and the first electric fuse trim code EFUSE1. The internal clock signal generation circuit 1400 generates the internal clock signal ICLK in response to the second MRS trim code MRS2 and the second electric fuse trim code EFUSE2. The input buffer 1100 buffers the input signal IN and generates a first buffered input signal BIN in response to the internal reference voltage VREF and the enable signal EN. The sampler 1200 samples the first buffered input signal BIN in response to the internal clock signal ICLK and generates a second buffered input signal BOUT.

3 is a circuit diagram illustrating an example of an input buffer 1100 included in an input circuit 1000 of the nonvolatile semiconductor memory device illustrated in FIG. 2.

Referring to FIG. 3, the input buffer 1100 includes a differential amplifier 1110 and a buffer 1120. The differential amplifier 1110 generates a differential amplified signal by amplifying a difference between the input signal IN and the internal reference voltage VREF. The buffer 1120 buffers the differential amplified signal, which is an output signal of the differential amplifier 1110, and generates a first buffered input signal BIN.

The differential amplifier 1110 includes a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, a second NMOS transistor MN2, and a third NMOS transistor MN3.

The first PMOS transistor MP1 has a source coupled to the power supply voltage VDD, and a gate and a drain coupled to the first node N1. The second PMOS transistor MP2 has a source coupled to the power supply voltage VDD, a gate coupled to the first node N1, and a drain coupled to the second node N2. The first NMOS transistor MN1 has a gate to which the input signal IN is applied, a drain coupled to the first node N1, and a source coupled to the third node N3. The second NMOS transistor MN2 has a gate to which the internal reference voltage VREF is applied, a drain coupled to the second node N2, and a source coupled to the third node N3. The third NMOS transistor MN3 has a gate coupled to the first node N1 and a drain coupled to the third node N3. The fourth NMOS transistor MN4 has a gate to which the enable signal EN is applied, a drain coupled to the source of the third NMOS transistor MN3, and a source coupled to the ground voltage VSS.

The buffer 1120 includes a first inverter 1121 and a second inverter 1123.

4 is a circuit diagram illustrating an example of a sampler 1200 included in an input circuit 1000 of the nonvolatile semiconductor memory device illustrated in FIG. 2.

Referring to FIG. 4, the sampler 1200 includes a D flip-flop 1210 and a buffer 1220. The D-type flip-flop 1210 latches the first buffered input signal BIN in response to the internal clock signal ICLK. The buffer 1220 buffers the output signal of the D flip-flop 1210 and includes inverters 1221 and 1223. Although FIG. 4 shows a buffer 1220 consisting of two inverters, the buffer 1220 may comprise any even number of inverters.

FIG. 5 is a circuit diagram illustrating an example of a reference voltage generation circuit 1300 included in the input circuit 1000 of the nonvolatile semiconductor memory device shown in FIG. 2.

Referring to FIG. 5, the reference voltage generator 1300 includes a multiplexer 1310 and a reference voltage generator 1320. The multiplexer 1310 selects one of the first MRS trim code MRS1 and the first electric fuse trim code EFUSE1 in response to the first trim control signal MRS_VREF_TRIM, and outputs a first trim code TRIM_CODE1. The reference voltage generator 1320 generates the internal reference voltage VREF having a voltage level that changes in response to the first trim code TRIM_CODE1.

FIG. 6 is a circuit diagram illustrating an example of an internal clock signal generation circuit 1400 included in the input circuit 1000 of the nonvolatile semiconductor memory device illustrated in FIG. 2.

Referring to FIG. 6, the internal clock signal generation circuit 1400 includes a delay line 1410, a first multiplexer 1430, and a second multiplexer 1420.

The delay line 1410 delays the external clock signal CLK and generates a plurality of delay clock signals DCLK. The first multiplexer 1430 selects one of the second MRS trim code MRS2 and the second electric fuse trim code EFUSE2 in response to the second trim control signal MRS_CLK_TRIM, and outputs the second trim code TRIM_CODE2. do. The second multiplexer 1420 selects one of the plurality of delayed clock signals DCLK in response to the second trim code TRIM_CODE2 to generate the internal clock signal ICLK.

FIG. 7 is a circuit diagram illustrating a delay line 1410 and a multiplexer 1420 included in the internal clock signal generation circuit 1400 of FIG. 6.

Referring to FIG. 7, the delay lines 1410 are cascaded to each other and include a plurality of unit delay cells for delaying a unit delay time of a cell input signal. The delay line 1410 includes a first unit delay cell 1411, a second unit delay cell 1412, a third unit delay cell 1413, and a fourth unit delay cell 1414.

The first unit delay cell 1411 delays the external clock signal CLK by a unit delay time and generates the first delay clock signal DCLK1. The second unit delay cell 1412 delays the first delay clock signal DCLK1 by a unit delay time and generates a second delay clock signal DCLK2. The third unit delay cell 1413 delays the second delayed clock signal DCLK2 by a unit delay time and generates a third delayed clock signal DCLK3. The fourth unit delay cell 1414 delays the third delayed clock signal DCLK3 by a unit delay time and generates a fourth delayed clock signal DCLK4.

The second multiplexer 1420 may receive the first delayed clock signal DCLK1, the second delayed clock signal DCLK2, the third delayed clock signal DCLK3, and the fourth delayed clock signal in response to the second trim code TRIM_CODE2. One of DCLK4) is selected to generate an internal clock signal ICLK.

Hereinafter, an operation of an input circuit of a nonvolatile semiconductor memory device according to an embodiment of the present invention will be described with reference to FIGS. 1 to 7.

The input circuit 1000 shown in FIG. 1 uses a first MRS trim code MRS1, a first electric fuse trim code EFUSE1, a second MRS trim code MRS2, and a second electric fuse trim code EFUSE1. The trimming range of the internal reference voltage VREF and the trimming range of the sampling clock can be adjusted. Accordingly, the input circuit 1000 may interface data in a high speed memory system.

8 is a block diagram illustrating an input circuit of a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

Referring to FIG. 8, the input circuit 2000 includes a reference voltage generator 1500, an internal clock signal generator 1400, an input buffer 1100, and a sampler 1200.

The reference voltage generator 1500 generates the internal reference voltage VREF in response to the first MRS trim code MRS1, the first electric fuse trim code EFUSE1, and the external reference voltage EVREF. The internal clock signal generation circuit 1400 generates the internal clock signal ICLK in response to the second MRS trim code MRS2 and the second electric fuse trim code EFUSE2. The input buffer 1100 buffers the input signal IN and generates the first buffered input signal BIN in response to the internal reference voltage VREF and the enable signal EN. The sampler 1200 samples the first buffered input signal BIN in response to the internal clock signal ICLK and generates a second buffered input signal BOUT.

FIG. 9 is a circuit diagram illustrating an example of a reference voltage generation circuit 1500 included in the input circuit 2000 of the nonvolatile semiconductor memory device shown in FIG. 8.

Referring to FIG. 9, the reference voltage generator 1500 includes a first multiplexer 1310, a reference voltage generator 1320, and a second multiplexer 1330. The first multiplexer 1310 selects one of the first MRS trim code MRS1 and the first electric fuse trim code EFUSE1 in response to the first trim control signal MRS_VREF_TRIM to output the first trim code TRIM_CODE1. do. The reference voltage generator 1320 generates the internal reference voltage VREF having a voltage level that changes in response to the first trim code TRIM_CODE1. The second multiplexer 1330 selects one of an external reference voltage EVREF and a first reference voltage IVREF and generates an internal reference voltage VREF in response to the reference voltage selection signal VREF_SEL.

The internal clock signal generation circuit 1400, the input buffer 1100, and the sampler 1200 included in the input circuit 2000 illustrated in FIG. 8 may include the input circuit according to the first embodiment of the present invention illustrated in FIG. 2. The internal clock signal generation circuit 1400, the input buffer 1100, and the sampler 1200 included in 1000 have the same configuration.

In the input circuit 2000 illustrated in FIG. 8, the reference voltage generation circuit 1500 may selectively use the reference voltage generated by the external reference voltage EVREF and the reference voltage generation circuit 1500.

10 is a block diagram illustrating an input circuit 3000 of a nonvolatile semiconductor memory device according to a third embodiment of the present invention.

Referring to FIG. 10, the input circuit 3000 includes an internal clock signal generation circuit 1400, an input buffer 1600, and a sampler 1200.

The internal clock signal generation circuit 1400 generates the internal clock signal ICLK in response to the second MRS trim code MRS2 and the second electric fuse trim code EFUSE2. The input buffer 1100 is turned on or off in response to the enable signal EN, buffers the input signal IN, and generates a first buffered input signal BIN. The sampler 1200 samples the first buffered input signal BIN in response to the internal clock signal ICLK and generates a second buffered input signal BOUT.

FIG. 11 is a circuit diagram illustrating an example of an input buffer 1600 included in an input circuit 3000 of the nonvolatile semiconductor memory device illustrated in FIG. 10.

Referring to FIG. 11, the input buffer 1600 includes a buffer composed of a NOR gate 1610 and inverters 1620, 1630, and 1640. The NOR gate 1610 performs an illogical sum operation on the input signal IN and the enable signal EN. A buffer composed of inverters 1620, 1630, 1640 buffers the output signal of the NOR gate 1610.

The internal clock signal generation circuit 1400, the input buffer 1100, and the sampler 1200 included in the input circuit 3000 shown in FIG. 10 are the input circuit according to the first embodiment of the present invention shown in FIG. 2. The internal clock signal generation circuit 1400, the input buffer 1100, and the sampler 1200 included in 1000 have the same configuration.

The input circuit 3000 illustrated in FIG. 10 determines the trimming range by adjusting the delay time of the internal clock signal ICLK using only the internal clock signal generation circuit 1400 without using the reference voltage generation circuit 1500. . As illustrated in FIG. 11, the input buffer 1100 included in the input circuit 3000 shown in FIG. 10 is buffered without using an internal reference voltage.

12 is a block diagram illustrating an input circuit 4000 of a nonvolatile semiconductor memory device according to a fourth embodiment of the present invention.

Referring to FIG. 12, the input circuit 4000 includes a reference voltage generation circuit 1300, an input buffer 1100, and a sampler 1200.

The reference voltage generator 1300 generates an internal reference voltage VREF in response to the first MRS trim code MRS1 and the first electric fuse trim code EFUSE1. The input buffer 1100 buffers the input signal IN and generates the first buffered input signal BIN in response to the internal reference voltage VREF and the enable signal EN. The sampler 1200 samples the first buffered input signal BIN in response to the clock signal CLK and generates a second buffered input signal BOUT. The clock signal CLK in FIG. 12 may be an external clock signal input from an external of the nonvolatile semiconductor memory device.

The reference voltage generating circuit 1300, the input buffer 1100, and the sampler 1200 included in the input circuit 4000 illustrated in FIG. 12 are connected to the input circuit according to the first embodiment of the present invention illustrated in FIG. 2. The reference voltage generating circuit 1300, the input buffer 1100, and the sampler 1200 included in the 1000 have the same configuration.

The input circuit 4000 illustrated in FIG. 12 determines the trimming range by adjusting the delay time of the internal reference voltage VREF using only the reference voltage generation circuit 1500 without using the internal clock signal generation circuit 1400. .

FIG. 13 is a block diagram illustrating a trim code generator circuit 5000 that generates trim codes used in a reference voltage generator circuit and an internal clock signal generator circuit included in embodiments of the present invention.

Referring to FIG. 13, the trim code generation circuit 5000 may include a decoder 5010, a first register 5050, a second register 5040, a word line driver circuit 5030, a sense amplifier 5060, and a third register. 5070, a multiplexer 5080, and a nonvolatile semiconductor memory cell 5020.

The decoder 5010 decodes the MRS trim update signal MRS_TRIM_UPDATE. The first register 5050 stores the MRS trim code MRS_TRIM_CODE and outputs an MRS trim code MRS_TRIM_CODE in response to the MRS trim enable signal MRS_TRIM_EN. The second register 5040 stores the MRS trim code MRS_TRIM_CODE and outputs an MRS trim code MRS_TRIM_CODE in response to the trim update signal MRS_TRIM_UPDATE. The word line driver circuit 5030 provides the MRS trim code MRS_TRIM_CODE to the nonvolatile semiconductor memory cell 5020 in response to the MRS trim update signal MRS_TRIM_UPDATE. The sense amplifier 5060 generates the first data by amplifying the first voltage signal corresponding to the MRS dream code MRS_TRIM_CODE from the nonvolatile semiconductor memory cell 5020. The third register 5070 stores the first data and generates an electric fuse trim code EFUSE_TRIM_CODE. The multiplexer 5080 selects one of the MRS trim code MRS_TRIM_CODE and the electric fuse trim code EFUSE_TRIM_CODE in response to the MRS trim enable signal MRS_TRIM_EN to generate a trim code TRIM_CODE. In FIG. 13, the multiplexer 5080 is a multiplexer corresponding to the multiplexer 1310 of FIG. 5, the multiplexer 1430 of FIG. 6, and the multiplexer 1310 of FIG. 9.

FIG. 14 illustrates an MRS logic enable signal 5100 that generates an MRS trim enable signal MRS_TRIM_EN, an MRS trim update signal MRS_TRIM_UPDATE, and an MRS trim code MRS_TRIM_CODE used in the trim code generation circuit shown in FIG. 13. The MRS logic circuit 5100 generates an MRS trim enable signal MRS_TRIM_EN, an MRS trim update signal MRS_TRIM_UPDATE, and an MRS trim code MRS_TRIM_CODE in response to the command signals CMD.

15A is a diagram illustrating a reference voltage trimming range for an input signal, and FIG. 15B is a diagram illustrating a sampling clock trimming range for an input signal.

Referring to FIG. 15A, the trimming range of the internal reference voltage VREF includes the minimum value VIH_MIN of the "high" level of the input signal DIN and the maximum value of the "low" level of the input signal DIN ( VIL_MAX). Referring to FIG. 15B, the trimming range of the internal clock signal ICLK, that is, the sampling clock may be set to include a setup / hold window of the input signal DIN.

16A, 16B, and 16C are flowcharts illustrating a trimming method of a reference voltage and an internal clock signal.

Referring to FIG. 16A, the trimming method of the reference voltage and the internal clock signal includes setting an input buffer trimming mode (S1), and proceeds to A if the input buffer trimming mode is trimming of the internal reference voltage VREF. If the input buffer trimming mode is trimming the internal clock signal ICLK, the process proceeds to B.

Referring to FIG. 16B, the generating of the internal reference voltage may include trimming the internal reference voltage (S2); Receiving input data (S3); Determining whether correct input data has been received (S4); If the received input data is not correct input data, going to trimming the internal reference voltage; If the received input data is a correct input signal, storing a final trim code in a register (S5); And writing the final trim code to the nonvolatile semiconductor memory cell (S6).

Referring to FIG. 16C, the generating of the internal clock signal ICLK may include trimming the internal clock signal ICLK (S7); Receiving the input data (S8); Determining whether correct input data has been received (S9); If the received input data is not correct input data, going to trimming the internal clock signal; If the received input data is a correct input signal, storing a final trim code in a register (S10); And writing the final trim code to the nonvolatile semiconductor memory cell (S11).

The input data in FIGS. 16B and 16C are signals corresponding to the input signals shown in FIGS. 2 to 12.

17 is a block diagram illustrating an example of a nonvolatile semiconductor memory device including an input circuit according to example embodiments.

Referring to FIG. 17, the nonvolatile semiconductor memory device 6000 may include a program control circuit 6100, a high voltage generation circuit 6200, a row decoder 6300, and a memory cell array 6700.

The memory cell array 6700 is composed of a plurality of memory transistors. The high voltage generation circuit 6200 generates a program voltage signal VPGM, a pass voltage signal VPASS, and a boost voltage signal VPP. The program control circuit 6100 may receive a program voltage enable signal VPGM_EN, a pass voltage enable signal VPASS_EN, and a drop pass voltage enable signal DVPASS_EN in response to the command signal CMD and the row address signal X_ADDR. Generates. The row decoder 6300 generates the first program voltage signal VPGM1, the first pass voltage signal VPASS1, and the second pass voltage signal VPASS2. The first pass voltage signal VPASS1 transitions to the voltage level of the pass voltage signal VPASS in response to the pass voltage enable signal VPASS_EN. The second pass voltage signal VPASS2 has a voltage level of the falling pass voltage signal VPASSD before the program voltage enable signal VPGM_EN is activated, and after the program enable signal VPGM_EN is activated, the pass voltage signal VPASS. ) Has a voltage level of. The first program voltage signal VPGM1, the first pass voltage signal VPASS1, and the second voltage signal VPASS2 are provided to word lines coupled to the memory cell array 6700.

The nonvolatile semiconductor memory device 6000 may further include an address buffer 6800, a column decoder 6400, a column gate 6500, and a sense amplifier 6600.

The address buffer 6800 buffers the address ADDR and generates a row address X_ADDR and a column address Y_ADDR. The column decoder 6400 decodes the column address Y_ADDR and generates a decoded column address. The column gate 6500 gates first data received from the outside in response to the decoded column address and gates second data output to the outside. The sense amplifier 6600 may amplify the output data of the memory cell array 6700 and provide it to the column gate 6500, and receive and output the output data of the column gate 6500 to the memory cell array 6700.

In addition, the nonvolatile semiconductor memory device 6000 may include an input circuit that receives and buffers an input signal IN received from the outside, generates a command CMD, an address ADDR, and data and provides the same to an internal circuit. In addition, the nonvolatile semiconductor memory device 6000 further includes an output circuit that receives data from an internal circuit, buffers the data, and outputs the data to the outside.

The input circuit 6900 included in the nonvolatile semiconductor memory device 6000 illustrated in FIG. 17 may use the input circuits according to the first to fourth embodiments.

As described above, the input circuit included in the nonvolatile semiconductor memory device 6000 according to the present invention can trim a reference voltage and / or a clock signal, and can safely buffer an input signal having a small swing width. In addition, in a system for high-speed data transfer, an external circuit and an internal circuit of the nonvolatile semiconductor memory device may be interfaced, and a standby current may be reduced.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (30)

A memory cell array composed of a plurality of memory transistors; An input circuit configured to adjust a voltage level of an internal reference voltage and / or a delay time of an internal clock signal in response to the MRS trim code and / or the electric fuse trim code, and generate a first buffered input signal; A column gate gating the buffered input signal in response to a decoded column address signal; And And a sense amplifier configured to amplify an output signal of the memory cell array to the column gate and to receive the output signal of the column gate to provide the output signal to the memory cell array. The method of claim 1, wherein the input circuit A reference voltage generation circuit for generating the internal reference voltage in response to a first MRS trim code and a first electrical fuse trim code; An internal clock signal generation circuit configured to generate the internal clock signal in response to a second MRS trim code and a second electrical fuse trim code; An input buffer configured to buffer an input signal and generate a second buffered input signal in response to the internal reference voltage; And And a sampler sampling the second buffered input signal in response to the internal clock signal and generating the first buffered input signal. The method of claim 2, wherein the input buffer is Non-volatile semiconductor memory device, characterized in that turned off in response to the enable signal. The method of claim 3, wherein the input buffer A differential amplifier for generating a differential amplified signal by amplifying a difference between the input signal and the internal reference voltage; And And a buffer for buffering the differential amplified signal. The method of claim 4, wherein the differential amplifier A first PMOS transistor having a source coupled to a power supply voltage and a gate and a drain coupled to the first node; A second PMOS transistor having a source coupled to the power supply voltage, a gate coupled to the first node, and a drain coupled to a second node; A first NMOS transistor having a gate to which the input signal is applied, a drain coupled to the first node, and a source coupled to a third node; A second NMOS transistor having a gate to which the internal reference voltage is applied, a drain coupled to the second node, and a source coupled to the third node; A third NMOS transistor having a gate coupled to the first node and a drain coupled to the third node; And And a fourth NMOS transistor having a gate coupled to the enable signal, a drain coupled to a source of the third NMOS transistor, and a source coupled to a ground voltage. The method of claim 4 wherein the buffer is A nonvolatile semiconductor memory device comprising an even number of inverters. The method of claim 2, wherein the sampler A D-type flip-flop for latching the second buffered input signal in response to the internal clock signal; And And a buffer for buffering the output signal of the D flip-flop. The method of claim 2, wherein the reference voltage generating circuit A multiplexer for selecting one of the first MRS trim code and the first electric fuse trim code in response to a first trim control signal to output a first trim code; And And a reference voltage generator configured to generate the internal reference voltage having a voltage level that changes in response to the first trim code. The circuit of claim 2, wherein the internal clock signal generation circuit comprises: A delay line for delaying an external clock signal and generating a plurality of delayed clock signals; A first multiplexer for selecting one of the second MRS trim code and the second electrical fuse trim code in response to a second trim control signal to output a second trim code; And And a second multiplexer for selecting one of the plurality of delayed clock signals in response to the second trim code to generate the internal clock signal. The method of claim 9, wherein the delay line is And a plurality of unit delay cells cascaded to each other and configured to delay a unit delay time of the cell input signal. The method of claim 10, wherein the delay line A first unit delay cell delaying the external clock signal to the unit delay time and generating a first delay clock signal; A second unit delay cell delaying the first delay clock signal to the unit delay time and generating a second delay clock signal; A third unit delay cell delaying the second delay clock signal to the unit delay time and generating a third delay clock signal; And And a fourth unit delay cell for delaying the third delayed clock signal by the unit delay time and generating a fourth delayed clock signal. The method of claim 1, wherein the input circuit A reference voltage generation circuit configured to generate the internal reference voltage in response to a first MRS trim code, a first electric fuse trim code, and an external reference voltage; An internal clock signal generation circuit configured to generate an internal clock signal in response to the second MRS trim code and the second electrical fuse trim code; An input buffer configured to buffer an input signal and generate a second buffered input signal in response to the internal reference voltage; And And a sampler sampling the second buffered input signal in response to the internal clock signal and generating the first buffered input signal. The method of claim 12, wherein the input buffer is Non-volatile semiconductor memory device, characterized in that turned off in response to the enable signal. The method of claim 13, wherein the sampler is A D-type flip-flop for latching the second buffered input signal in response to the internal clock signal; And And a buffer for buffering the output signal of the D flip-flop. The circuit of claim 13, wherein the reference voltage generation circuit is A first multiplexer configured to select one of the first MRS trim code and the first electric fuse trim code in response to a first trim control signal to output a first trim code; A reference voltage generator configured to generate a first reference voltage having a voltage level that changes in response to the first trim code; And  And a second multiplexer configured to select one of the external reference voltage and the first reference voltage and generate the internal reference voltage in response to a reference voltage selection signal. 14. The circuit of claim 13, wherein the internal clock signal generation circuit A delay line for delaying an external clock signal and generating a plurality of delayed clock signals; A first multiplexer for selecting one of the second MRS trim code and the second electrical fuse trim code in response to a second trim control signal to output a second trim code; And And a second multiplexer for selecting one of the plurality of delayed clock signals in response to the second trim code to generate the internal clock signal. The method of claim 1, wherein the input circuit An internal clock signal generation circuit configured to generate the internal clock signal in response to an MRS trim code and an electric fuse trim code; An input buffer for buffering the input signal and generating a second buffered input signal; And And a sampler sampling the second buffered input signal in response to the internal clock signal and generating the first buffered input signal. 18. The system of claim 17, wherein the input buffer is Non-volatile semiconductor memory device, characterized in that turned off in response to the enable signal. 19. The apparatus of claim 18, wherein the input buffer is A NOR gate performing an illogical sum operation on the input signal and the enable signal; And And a buffer for buffering the output signal of the NOR gate. 19. The circuit of claim 18, wherein the internal clock signal generation circuit A delay line for delaying an external clock signal and generating a plurality of delayed clock signals; A first multiplexer for selecting one of the MRS trim code and the electric fuse trim code and outputting a trim code in response to a trim control signal; And And a second multiplexer for selecting one of the plurality of delayed clock signals in response to the trim code to generate the internal clock signal. The method of claim 1, wherein the input circuit A reference voltage generating circuit for generating said internal reference voltage in response to an MRS trim code and an electrical fuse trim code; An input buffer buffering an input signal in response to the internal reference voltage and generating a second buffered input signal; And And a sampler for sampling the second buffered input signal and generating the first buffered input signal in response to a clock signal. The method of claim 21, wherein the input buffer is Non-volatile semiconductor memory device, characterized in that turned off in response to the enable signal. The method of claim 22, wherein the reference voltage generating circuit A multiplexer for selecting one of the first MRS trim code and the first electric fuse trim code in response to a first trim control signal to output a first trim code; And And a reference voltage generator configured to generate the internal reference voltage having a voltage level that changes in response to the first trim code. The method of claim 2, wherein the input circuit And a trim code generation circuit for generating said first MRS trim code and said first electrical fuse trim code. The method of claim 24, wherein the dream code generation circuit A decoder for decoding the MRS trim update signal; A first register for storing an MRS trim code and outputting the MRS trim code in response to an MRS trim enable signal; A second register for storing the MRS trim code and outputting the MRS trim code in response to the trim update signal; A word line driver circuit for providing the MRS trim code to a nonvolatile semiconductor memory cell in response to the MRS trim update signal; A sense amplifier configured to generate first data by amplifying a first voltage signal corresponding to the MRS dream code from the nonvolatile semiconductor memory cell; And And a third register for storing said first data and generating an electrical fuse trim code. 27. The system of claim 25, wherein the dream code generation circuit And an MRS logic circuit for generating the MRS trim enable signal, the MRS trim update signal, and the MRS trim code in response to command signals. The method of claim 2, wherein the input circuit And a trim code generation circuit for generating the second MRS trim code and the second electrical fuse trim code. Generating an internal reference voltage in response to the first MRS trim code and the first electrical fuse trim code; Generating an internal clock signal in response to the second MRS trim code and the second electrical fuse trim code; Buffering an input signal in response to the internal reference voltage and generating a first buffered input signal; And Sampling the second buffered input signal in response to the internal clock signal and generating a first buffered input signal. 29. The method of claim 28, wherein generating the internal reference voltage Trimming the internal reference voltage; Receiving the input signal; Determining whether a correct input signal has been received; If the received input signal is not a valid input signal, going to trimming the internal reference voltage; Storing the final trim code in a register if the received input signal is a valid input signal; And And writing the final trim code to a nonvolatile semiconductor memory cell. 29. The method of claim 28, wherein generating the internal clock signal Trimming the internal clock signal; Receiving the input signal; Determining whether a correct input signal has been received; If the received input signal is not a correct input signal, going to trimming the internal clock signal; Storing the final trim code in a register if the received input signal is a valid input signal; And And writing the final trim code to a nonvolatile semiconductor memory cell.

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